Presented by Terry C. Shannon to

HP Marketing & BeLux User Group 07-12-04

Publisher,, Shannon Knows HPCShannon Knows HPC

www.shannonknowshpc.com

terry@shannonknowshpc.comterry@shannonknowshpc.com

Presented by Terry C. Shannon to

HP Marketing & BeLux User Group 07-12-04

Publisher,, Shannon Knows HPCShannon Knows HPC

www.shannonknowshpc.com

terry@shannonknowshpc.comterry@shannonknowshpc.com

HP, IPF, and Recent Developments

HP, IPF, and Recent Developments

2

The Fine PrintThe Fine Print The following text reflects legal requirementsThe following text reflects legal requirements

– I am not nor ever have been an HP or Intel EmployeeI am not nor ever have been an HP or Intel Employee– I am not being compensated to deliver a marketing pitchI am not being compensated to deliver a marketing pitch– This presentation reflects my opinion, not HP’s opinionThis presentation reflects my opinion, not HP’s opinion– No NDA material is contained in this presentationNo NDA material is contained in this presentation– I strive for accuracy, but offer no guaranteesI strive for accuracy, but offer no guarantees– Trust but verify: always get a second opinionTrust but verify: always get a second opinion– Make no purchasing decisions based on this sessionMake no purchasing decisions based on this session– Always check with HP before planning your purchasesAlways check with HP before planning your purchases– Above all, enjoy the presentationAbove all, enjoy the presentation– Please excuse my “American English”Please excuse my “American English”– Comments? Email Comments? Email terry@terry@shannonknowshpcshannonknowshpc.com.com

3

Session AgendaSession Agenda

Processor Evolution from 1950 to PresentProcessor Evolution from 1950 to Present From UNIVAC to IntegrityFrom UNIVAC to Integrity

– Current Superdome, PA-RISC and IPF TechnologyCurrent Superdome, PA-RISC and IPF Technology

– Anticipated Improvements in the next few yearsAnticipated Improvements in the next few years Rumours of the death of Itanium are greatly exaggerated.Rumours of the death of Itanium are greatly exaggerated. Extensions are not all things to all peopleExtensions are not all things to all people Why IPF? Why IPF? Why not?Why not? Why HP? Why HP? Who else!Who else!

4

HP’s hardware strategyHP’s hardware strategyHP’s hardware strategyHP’s hardware strategy Hardware Hardware evolution drives the rise of EPICevolution drives the rise of EPIC HP standardizes on Itanium for enterprise systemsHP standardizes on Itanium for enterprise systems AMD Opteron and Intel Nocona enter the pictureAMD Opteron and Intel Nocona enter the picture, ,

delivering 64-bit support to ProLiant systems.delivering 64-bit support to ProLiant systems. Customer choice drives platform selectionCustomer choice drives platform selection Intel Itanium hardware will form the basis of all HP Intel Itanium hardware will form the basis of all HP

enterprise systemsenterprise systems This includes the next-generation Post-Superdome This includes the next-generation Post-Superdome

enterprise server due in ~2008 and new NSK systems enterprise server due in ~2008 and new NSK systems that implement the NSAA.that implement the NSAA.

5

A Chat About CPUsA Chat About CPUsA Chat About CPUsA Chat About CPUs A topic with more misconceptions than factsA topic with more misconceptions than facts Processor evolution keeps pace with technologyProcessor evolution keeps pace with technology Darwin was right… but…Darwin was right… but… Beyond Darwin, there’s always business decisionsBeyond Darwin, there’s always business decisions A 52-year microprocessor journeyA 52-year microprocessor journey

– UNIVAC 1952 – first commercial computerUNIVAC 1952 – first commercial computer– VLSI, incompatibility, and poor marketing killed UNIVACVLSI, incompatibility, and poor marketing killed UNIVAC– IBM subsequently ruled the roost with a wide variety of IBM subsequently ruled the roost with a wide variety of

machines based on a wide variety of architecturesmachines based on a wide variety of architectures..– Incompatibility: scientific or commercialIncompatibility: scientific or commercial– IBM solves the problem in 1964IBM solves the problem in 1964

6

A chat about CPUs, ctdA chat about CPUs, ctd April 7, 1964: IBM debuts System/360 seriesApril 7, 1964: IBM debuts System/360 series

– First commercial microprogrammed computer architectureFirst commercial microprogrammed computer architecture

– Floor wax and a dessert toppingFloor wax and a dessert topping

– First instantiation of a CISC architectureFirst instantiation of a CISC architecture

– Dominated computer design for two decades… even Dominated computer design for two decades… even VAX/VMS… one of most successful CISC architecturesVAX/VMS… one of most successful CISC architectures

– Mainframes are still alive and wellMainframes are still alive and well

– But evolution continues…But evolution continues…

7

A Chat about CPUs, ctd…A Chat about CPUs, ctd…A Chat about CPUs, ctd…A Chat about CPUs, ctd… Improved measurement tools proved that most CISC Improved measurement tools proved that most CISC

programs relied a few simple instructionsprograms relied a few simple instructions IBM sets out to solve the problemIBM sets out to solve the problem

– 1975 – 1979: 1975 – 1979: IBM invents the 801IBM invents the 801– Never commercialized, but the first exemplar of RISCNever commercialized, but the first exemplar of RISC– Developed by Joel Birnbaum, who later did PA-RISCDeveloped by Joel Birnbaum, who later did PA-RISC– A derivative single-chip 801(ROMP) was used in IBM’s first A derivative single-chip 801(ROMP) was used in IBM’s first

commercial RISC system, the PC/RT in 1986, which commercial RISC system, the PC/RT in 1986, which launched concurrently with PA-RISC.launched concurrently with PA-RISC.

– The PC/RT was a commercial failure, but…The PC/RT was a commercial failure, but…– It set the stage for POWER and PowerPCIt set the stage for POWER and PowerPC– CISC was placed at risk by RISCCISC was placed at risk by RISC

8

A Chat about CPUs, ctd…A Chat about CPUs, ctd…A Chat about CPUs, ctd…A Chat about CPUs, ctd… Computer Scientists Recognize RISCComputer Scientists Recognize RISC

– Stanford computer scientistsStanford computer scientists emulated the IBM example of emulated the IBM example of relying on compiler optimization and pipeline efficiency and relying on compiler optimization and pipeline efficiency and produced what became the MIPS architectureproduced what became the MIPS architecture..

– BerkeleyBerkeley focused on minimizing inherently slow calls to focused on minimizing inherently slow calls to external memory with a register rich architecture adopted external memory with a register rich architecture adopted in 1987 by Sun Microsystems and, thus in 1987 by Sun Microsystems and, thus helped productize helped productize the SPARC processorthe SPARC processor

– DEC developed and cancelled PRISM,DEC developed and cancelled PRISM, a scalar/vector a scalar/vector RISC architecture. Big mistake!RISC architecture. Big mistake!

– PRISM was supplanted by a DEC/MIPS joint venturePRISM was supplanted by a DEC/MIPS joint venture, , which ultimately failed. Bigger mistake.which ultimately failed. Bigger mistake.

– DEC then developed AlphaDEC then developed Alpha, a superscalar RISC CPU, a superscalar RISC CPU

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The Rise and Fall of AlphaThe Rise and Fall of AlphaThe Rise and Fall of AlphaThe Rise and Fall of Alpha HP acquired Alpha technology with the CPQ buyHP acquired Alpha technology with the CPQ buy

– For a variety of reasons, not the least of which was For a variety of reasons, not the least of which was marketing malfeasancemarketing malfeasance, Alpha never achieved critical , Alpha never achieved critical mass or commercial success.mass or commercial success.

– Alpha was very successful in real-time and HPTCAlpha was very successful in real-time and HPTC– HP will phase-out AlphaHP will phase-out Alpha after the EV7z release after the EV7z release– PA-RISC will followPA-RISC will follow after final PA-8900 release in 2005 after final PA-8900 release in 2005– SPARC and MIPSSPARC and MIPS are no longer relevant are no longer relevant

New choices: POWER, IPF, and x86 extensionsNew choices: POWER, IPF, and x86 extensions– Today, RISC CPUs power the majority of servers and Today, RISC CPUs power the majority of servers and

workstations, although IA and IBM’s zSeries servers workstations, although IA and IBM’s zSeries servers manage to disguise their RISC DNA quite well.manage to disguise their RISC DNA quite well.

10

Intel gets inside with CICSIntel gets inside with CICSIntel gets inside with CICSIntel gets inside with CICS While the workstation and server market focused on While the workstation and server market focused on

RISC, Intel had plans of its own.RISC, Intel had plans of its own.– Intel developed the first microprocessor in 1971, but waited Intel developed the first microprocessor in 1971, but waited

15 years to begin executing a plan to achieve 15 years to begin executing a plan to achieve microprocessor dominance.microprocessor dominance.

– Remember “Intel Inside” in 1988?Remember “Intel Inside” in 1988? Behind the scenes…Behind the scenes…

– June 8, 1978: Intel launches 8086, a 16-bit CPUJune 8, 1978: Intel launches 8086, a 16-bit CPU– First CPU in the x86 family… vestiges of which remain in First CPU in the x86 family… vestiges of which remain in

the latest Pentium and Xeon processors.the latest Pentium and Xeon processors.– Cost-reduced 8-bit 8088 powered IBM PCCost-reduced 8-bit 8088 powered IBM PC

Enhancement acceleration beginsEnhancement acceleration begins

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Intel processor proliferationIntel processor proliferationIntel processor proliferationIntel processor proliferation First four Intel CPUs bore the 8x86 nameFirst four Intel CPUs bore the 8x86 name Time for “Five-9’s”Time for “Five-9’s”

– 1980: 80186, 8 or 16 bits1980: 80186, 8 or 16 bits– 1982: 80286, 16 bits, 16MB RAM, VM, multitasking1982: 80286, 16 bits, 16MB RAM, VM, multitasking– 1985: 80386: 32 bits, 275M xsistors, 4GB memory1985: 80386: 32 bits, 275M xsistors, 4GB memory– 1989: 80486: on-chip cache and FPU = 2x performance1989: 80486: on-chip cache and FPU = 2x performance

Numbers are out, names are inNumbers are out, names are in– 1983: Pentium 1 3.1M xsistors, 100MIPS1983: Pentium 1 3.1M xsistors, 100MIPS– 1995: Pentium Pro: Intel’s 5.5M xsistor “October Surprise”1995: Pentium Pro: Intel’s 5.5M xsistor “October Surprise”– 1999 Pentium III and Xeon: competitive fear and loathing1999 Pentium III and Xeon: competitive fear and loathing– 2000 Pentium 4 and Xeon double performance, again2000 Pentium 4 and Xeon double performance, again

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What’s Next?What’s Next?What’s Next?What’s Next? Intel increased speed and performance of 32b chipsIntel increased speed and performance of 32b chips Meanwhile, Meanwhile, the time had come for a post-RISC 64 bit the time had come for a post-RISC 64 bit

processorprocessor that eliminated RISC limitations that eliminated RISC limitations An EPIC Adventure BeginsAn EPIC Adventure Begins

– In 1988, HP started to design a long-term RISC CPUIn 1988, HP started to design a long-term RISC CPU

– HP opted to partner with Intel on the effortHP opted to partner with Intel on the effort

– June 3, 1994:June 3, 1994: P7/Merced/Itanium is jointly announced P7/Merced/Itanium is jointly announced

– 2001 debut was four years late, performance lagged2001 debut was four years late, performance lagged

– June 25, 2001 – Compaq scuttles Alpha for ItaniumJune 25, 2001 – Compaq scuttles Alpha for Itanium

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The timing of a processor transitionThe timing of a processor transitionThe timing of a processor transitionThe timing of a processor transition

CPQ wanted to use the EV7 launch to announceCPQ wanted to use the EV7 launch to announce Itanium Itanium as an ”option,” Intel wanted a rapid closure.as an ”option,” Intel wanted a rapid closure.

– In April 2001, Compaq realized 2FQ would be ugly. In April 2001, Compaq realized 2FQ would be ugly. Finalizing the technology transfer by the end of the quarter Finalizing the technology transfer by the end of the quarter would resolve the financial issueswould resolve the financial issues. 25 June was selected, . 25 June was selected, contracts were signed, and a marketing effortcontracts were signed, and a marketing effort commenced commenced in June.in June.

– Compaq endured great wrath from irate Alpha customers.Compaq endured great wrath from irate Alpha customers. But with Alpha no longer the “other woman” in the Intel-But with Alpha no longer the “other woman” in the Intel-Compaq relationship, that relationship improved and Intel Compaq relationship, that relationship improved and Intel got a big-name addition to the Itanium adoption list.got a big-name addition to the Itanium adoption list.

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Alpha Retired, Itanium hiredAlpha Retired, Itanium hiredAlpha Retired, Itanium hiredAlpha Retired, Itanium hired How and why did this happen?How and why did this happen? Darwin was rightDarwin was right ““The Origin of Species” sums it up in two linesThe Origin of Species” sums it up in two lines

– Evolution happensEvolution happens– Only the strong surviveOnly the strong survive

Microprocessor EvolutionMicroprocessor Evolution– Early specialized CPUs replaced by CISCEarly specialized CPUs replaced by CISC– CISC supplanted by RISCCISC supplanted by RISC– EPIC will likely supplant RISCEPIC will likely supplant RISC

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Alpha’s omega Alpha’s omega Alpha’s omega Alpha’s omega

Business, technology, and corporate policyBusiness, technology, and corporate policy– Technology: Alpha as roadmap roadkillTechnology: Alpha as roadmap roadkill– Alpha’s differentiator was Alpha’s differentiator was “twice the performance of Intel”“twice the performance of Intel”

Itanium appeared on Alpha charts long before Intel deliveredItanium appeared on Alpha charts long before Intel delivered Alpha CPU cartographers could better project performanceAlpha CPU cartographers could better project performance Intel could better project Itanium performanceIntel could better project Itanium performance So the following curve reflected Compaq’s expectations for So the following curve reflected Compaq’s expectations for

IntelIntel– Intel invited Compaq to review the Itanium roadmap in 2000Intel invited Compaq to review the Itanium roadmap in 2000

Itanium would achieve performance parity in the EV7 eraItanium would achieve performance parity in the EV7 era and and rapidly extend its performance leadershiprapidly extend its performance leadership

– Without a value proposition, Alpha was toastWithout a value proposition, Alpha was toast

– Compaq used the same 1998 slide through mid-2001Compaq used the same 1998 slide through mid-2001

102030405060708090

100110120130140150160170180190200210220

SP

EC

int9

5

Alpha could only estimate Itanium performance

21164600 MHz

21264.25u

EV7

IA-64(Merced)

21264600 MHz

EV8

Alpha/Itanium roadmap circa 1998

EV68

Alpha will maintain its performance leadership

64-bit capability on WNT well before it debuts on Itanium

1995 1996 1997 1998 91999 2000 2001 20220

EV78

CPU evolution changed the curveCPU evolution changed the curve

EPIC

Superscalar RISC~2 instructions/cycle

performance

RISC< 1 instruction/cycle

.3 ins/cycle

next generation

CISC 20-30% increase per year dueto advances in underlying semiconductor technology

1 micron - > .5 micron --> .35 micron --> .25 micron --> .18 micron --> .13 micron

Itanium®

you are here

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Acts of Omission in Prognostication?Acts of Omission in Prognostication?Acts of Omission in Prognostication?Acts of Omission in Prognostication? Back to the original chart:Back to the original chart: ““It’s difficult to predict, especially the future”It’s difficult to predict, especially the future” Projecting the future performanceProjecting the future performance of one’s own product is of one’s own product is

feasible.feasible. Probability decreasesProbability decreases as distance increases. as distance increases. Projecting the future performance of a rival product is Projecting the future performance of a rival product is

more guesstimation than extrapolationmore guesstimation than extrapolation And And processor evolutionprocessor evolution plays a role plays a role If EPIC is the successor to superscalar RISCIf EPIC is the successor to superscalar RISC Projections may be even less accurate Projections may be even less accurate

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The business of CPU death and lifeThe business of CPU death and life

Alpha’s fate was sealed by the Intel roadmapsAlpha’s fate was sealed by the Intel roadmaps– Alpha already was bound for Death Row because:Alpha already was bound for Death Row because:

Sales volumes were decreasingSales volumes were decreasing It cost Compaq $800USD for each processor it shippedIt cost Compaq $800USD for each processor it shipped The EV8 effort required additional resourcesThe EV8 effort required additional resources

– Negotiations, Alphacide, and Itanium risingNegotiations, Alphacide, and Itanium rising Itanium was Compaq’s chosen Alpha successor, Intel Itanium was Compaq’s chosen Alpha successor, Intel

wanted Alpha out of the picture, negotiations were held.wanted Alpha out of the picture, negotiations were held. The result: The result: Compaq granted Intel nonexclusive rights to Compaq granted Intel nonexclusive rights to

use and modify the Alpha architecture, and provide all use and modify the Alpha architecture, and provide all Alpha IP. Alpha developers were offered jobs at Intel. Alpha IP. Alpha developers were offered jobs at Intel. Compaq agreed to adopt Itanium as the successor to Compaq agreed to adopt Itanium as the successor to Alpha when all EV7 work was done.Alpha when all EV7 work was done.

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EPIC Addresses Alpha LimitationsProblem Itanium®

Architecture Alpha Comments

Branch Mispredicts

Predication Conditional Move (CMOVE) Dual Algorithm Branch Predictor (EV6)

Branchless If-Then-Else at cost of increased I-Stream Bandwidth Reduced Branch Mis-Predicts

Memory Latency Explicit Speculative Load

Explicit Memory Prefetch (Prefetch) Speculative Load

Allows compiler to move load to earlier block Allows speculative loads outside view of compiler

Explicit vs Implicit Parallelism

128 Integer Registers

32 Integer Registers + 48 Shadow Registers

Allows compiler to directly schedule all registers at cost of increased context switch Large register count without save/restore overhead. Shadow register count can grow in future implementations

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EPIC: Basic Ideas for a New ArchitectureEPIC: Basic Ideas for a New ArchitectureEPIC: Basic Ideas for a New ArchitectureEPIC: Basic Ideas for a New Architecture

EPIC = Explicitly Parallel Instruction ComputingEPIC = Explicitly Parallel Instruction Computing Static hardware designStatic hardware design

– Compiler creates record of executionCompiler creates record of execution– Instructions arranged in “bundles”Instructions arranged in “bundles”– The EPIC CPU “plays the record”The EPIC CPU “plays the record”– No runtime changes as with out of order executionNo runtime changes as with out of order execution

High scalability of execution unitsHigh scalability of execution units– Very Long Instruction Word (VLIW) conceptVery Long Instruction Word (VLIW) concept– Focus is parallelismFocus is parallelism– 6 instructions in parallel (2 bundles per cycle)6 instructions in parallel (2 bundles per cycle)– High number of execution unitsHigh number of execution units

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Explicit parallelism explainedExplicit parallelism explainedExplicit parallelism explainedExplicit parallelism explained

Instruction Level Parallelism (Instruction Level Parallelism (ILPILP) = ability to execute ) = ability to execute multiple instructions concurrently. multiple instructions concurrently.

Explicitly Parallel Instruction Computing Explicitly Parallel Instruction Computing ((EPICEPIC) allows the ) allows the compiler or assembler to specify the parallelismcompiler or assembler to specify the parallelism

– Compiler specifies Compiler specifies Instruction Group,Instruction Group, list of instructions list of instructions with no dependencies that can be executed in parallelwith no dependencies that can be executed in parallel

– Instructions are packed in Instructions are packed in bundlesbundles of 3 instructions each of 3 instructions each Instruction bundle - two executed per cycleInstruction bundle - two executed per cycle

Massive resources on chipMassive resources on chip– Large number of registers to avoid register contentionLarge number of registers to avoid register contention

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compiler

compiler

implicitly parallel

implicitly parallel

hardware

......

......

execution units unused – reduced efficiency

sequential machine code

Traditional architecture

multiple execution units

original source

code

Itanium-based

compiler

......

......

parallel machine code

Itanium architecture

massive resource

s

original source

code

Itanium Architecture – Basic IdeasItanium Architecture – Basic Ideas

Increased parallelization – more throughput

IA-32

IA-64IA-64

ItaniumItanium**

IA-32 expands leading edge

performance for volume segments

IA-64 enhances IA

with world class performance for

workstations and servers and

full compatibility

A Unified CPU Architecture – 32 Bits and 64 Bits

PentiumPentium®® Pro ProPentiumPentium®® II II

Pentium IIIPentium III

Pentium II XeonPentium II Xeon

. . .

.. .

. .

FosterFoster

CascadesCascades

Itanium 2Itanium 2

MadisonMadisonIA64-PerfIA64-Perf

Hondo

Montecito

Future IA32

GallatinGallatinPentium-MPentium-M

Tukwila

. . . . . .

. . .

. . . . . .

. . .

. .

Intel architecture roadmap

We are Here

25

Things were looking good for ItaniumThings were looking good for Itanium

Itanium finally arrivesItanium finally arrives– Unfashionably lateUnfashionably late

– Disappointing in performanceDisappointing in performance

McKinley successor arrives a year laterMcKinley successor arrives a year later– HP takes charge of compiler developmentHP takes charge of compiler development

– Higher performance, broader acceptanceHigher performance, broader acceptance

– Products begin to proliferate, HP Integrity thrust beginsProducts begin to proliferate, HP Integrity thrust begins

Madison debut imminentMadison debut imminent– Performance projections portended leadershipPerformance projections portended leadership

Then along comes 18 February 2004Then along comes 18 February 2004

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IIII Breaking News from Spring Breaking News from Spring

2004 IDF Conference2004 IDF Conference– HP will offer AMD Opteron HP will offer AMD Opteron

and Intel Nocona x86 CPUs and Intel Nocona x86 CPUs with 64-bit extensions on with 64-bit extensions on select ProLiant models.select ProLiant models.

– HP’s commitment to Xeon & HP’s commitment to Xeon & Itanium as strategic industry Itanium as strategic industry standard platforms for the standard platforms for the future is unchanged.future is unchanged. Integrity forIntegrity for enterprise enterprise

scalability and scalability and performanceperformance

Itanium NSK systemsItanium NSK systems get get NSAA performance gainsNSAA performance gains

Itanium still intact and on trackItanium still intact and on track

Fister and Robison

Itanium interruptus? No way!

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What is 64-bit Extension Technology?What is 64-bit Extension Technology?

Evolutionary IA-32 architectural enhancements to support extended memory starting in mid ’04

Evolutionary IA-32 architectural enhancements to support extended memory starting in mid ’04

Additional Registers8-SSE & 8-Gen Purpose

Additional Registers8-SSE & 8-Gen Purpose

Double Precision (64-bit) Integer Support

Double Precision (64-bit) Integer Support

Extended Memory Addressability

64-Bit Pointers, Registers

Extended Memory Addressability

64-Bit Pointers, Registers

++ ==With 64-Bit Extension

Technology

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And what do extensions give me?And what do extensions give me?

More choice in the ProLiant spaceMore choice in the ProLiant space– Compaq developed, but didn’t ship, an Alpha ProLiantCompaq developed, but didn’t ship, an Alpha ProLiant– Opteron option available now, Nocona nextOpteron option available now, Nocona next– Consistent design across all ProLiant product linesConsistent design across all ProLiant product lines, so you won’t , so you won’t

see anything radically new in the new boxes.see anything radically new in the new boxes.– Systems currently offered in three form factorsSystems currently offered in three form factors

100 series – economy-class HPC100 series – economy-class HPC 500 series - 4P performance for power-starved apps 500 series - 4P performance for power-starved apps BL series - B lades run cool, use less fuel are great for HPTCBL series - B lades run cool, use less fuel are great for HPTC

– Benefits both 32b and 64b usersBenefits both 32b and 64b users Linux and Solaris supported in 64-bit mode, Windows Linux and Solaris supported in 64-bit mode, Windows

someday.someday. 32-bit users can address as much as 64b of memory while 32-bit users can address as much as 64b of memory while

gaining a performance boost.gaining a performance boost.

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What do else do extensions provide?What do else do extensions provide?

64-bit wide64-bit wide general purpose registers, instruction general purpose registers, instruction pointer and operations pointer and operations

48-bits of virtual addressing48-bits of virtual addressing in first products in first products Up to 40-bits physical addressingUp to 40-bits physical addressing

– Nocona & future Prescott 36-bits (64 GB)Nocona & future Prescott 36-bits (64 GB)– Potomac 40-bits (1 TB)Potomac 40-bits (1 TB)

Flat virtual addressingFlat virtual addressing space space Instruction pointer Instruction pointer relative addressing moderelative addressing mode 8 new general purpose registers8 new general purpose registers (GPR) (GPR) 8 new SSE registers8 new SSE registers (128-bit) (128-bit)

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X86 extensions benefit many…X86 extensions benefit many…X86 extensions benefit many…X86 extensions benefit many…

64-bit computing is inevitable, and now it’s sooner64-bit computing is inevitable, and now it’s sooner

x86 with 64-bit extension technology will speed the x86 with 64-bit extension technology will speed the development of a full 64-bit ecosystem development of a full 64-bit ecosystem

– Day one Linux and Solaris support, Windows someday.

– Accelerating 32-bit to 64-bit apps upgrade rates

– 32-bit apps freed 4GB addressing limit of 32-bit CPUs

– And an unintended consequence for ItaniumAnd an unintended consequence for Itanium

Intel must increase the frequency and magnitude of Intel must increase the frequency and magnitude of Itanium price cuts to compete in volume marketItanium price cuts to compete in volume market

Intel’s loss is Itanium customers’ gainIntel’s loss is Itanium customers’ gain

So why bother with Itanium?

31

Another Unintended ConsequenceAnother Unintended Consequence Microsoft admits delay of Win64 on x86-extendedMicrosoft admits delay of Win64 on x86-extended From 4CQ04 to 1H05, Microsoft Standard TimeFrom 4CQ04 to 1H05, Microsoft Standard Time Converted to Julian calendar, this means 2006Converted to Julian calendar, this means 2006 Hence x86 with extensions poses no immediate threat in Hence x86 with extensions poses no immediate threat in

1-8 way Windows space1-8 way Windows space Bad news for Opteron and NoconaBad news for Opteron and Nocona Good news for ItaniumGood news for Itanium Itanium has a shot at the high-volume marketplace it Itanium has a shot at the high-volume marketplace it

needs to achieve volume and market shareneeds to achieve volume and market share

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Why should I bother with Itanium?Why should I bother with Itanium?

X86 extensions are not all things to all people, except in X86 extensions are not all things to all people, except in press articlespress articles..

There’s plenty of areas in which Itanium adds value. One There’s plenty of areas in which Itanium adds value. One area reflects the EPIC architecture.area reflects the EPIC architecture.

EPIC PerformanceEPIC Performance– Freedom from RISC limits deliver lower latency and higher Freedom from RISC limits deliver lower latency and higher

throughputthroughput

– High performance through parallelizationHigh performance through parallelization• Up to 2x performance per clock cycleUp to 2x performance per clock cycle

• Massive on-chip resources to boost apps performanceMassive on-chip resources to boost apps performance

• Lower memory latency gap with shorter pipelinesLower memory latency gap with shorter pipelines

What? Extensions are not a panacea?What? Extensions are not a panacea?

33

What else can Itanium do?What else can Itanium do?

Itanium can go places where x86 isn’t an option.Itanium can go places where x86 isn’t an option. Enterprise supportEnterprise support If you’re an enterprise user who wants a system larger If you’re an enterprise user who wants a system larger

than 8P and you require support for VMS, NSK or Tru64 than 8P and you require support for VMS, NSK or Tru64 Unix, Itanium provides all of the above, as well as 64-bit Unix, Itanium provides all of the above, as well as 64-bit Unix and windows.Unix and windows.– Indeed, you can run four of these OSes concurrently in Indeed, you can run four of these OSes concurrently in

separate hard partitions on a Superdome.separate hard partitions on a Superdome.

– Due to architectural necessity, NSK requires its own box, Due to architectural necessity, NSK requires its own box, but it remains key component of HP’s AE strategy.but it remains key component of HP’s AE strategy.

As a new architecture, EPIC is built to last…As a new architecture, EPIC is built to last…

35

Choose Your Weapon… or CPUChoose Your Weapon… or CPUChoose Your Weapon… or CPUChoose Your Weapon… or CPU

IF… IF… a 1P to 8P ProLiant running Linux or Solaris, a 1P to 8P ProLiant running Linux or Solaris, and someday Windows 64and someday Windows 64 meets your needs… meets your needs…

THEN… THEN… Opteron and Nocona are a good choiceOpteron and Nocona are a good choice IF… IF… you need a 1 to 128P enterprise systemyou need a 1 to 128P enterprise system that that

can run HP-UX, NSK, or VMS as well as the can run HP-UX, NSK, or VMS as well as the commodity OSes listed above while delivering commodity OSes listed above while delivering superior RAS and manageability capabilities…superior RAS and manageability capabilities…

THEN: THEN: HP Integrity and Itanium are for youHP Integrity and Itanium are for you!!

36

Some “pressing” architectural issuesSome “pressing” architectural issues Freedom of the press: upsides are manyFreedom of the press: upsides are many Downside (from some experienced in the trade)Downside (from some experienced in the trade)

– During the past 20 years, the During the past 20 years, the US trade press has shown a US trade press has shown a significant decline in qualitysignificant decline in quality

– The job of a reporter is to report facts, not gather a few facts The job of a reporter is to report facts, not gather a few facts and, report their opinionsand, report their opinions as statements of fact. as statements of fact.

– Jumping to a conclusion is one thing, but any journalist who Jumping to a conclusion is one thing, but any journalist who makes quantum leaps to conclusions needs firing. makes quantum leaps to conclusions needs firing.

ConclusionsConclusions– Failure to stick to the facts can injure a person or business Failure to stick to the facts can injure a person or business

or lead to misunderstandings among readersor lead to misunderstandings among readers. .

37

The press makes an EPIC assumptionThe press makes an EPIC assumptionThe press makes an EPIC assumptionThe press makes an EPIC assumption ““X86 with extensions is equivalent to EPIC”X86 with extensions is equivalent to EPIC”

– Completely inaccurate, but a good example of coming to a Completely inaccurate, but a good example of coming to a conclusion before checking all of the facts.conclusion before checking all of the facts.

A few facts the press failed to considerA few facts the press failed to consider– Extending a 25-year-old 32-bit architectureExtending a 25-year-old 32-bit architecture to support to support

extended memory addressing and 64-bit versions of two extended memory addressing and 64-bit versions of two volume OSes volume OSes does not render Opteron or Nocona the equal of does not render Opteron or Nocona the equal of Itanium.Itanium.

– Opteron and Nocona lack the scalability and RAS capabilities Opteron and Nocona lack the scalability and RAS capabilities required by enterprise systems.required by enterprise systems. Opteron and Nocona do not support enterprise OSes (other than Opteron and Nocona do not support enterprise OSes (other than

Solaris). There are no plans to port VMS or NSK or HP-UX to Solaris). There are no plans to port VMS or NSK or HP-UX to these platforms, and feasibility of doing so is unknown.these platforms, and feasibility of doing so is unknown.

38

How do extensions affect HP? How do extensions affect HP? How do extensions affect HP? How do extensions affect HP?

• Does this change HP’s industry standard server or Itanium Does this change HP’s industry standard server or Itanium processor strategy?processor strategy?

• No.No. The ProLiant strategy is validated, and Itanium remains The ProLiant strategy is validated, and Itanium remains the 64-bit enterprise CPU of choice.the 64-bit enterprise CPU of choice.

• Is Is Integrity and ProLiant positioningIntegrity and ProLiant positioning a big problem? a big problem?

• NoNo. Differentiating low-end Integrity and ProLiant products is . Differentiating low-end Integrity and ProLiant products is now an issue. now an issue. Overlapping capabilities in the 1P to 8P space Overlapping capabilities in the 1P to 8P space reduces HP’s ability to differentiate its low-end systems based reduces HP’s ability to differentiate its low-end systems based on CPU counton CPU count. Customers will choose the product that best fits . Customers will choose the product that best fits their needs.their needs.

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Itanium impactItanium impactItanium impactItanium impact Will this affect the Will this affect the acceptance of Itanium CPUs?acceptance of Itanium CPUs?

– Slightly, but not to the extent that adoption rates will be Slightly, but not to the extent that adoption rates will be impacted in Linux HPTC clusters and the low end marketimpacted in Linux HPTC clusters and the low end market defined by CPU count and OS support. If an 8P system defined by CPU count and OS support. If an 8P system supporting 64-bit Linux or Solaris meets a customer’s supporting 64-bit Linux or Solaris meets a customer’s needs, Opteron or Nocona is a cost-effective solution.needs, Opteron or Nocona is a cost-effective solution.

What about the What about the Itanium adoption ratesItanium adoption rates??– They will not meet Intel’s expectations in the near term, as They will not meet Intel’s expectations in the near term, as

Intel wanted the volume market. Intel wanted the volume market. The only way Intel can The only way Intel can enter this market is by accelerating the frequency and enter this market is by accelerating the frequency and magnitude of its Itanium price cutsmagnitude of its Itanium price cuts. Customers will get . Customers will get faster Itanium systems soonerfaster Itanium systems sooner

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Itanium distinguishing featuresItanium distinguishing featuresItanium distinguishing featuresItanium distinguishing features Performance through ParallelizationPerformance through Parallelization

– Advantage: Up to 2x performance per clock cycleAdvantage: Up to 2x performance per clock cycle– Proof point:Proof point: Best SpecFP Best SpecFP

Massive On-chip ResourcesMassive On-chip Resources– Advantage Imaging, rich data, voice, encryptionAdvantage Imaging, rich data, voice, encryption– Proof point:Proof point: Superior Linpack results Superior Linpack results

Business Critical AvailabilityBusiness Critical Availability– Advantage: Machine check architectureAdvantage: Machine check architecture

Inherent protection and security featuresInherent protection and security features

Shorter pipelines beat the memory latency gapShorter pipelines beat the memory latency gap– Advantage: SMP complex workloads: OLTP, data mining Advantage: SMP complex workloads: OLTP, data mining

Proof point: TPC-C, TPC-H benchmarksProof point: TPC-C, TPC-H benchmarks

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64-bit computing becomes pervasive4p server memory will exceed 1 TB by 20074p server memory will exceed 1 TB by 2007

Applications are a driving force to 64-bit Applications are a driving force to 64-bit computingcomputing

– Real time security - Biometrics, encryption, virus Real time security - Biometrics, encryption, virus scanningscanning

– Huge data warehousing (database and data mining)Huge data warehousing (database and data mining)– Rich data types, complex technical workloadsRich data types, complex technical workloads

0

200

400

600

800

1000

1200

GB

8 GB 16 GB 32 GB64 GB128 GB*

* future

512 GB*

1 TB*

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Itanium Processor

Itanium2 / McKinley / Madison

System Bus64 bits wide133MHz/266 MT/s2.1 GB/s

Width2 bundles per clock4 integer units2 load or stores per clock9 issue ports

CachesL1 – 2X16KB - 2 clock latencyL2 – 96K – 12 clock latencyL3 - 4MB external –20 clk 11.7 GB/s bandwidth

Addressing44 bit physical addressing50 bit virtual addressingMaximum page size of 256MB

System BusSystem Bus

Core800 MHz

L3 Cache BSBBSB

System Bus128 bits wide200MHz/400 MT/s6.4 GB/s

50% Increase in Clock Rate

Width2 bundles per clock6 integer units2 loads and 2 stores per clock11 issue ports

CachesL1 – 2X16KB - 1 clock latencyL2 – 256K – 5 clock latencyL3 - 3MB / 6MB – 12 clk 32 GB/s bandwidth

Addressing50 bit physical addressing64 bit virtual addressingMaximum page size of 4GB

Core1 GHz

L3 Cache

System BusSystem Bus

Itanium evolution – First 3 IterationsItanium evolution – First 3 Iterations

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At HP, Itanium and standards rule!At HP, Itanium and standards rule!At HP, Itanium and standards rule!At HP, Itanium and standards rule! HP has the most complete portfolio of any vendor HP has the most complete portfolio of any vendor

offering Itanium solutionsoffering Itanium solutions For example:For example:

– HardwareHardware– ApplicationsApplications– Migration toolsMigration tools– Assessment servicesAssessment services– Online assistanceOnline assistance

And it’s working: And it’s working: HP Integrity sales are growingHP Integrity sales are growing

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Recent Integrity AnnouncementsRecent Integrity AnnouncementsRecent Integrity AnnouncementsRecent Integrity Announcements

3 November 2003: HP Fleshes Out Integrity Line… New products include…

– Itanium-based HP Integrity rx4640 4P server

– Itanium-based HP Integrity rx7620 8P server

– Itanium-based HP Integrity rx8620 16P midrange servers

The rx7620 and rx8620 servers feature the Superdome The rx7620 and rx8620 servers feature the Superdome cellular architecture, and thus are “Superdome Juniors.” cellular architecture, and thus are “Superdome Juniors.” CPU capacity can be doubled on cellular systems with CPU capacity can be doubled on cellular systems with the new Hondo module.the new Hondo module.

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More Recent AnnouncementsMore Recent AnnouncementsMore Recent AnnouncementsMore Recent Announcements Also announced was the cost-reduced HP ProLiant 100 server

series, including its first member, the ProLiant 140, then the Opteron-based 145 and 585.

And HP addressed the HPTC community with the

HP XC6000 cluster, based on Integrity rx2600 systems

HP XC3000 cluster is based on HP ProLiant servers.

Both clusters support up to 512 nodes

Both support high-speed interconnects from Quadrics LTD and Myricom.

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Even More Recent AnnouncementsEven More Recent AnnouncementsEven More Recent AnnouncementsEven More Recent Announcements

A Quintet of dual-CPU Nocona-Inside ProLiants– The ProLiant DL380 G4, the most popular ProLiant, a 2U rack

server two 3.4GHz Nocona CPUs and 1GB of memory.

– The ProLiant DL360 G4, a Intel alternative to the DL145, a 1U server with up to two 3.0 GHz Nocona CPUs and up to 1GB of memory.

– The ProLiant ML370 G4, the next generation of HP’s most expandable DP ProLiant, supports two 3.4GHz Nocona CPUs, and up to 1GB of memory

– The ProLiant ML350 G4, a Nocona-enhanced member of the ProLiant ML-Series that supports two 3.0GHz Xeon Intel EM64T-equipped processors and 512MB of memory.

– The ProLiant BL20p G3, a Nocona server blade with 3.2GHz Xeon Intel EM64T CPUs and 1GB of memory.

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NSK Users: New Itanium-based HP NSAANSK Users: New Itanium-based HP NSAA

Intel Itanium processors and Intel Itanium processors and Integrity board sets enable Integrity board sets enable new design that delivers new design that delivers better fault tolerancebetter fault tolerance

Individual microprocessors Individual microprocessors on a four-processor “slice” on a four-processor “slice” run as separate CPUsrun as separate CPUs

Recovers transparently Recovers transparently from multiple hardware from multiple hardware or software faultsor software faults

= logical synchronization units*

ServerNet

*

1

2

0

3

1 20 3

1

2

0

3

HP Integrity architecture is the HP Integrity architecture is the foundation for the industry’s foundation for the industry’s leading fault-tolerant solutionleading fault-tolerant solution

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Why IPF… And Why HP?Why IPF… And Why HP?

IPF is the logical RISC successorIPF is the logical RISC successor Intel and HP co-developed ItaniumIntel and HP co-developed Itanium Both firms depend on ItaniumBoth firms depend on Itanium Itanium will get annual “speed bumps”Itanium will get annual “speed bumps” HP has the industry’s broadest portfolio ofHP has the industry’s broadest portfolio of

– IPF systems and future IPF systemsIPF systems and future IPF systems

– ApplicationsApplications

– OS supportOS support

– Customer supportCustomer support

So why NOT IPF… and why NOT HP?So why NOT IPF… and why NOT HP?

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Q &A on Recent DevelopmentsQ &A on Recent Developments

Itanium relegated to high endItanium relegated to high end HP financialsHP financials Imminent downsizingImminent downsizing The “death” of UDCThe “death” of UDC Virtualization with VERITASVirtualization with VERITAS TruCluster ImpactTruCluster Impact HP-UX ImpactHP-UX Impact