uninterupted dc power supply through brownout methodology

hierarchical design methodology in fpga

presented by

p.naveen sai (15937)

m.leela mukund (15938)

s.shashikanth reddy (16179)contents

IntroductionWhy hierarchical design methodology?SolutionPros and consCompanies that implements this methodologyReferences

INTRODUCTIONHierarchical design(HD) is an advanced design methodology implemented on complex FPGAsHD addresses the problems of long implementation runsThe designer can break up the design into smaller logical blocksEast block operates independently

WHY HIERARCHICAL DESIGN METHODOLOGY ?To achieve potential physical implementation problems prior to place and routeUsing this methodology it is no longer necessary to run place and route on the entire flatten design , each time the designer makes a small change With flat methodologies it is common to kickoff Multiple routing runs Random seed values

continued.. This method produces acceptable timing resultsIt reduces number of back end iterationsIt is stableSolution

A floor planning is created and proper analysis is done

This interconnecting methodology implements one acceptable timing routeImproves performance continued.

proper integrated floor planning fixesTiming knotsLong critical pathsComplex clocking schemesHigh fan outControlling the utilization of desired space is seen in this methodology

It is an important aspect of FPGA designVolume production plays a vital role hereIt is much easier through block level techniques of a hierarchical design methodologySome designers leave ample amount of space while designing the FPGA for upgrades.

Controlling utilizationIntellectual property(IP) flowDesigners can split their work into smaller, more manageable, block-based pieces, these blocks are called IP blocksIP blocks can be reused from previous designs Designers can freeze the placement within these blocks so that timing, power, and other physical characteristics are fixed and known to meet their requirementsDesigners will quickly connect these blocks to form larger, more complex designs that meet their physical requirementsEach component of logic block of the FPGA design meets their timing requirements.

The new FPGA design paradigm

Pros:

Improves design performanceShortens connectivity lengthsTiming problems can be identified earlierAdjustments can be made without interrupting the designTiming analysis results are in minutes instead of waiting for hours

Cons:

Needs more design resourses for the design and place and route on multiple blocksNeed to budget the timing and clock trees on each level of blockSometimes a tool may not be able to handle a large chip in a flat level Companies that implements this methodology

Xilinx IncAlteraIntevacReferenceswww.eetimes.comwww.xilinx.comwww.altera.com