prepared by ins. arwa al-issa · 2014. 4. 18. · to add a port, click the new button and type the...
TRANSCRIPT
Prepared By Ins. Arwa Al-Issa
I.Arwa Al-Issa
The purpose of this program is to write a correct verilog code that represent the primitive gates.
Verilog Structure:
1. Start with module and ends with endmodule.
2. Input and Output variables.
3. Wires.
4. The primitive gates: NOT, AND, OR, NAND, NOR, XOR,XNOR
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module AND2gate(A, B, F);
input A;
input B;
output F;
and (F, A, B);
endmodule
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Verilog Code representation Gate
not (notA, A) A’ NOT
and (F,A,B) F=A . B AND
or (F,A,B) F=A + B OR
nand (F,A,B) F=(A . B)’ NAND
nor (F,A,B) F=(A + B)’ NOR
xor (F,A,B) F=A B XOR
xnor (F,A,B) F=(A B)’ XNOR
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F Y X
0 0 0
0 1 0
0 0 1
1 1 1
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0 0 0 0 0
0 1
1 0
1 1 1
Starting Active DHL
“Verilog”
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Define the following ports: Input Ports: - X - Y
Output Port: - F
Click the Finish button.
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To add a port, click the New button and type the name of a port.
To change a port type, click the appropriate button in the Port direction box. There are four types: In Out Inout Buffer
To remove any port, click its name on the list and click the Delete button.
To create a bus, add a new port name and click the Array Indexes arrows to specify the bus width.
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F Y X
0 0 0
0 1 0
0 0 1
1 1 1
implement the following function in Verilog:
F=BC+ABC
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F A’BC’ BC C’ A’ C B A
0 0 0 1 1 0 0 0
0 0 0 0 1 1 0 0
1 1 0 1 1 0 1 0
1 0 1 0 1 1 1 0
0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 1
0 0 0 1 0 0 1 1
1 0 1 0 0 1 1 1
module Function(A, B,C, F); input A, B, C; output F; wire notA , notC; wire Y1, Y2; and (Y1,B,C); not (notA, A); not (notC, C); and (Y2, notA, B , notC); or (F, Y1, Y2); endmodule
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Thanks
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