preliminary specification ks0708 64com/128seg drive … notes/samsung/ks0708.pdf · 2017. 6. 5. ·...

PRELIMINARY SPECIFICATION

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708

1M/M-96-D00197-09-19

INTRODUCTION

KS0708 is a single-chip LCD driver LSI for liquid crystal dot-matrix graphic display systems. It incorporates192 driver circuit for 64 commom and 128 segment and 64x128-bit bit-map RAM. It is capable of interfac-ing with the microprocessor, accepting 8-bit parallel display data directly from it, and storing data in anonechip Display Data RAM. And it generates internal signals for using LCD driving independent of micro-processor clock.

FEATURES

¡Ü 64-Channel COMMON & 128-Channel SEGMENT Driver for DOT matrix LCD¡Ü On-chip display data RAM : 64 X 128 = 8192bits¡Ü Display data is stored in display data RAM from MPU - RAM bit data : ON(1), OFF(0)¡Ü Internal timing generator circuit for dynamic display¡Ü 8-bit parallel bi-directional data bus¡Ü Applicable LCD duty : 1/64¡Ü Power supply voltages : Power supply voltage range : 4.5 ~ 5.5 V(VDD) LCD Driving voltage range : 8.0 ~ 17.0 V(VLCD = VDD - VEE)¡Ü Wide operating temperature range : Ta = -30 ¡É ~ 85¡É¡Ü High Voltage CMOS process¡Ü Package : available bumped chip



2M/M-96-D00197-09-19

BLOCK DIAGRAM

64 CHANNELSEGMENT

DRIVER

64 CHANNELSEGMENT

DRIVER

32CHANNELCOMMONDRIVER

32BITSHIFT REG

32CHANNELCOMMON

32BITSHIFT REG

64-BIT DATA LATCH 64-BIT DATA LATCH

DISPLAY DATA RAM64 X 64 = 4,096 BITS

DISPLAY DATA RAM64 X 64 = 4,096 BITS

PAG

E &

LINE

Decoder

PAG

E &

LINE

Decoder

Column Decoder Column Decoder

RAM Address register RAM Address register

INSTRUCTIONDECODER

INSTRUCTIONDECODER

ISTATUSREGISTER

STATUSREGISTER

I/O REGISTER I/O BUFFERI/O BUFFER

OSCILLATOR

DISPLAYTIMING

GENERATORCIRCUIT

C1 ... C32 S1 S2 ... S63 S64 S65 S66 ... S127 S128 C33...C64... ... ... ...

SHLPCLK2

VDDV0V1V2V3V4V5

VEE

VSS

FS

CCR

R

ADC

CS

1B

DB0 ~ DB7

RE

SE

TB

E RS

RW

CS

2B

4



3M/M-96-D00197-09-19

PAD CONFIGURATION

219

218

250

1

86

85

54

53

Y

X(0,0)

KS0708(TOP VIEW)

ITEM PAD NO...SIZE

UNITX Y

CHIP SIZE - 12590 3630

¥ìm

PAD PITCH - 90(MIN)

BUMPED PAD SIZE

1 ~ 53 56 140

54 ~ 85 140 56

86 ~ 218 56 140

219 ~ 250 140 56

BUMPED PAD HEIGHT ALL PAD 18 ¡¾ 3

. . . .



4M/M-96-D00197-09-19

PAD LOCATION

PADNO.

PADNAME X Y PAD

NO.PAD

NAME X Y PADNO.

PADNAME X Y PAD

NO.PAD

NAME X Y

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263

DUMMYDUMMYDUMMY

VEEVEEVEEV5V5V5V4V4V4V3V3V3V2V2V2V1V1V1V0V0V0

VDDVDDVDDVSSVSSVSS

PCLK2FS

SHLADCCS2B

CCRR

DB0DB1DB2DB3DB4DB5DB6DB7RSRWE

CS1BRESETBDUMMYDUMMY

C1C2C3C4C5C6C7C8C9C10

-6115-6025-5935-5477-5257-5037-4817-4597-4377-4157-3937-3717-3497-3277-3057-2837-2617-2397-2177-1957-1737-1517-1297-1077-857-637-417-19723243463683903112313431563178320032175246727593051334336353927421945594779499952195439602561156115611561156115611561156115611561156115

-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600-1600

-1386.5-1296.5-1206.5-1116.5-1026.5-936.5-846.5-756.5-666.5-576.5

646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126

C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

DUMMYDUMMY

S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15S16S17S18S19S20S21S22S23S24S25S26S27S28S29S30S31S32S33S34S35S36S37S38S39

611561156115611561156115611561156115611561156115611561156115611561156115611561156115611561156025571556255535544553555265517550854995490548154725463545454455436542754185409540053915382537353645355534653375328531953105301529252835274526552565247523852295

-486.5-396.5-306.5-216.5-126.5-36.553.5143.5233.5323.5413.5503.5593.5683.5773.5863.5953.51043.51133.51223.51313.51403.516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635

127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189

S40S41S42S43S44S45S46S47S48S49S50S51S52S53S54S55S56S57S58S59S60S61S62S63S64S65S66S67S68S69S70S71S72S73S74S75S76S77S78S79S80S81S82S83S84S85S86S87S88S89S90S91S92S93S94S95S96S97S98S99S100S101S102

2205211520251935184517551665157514851395130512151125103594585576567558549540531522513545-45-135-225-315-405-495-585-675-765-855-945-1035-1125-1215-1305-1395-1485-1575-1665-1755-1845-1935-2025-2115-2205-2295-2385-2475-2565-2655-2745-2835-2925-3015-3105-3195-3285-3375

163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635

190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250

S103S104S105S106S107S108S109S110S111S112S113S114S115S116S117S118S119S120S121S122S123S124S125S126S127S128

DUMMYDUMMYDUMMY

C64C63C62C61C60C59C58C57C56C55C54C53C52C51C50C49C48C47C46C45C44C43C42C41C40C39C38C37C36C35C34C33

-3465-3555-3645-3735-3825-3915-4005-4095-4185-4275-4365-4456-4545-4635-4725-4815-4905-4995-5085-5175-5265-5355-5445-5535-5625-5715-5935-6025-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115-6115

16351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635163516351635

1403.51313.51223.51133.51043.5953.5863.5773.5683.5593.5503.5413.5323.5233.5143.553.5-36.5-126.5-216.5-306.5-396.5-486.5-576.5-666.5-756.5-846.5-936.5-1026.5-1116.5-1206.5-1296.5-1386.5



5M/M-96-D00197-09-19

PAD DESCRIPTION

Power Supply

Name I/O Description

VDD Supply Power supply

VSS Supply Ground

VEE Supply For LCD driver circuit

V0, V1V2, V3V4, V5

SupplyLCD driver supply voltagesThe voltages must satisfy the following relationshipVDD ¡Ã V0 ¡Ã V1 ¡Ã V2 ¡Ã V3 ¡Ã V4 ¡Ã V5 ¡Ã VEE


C

CR

R

O

I

O

RC Oscillator¥¡) Internal clock

¥¢) External clock

FS I

Frequency SelectionWhen the frame frequency is 70Hz, the oscillation frequency should be asfollowing table.

Oscillator

KS0708

CR CRRf : 47k¥ØCf : 20pF

CfRf

KS0708

CR CR

OPEN Open

FS - Oscillation Frequency

1 fose = 430 kHz

0 fosc = 215kHz

External clock



6M/M-96-D00197-09-19

Microprocessor Interface


CS1B I First Chip(S1 ~ S64) Select input.Data input/output is enabled via E, RS, RW, and DB[0:7]when CS1B = Low.

CS2B I Second Chip(S65 ~ S128) Select input.Data input/output is enabled via E, RS, RW, and DB[0:7] when CS2B = Low.

RS I Register Selection - HIGH : The data in DB[7:0] is display data - LOW : The data in DB[7:0] is control data

RW I

Read or Write

E

Enable signal.

DB0 ~ DB7 I/0 Data Bus [0 ~ 7] - Bi-directional data bus

RW Description

H Data appears at DB< 7:0 > when E = High.

L Display data DB < 7:0 > can be written at falling edge of E.

RW Description

H Read data in DB< 7:0 > appears the while E is high level.

L Display data DB < 7:0 > is latched at falling edge of E.


RESETB I Reset input - Chip is initialized when RESETB is LOW

Reset



7M/M-96-D00197-09-19

LCD Driver Outputs


C1 ~ C64 O LCD driver common output

S1 ~ S128 O LCD driver segment output

PCLK2 I

Phase of internal shift clock (CLK2)

ADC I

Address Control signal of Y address counter.

SHL I

Selection of data shift direction

PCLK2 Phase of Internal Shift Clock (CLK2)

0 Data shift at the falling edge of CLK2

1 Data shift at the rising edge of CLK2

ADC Segment output direction

H S1 ¡æ S2 ....S63 ¡æ S65 ¡æ S66 ....S127 ¡æ S128

L S64 ¡æ S63 ....S2 ¡æ S1 ¡æ S128 ¡æ S127 ....S66 ¡æ S65

SHL Data shift direction

H C1 ¡æ C2 ¡æ C3 .... C62 ¡æ C63 ¡æ C64

L C64 ¡æ C63 ¡æ C62 .... C3 ¡æ C2 ¡æ C1



8M/M-96-D00197-09-19

FUNCTIONAL DESCRIPTION

Chip Select input

The KS0708 has two chip select pin, CS1B and CS2B. It can interface with a mircoprocessor when thesepins(CS1B or CS2B)is Low. When both of these pins are set to High, DB0 to DB7 are high impedanceand RS, RW, and E inputs are disabled. CS1B pin controls the display status of S1 to S64, and CS2Bdoes that of S65 to S128. When CS1B and CS2B are Low at the same time, it is impossible to executeread operation. Therefore one of CS1B or CS2B should be set to Low((CS1B = ¡¨H¡¨& CS2B = ¡¨L¡¨)or(CS1B = ¡¨L¡¨ & CS2B = ¡¨H¡¨)) in read operation. The RESETB signal is entered independet of the sta-tus of Chip Select.

CS1B CS2BRead Operation Write Operation

CS1 CS2 CS1 CS2

H H X X X X

L H ¡Û X ¡Û X

H L X ¡Û X ¡Û

L L - - ¡Û ¡Û

( - : Not Recommended, ¡Û : Operation, X : No Operation)Table 1. Relationship between Chip Select pins and Read/Write Operation

Microprocessor InterfaceKS0708 transfers 8-bit parallel in either direction between the controlling microprocessor and the KS0708through the 8-bit I/O buffer(DB0 TO DB7).RS, RW and E identify the type of parallel data transfer to be made as shown in table 2.

RS RW Description

H H Display data read

H L Display data write

L H Status read

L L Writes to internal register (Instruction)

Table 2. Microprocessor Interface



9M/M-96-D00197-09-19

Busy flag

Busy flag indicates whether KS0708 is operating or not. When busy flag is high, KS0708 is in internal oper-ation. When low, KS0708 can accept the data or instruction. DB7 indicates busy flag of the KS0708.

E

BUSY FLAGTBUSY ¡Â 4/ fosc

Figure 1. Busy timing

Display Timing Generator Circuit

This section explains how the timing generation circuit operates. - Signal generation to display start line counter and display data latch circuit. - The display clock(CLK2) generates a clock to the line counter. The display start line address of the display RAM is synchronized with the display clock. 128-bit display data is latched by the display data latch circuit in synchronization with the display clock and output to the segment LCD drive output pin. - LCD AC signal(M) generation.



10M/M-96-D00197-09-19

Display Data RAM

The Display Data RAM stores pixel data for the LCD. It is a 128-column x 64-row addressable array asshown in Figure 3. The 64 rows are divided into 8 pages of 8 lines. Data is read from or written to the 8lines of each page directly through DB0 to DB7.The microprocessor reads from and writes to RAM through the I/O buffer. Since the LCD controller oper-ates independently, data can be written to RAM at the same time as data is being displayed, without caus-ing the LCD to flick.

DB0 1 0 0 0 1

DB1 1 0 0 1 0

DB2 1 0 1 0 0

DB3 1 1 0 0 0

DB4 1 0 1 0 0

DB5 1 0 0 1 0

DB6 1 0 0 0 1

DB7 0 0 0 0 0

( Display Data RAM )

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

( LCD Panel )

Figure 2. RAM-to-LCD data transfer



11M/M-96-D00197-09-19

Pageaddress

Lineaddress

SEGMENT OUTPUT(S1~S64)

DATABUS


Lineaddress

Pageaddress

S1

S2

S3

S4 ......

S61

S62

S63

S64

S65

S66

S67

S68

......S125

S126

S127

S128

0000

0001020304050607

......

DB0DB1DB2DB3DB4DB5DB6DB7

......

0001020304050607

000

001

0809101112131415

......


......

0809101112131415

001

010

1617181920212223

......


......

1617181920212223

010

011

2425262728293031

......


......

2425262728293031

011

100

32333435373839

......


......

3233343536373839

100

101

4041424344454647

......


......

4041424344454647

101



12M/M-96-D00197-09-19

Pageaddress

Lineaddress


DATABUS


Lineaddress

Pageaddress

S1

S2

S3

S4 ......

S61

S62

S63

S64

S65

S66

S67

S68

......S125

S126

S127

S128

110

4849505152535455

......


......

4849505152535455

110

111

5657585960616263

......


......

5657585960616263

111

ADC

1 0 1 2 4 ...... 60

61

62

63

0 1 2 4 ...... 60

61

62

63

1

ADC0 6

362

61

60

...... 3 2 1 0 63

62

61

60

...... 3 2 1 0 0

Column address Column address

Chip Select (CS1B) Chip Select (CS2B)

Figure 3. Display Data RAM



13M/M-96-D00197-09-19

MPU signal

RS

RW

E

N D(N) D(N+1) D(N+2) D(N+3) D(N+4) D(N+5)DB[7:0]

Internal signal

N D(N) D(N+1) D(N+2) D(N+3) D(N+4)

N N+1 N+2 N+3 N+4 N+5

WR

InputBuffer

ColumnAddress

Preset

K

Set Page Address => K

PageAddress

D(N) D(N+1) D(N+2) D(N+3) D(N+4)

Figure 4. Write Timing

RAM

MPU signal

N Dummy D(N) D(N+1) D(N+2) D(N+3)

RS

RW

E

DB[7:0]

Internal signal

D(N) D(N+1) D(N+2) D(N+3) D(N+4)

N N+1 N+2 N+3 N+4 N+5

Preset

K

Dummy

Set Page Address => K

PageAddress

ColumnAddress

WR

RD

OutputBuffer

Figure 5. Read timing



14M/M-96-D00197-09-19

Data Tramsfer

To match the timing of the display data RAM and registers to that of the controlling microprocessor,KS0708 uses an internal data bus and bus buffer. When the microprocessor reads the contents of displaydata RAM, the data for the initial read cycle is first stored inthe bus buffer (dummy read cycle). On the nextread cycle, the data is read from the bus buffer onto the microprocessor bus. At the same time, the nextblock of data is transferred from RAM to the bus buffer. Otherwise, when the microprocessor write data todisplay data RAM. the data is written to RAM atfer the falling edge of £àE£§. Therefore, it is necessary tocheck Busy Flag to write or read the next data. (refer to Figure4, 5)

Page Address Register

The 3-bit Page Address register provides the page address to display data RAM (refer to Figure 3). Themicroprocessor issues Set Page Address instruction to change the page and to access another page.

Column Address Counter

The column address counter is a 6-bit presettable counter that provides column address to display dataRAM (refer to Figure 3). It is incremented by 1 automatically after execution of each Read/Write Datainstruction. The column address counter loops the values 0 to 127, and it is independent of page addressregister. The ADC pin is issued to change the relationship between RAM Column address and display seg-ment output.

Display Start Line Register

The display start line register stores the line address of display data RAM that corresponds to the first (nor-mally the top) line(COM1) of liquid crystal display(LCD) panel. See Figure 3. When displaying contents indisplay data RAM on the LCD panel, 6-bit data(DB[5:0]) of the Set Display Start Line is latched in displaystart line register. Latched data are transferred to the line address counter just before COM1 is active High,presetting the line address counter. The line counter is then incremented on the display latch clock signalonce for every display line. It is used for vertical scrolling of the liquid crystal display screen.



15M/M-96-D00197-09-19

LCD Driver

LCD driver circuit has 192 outputs of 128 segment outputs, 64 common outputs for LCD driving.Each common output has a shift register. LCD driving output voltage is determined by the combination ofdisplay data and internal AC signal.

Display Data Common output Segment output

0V1 V2

V4 V3

1V5 V0

V0 V5

Display OFF - V2 or V3

Table 4. Relationship between data for each input signal and the LCD drive output.

Reset Circuit

Reset function can initialize system by setting RESETB terminal at Low level. When RESETB becomes low, following procedure occurs.

- Display start line : 0(First) - Display ON/OFF : OFF

While RESETB is in Low level, no instruction except Status Read can be accepted. Reset status appearsat DB4. Refers to Read Status of ¢©INSTRUCTION DESCRIPTION¢©.The conditions of power supply at initial power up are shown in table 3.

Item Symbol Min Typ Max Unit

Reset time tRESETB 1.0 - - us

Rise time tr - - 200 ns

Table 5. Power supply initial Conditions.

trVDD

RESETB

tRESETB

0.7VDD0.3VDD

Figure 6. Reset Timing



16M/M-96-D00197-09-19

INSTRUCTION DESCRIPTION

Instruction Table

Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function

Read display data 1 1 Read dataReads data (DB[0:7])from display data RAM tothe data bus.

Write display data 1 0 Write data

Writes data(DB[0:7]) intodisplay data RAM. Afterwriting instruction, columnaddress is incremented by1 automatically.

Status Read 0 1 BUSY 0 ON/OFF

RE-SET

0 0 0 0

Reads statusBUSY -0 : Ready -1 : In operationON/OFF -0 : Display ON -1 : Display OFFRESET -0 : Normal -1 : Reset

Set Column Address 0 0 0 1 Column address (0 ~ 63)Sets the Column address at the Column addresscounter

Set Display Start Line 0 0 1 1 Display Start Line (0 ~ 63)Indicates the display dataRAM displayed at the topof the screen.

Set Page Address 0 0 1 0 1 1 1 Page (0 ~ 7)Sets the Page address atthe Page address register.

Display ON/OFF 0 0 0 0 1 1 1 1 1 0/1

Controls the display on oroff. Internal status anddisplay RAM data is notaffected.L:OFF, H:ON



17M/M-96-D00197-09-19

Instructions

¡á Read Display Data

Reads 8-bit data display data RAM area specified by column address and page address. As the columnaddress is incremented by 1 automatically after each read operation, the microprocessor can continue toread data of multiple words.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 1 Read data

¡á Write Display Data

Writes 8-bit data in display data RAM. As the column address is incremented by 1 automatically after eachwrite operation, the microprocessor can continue to write data of multiple words.


1 0 Write data

¡á Read Status

Indicates the internal status conditions of the device to the microprocessor.


0 1 BUSY 0 ON/OFF RESET 0 0 0 0

Flag Description

BUSY The device is busy due to internal operation or reset. Any instruction is rejecteduntil BUSY goes Low.

ON/OFF Indicates whether the display is on or off. When goes Low, the display is on. When goesHigh, the display is off. This is the opposite of Display ON/OFF instruction.

RESET Indicates the initialization is in progress by RESETB signal. When Low, the chip is inactive. When High, the chip is being reset.



18M/M-96-D00197-09-19

¡á Set Page Address

Sets the page address of display RAM from the microprocessor into the page address register. Along withColumn address register, Page address register assigns the address of the display RAM to be written to orread from display data. Changing the address doesn ¢¥t affect the display status.


0 0 1 0 1 1 1 X2 X1 X0

X2 X1 X0 Page

0 0 0 0

0 0 1 1

: : : :

1 1 1 7

¡á Set Column Address

Sets the Column address of display RAM from the microprocessor into the Column address register.When the microprocessor reads or writes display data to or from display RAM, the address are automati-cally incremented.


0 0 0 1 Y5 Y4 Y3 Y2 Y1 Y0

Y5 Y4 Y3 Y2 Y1 Y0 Column address

0 0 0 0 0 0 0

0 0 0 0 0 1 1

: : : : : : :

1 1 1 1 1 0 62

1 1 1 1 1 1 63



19M/M-96-D00197-09-19

¡á Set Display Start Line

Sets the line address of display RAM to determine the display start line. The display data on the specifiedline of the display RAM is displayed at the top row COM1 of LCD panel. It is followed by the higher numberof lines in ascending order corresponding to the determined duty cycle. When this instruction changes thedisplay start line address, the LCD panel can be scrolled.


0 0 1 1 Z5 Z4 Z3 Z2 Z1 Z0

Z5 Z4 Z3 Z2 Z1 Z0 Line address

0 0 0 0 0 0 0

0 0 0 0 0 1 1

: : : : : : :

1 1 1 1 1 0 62

1 1 1 1 1 1 63

¡á Display ON/OFF

Turns the display ON or OFF.


0 0 0 0 1 1 1 1 1 D0

D0 = 1 : Display OND0 = 0 : Display OFF



20M/M-96-D00197-09-19

¡á APPLICATION DIAGRAM1 (ADC = H, SHL = H)

COM1 . .

COM32

LCD Panel(64 x 128)

COM33 . .

COM64SEG1 SEG2 .... SEG127 SEG128

C32 . . . .C1

C64 . . . .C33

S1 S2 . . . S127 S128

KS0708(Bottom View)

VE

EV

5V

4V

3V

2 V1

V0

VD

D

VDD

VEE

RE

SE

TB

RS

R/W

E CS

2B

DB

[0:7]

CS

1B

MPU

Figure 7. Application Diagram1

V0

V1

V2

V3

V4

V5

12

CS

2BER

/WRS

DB

[0:7]R

ES

ETB

CS

1B



21M/M-96-D00197-09-19

COM33 . . . COM32

LCD Panel(64 x 128)

COM1 . . .

COM32

SEG1 SEG2 .... SEG127 SEG128

C64 . . .C33

C32 . . .C1

S128 S127 . . . S1 S1

KS0708(Top View)

VE

EV

5V

4V

3V

2 V1

V0

VDD

VEE

RE

SE

TB

RS

R/W

E *CS

1B

DB

[0:7]

CS

1B

MPU

* Note When ADC = L, connects chip select pins(CS1B,CS2B) as following. - C1b (mpu) -> CS2B (KS0708) - CS2B (MPU) -> CS1B (KS0708)

Figure 8. Application Diagram 2

V0

V1

V2

V3

V4

V5

12

*CS

2BER

/WRS

DB

[0:7]R

ES

ETB

*CS

1B

¡á APPLICATION DIAGRAM2 (ADC = L, SHL = H)



22M/M-96-D00197-09-19

¡á APPLICATION DIAGRAM3 (ADC = L, SHL = L)

RE

SE

TB

RS

R/W E

*CS

2B

DB

[0:7]

*CS

2B

MPU

C33 . . . .C64

C1 . . . .C32S128 S127 . . . S2 S1

KS0708(Bottom View)

V0

V1

V2

V3

V4

V5

VE

E

*CS

2B

ERW

RS

DB

[0:7]R

ES

ET

B

COM1 . .

COM32

LCD Panel(64 x 128)

COM33 . .

COM64


* Note

When ADC = L, connects chip select pins (CS1B, CS2B) as following. - CS1B (MPU) -> CS2B (KS0708) - CS2B (MPU) -> CS1B (KS0708)


*CS

1B

12

VDD

VEE

V0

V1

V2

V3

V4

V5



23M/M-96-D00197-09-19

¡á APPLICATION DIAGRAM4 (ADC = H, SHL = L)

RE

SE

TB

RS

R/W E

*CS

2B

DB

[0:7]

*CS

2B

MPU

C1 . . . .C32

C33 . . . .C64S1 S2 . . . S127 S128

KS0708(Top View)

V0

V1

V2

V3

V4

V5

VE

E

*CS

1B

ERW

RS

DB

[0:7]R

ES

ET

B

COM33 . .

COM64

LCD Panel(64 x 128)

COM1 . . .

COM32


*CS

2B

12

VDD

VEE

V0

V1

V2

V3

V4

V5




24M/M-96-D00197-09-19

SPECIFICATIONS

Absolute Maximum Ratings

Parameter Symbol Rating Unit Note

Operating voltage VDD -0.3 ~ +7.0

V

*1

Supply Voltage VEE VDD-19.0 ~ VDD+0.3 *4

Driver Sypply VoltageVB -0.3 ~ VDD+0.3 *1,3

VLCD VEE-0.3 ~ VDD+0.3 *2

Note :

*1. Based on Vss = 0V*2. VLCD = VDD - VEE*3. Applies to SHL, FS, PCLK2, CR, RESETB, ADC, CS1B, CS2B, E, RW, RS and DB0 ~ DB7.*4. Voltage level VDD ¡Ã V0 ¡Ã V1 ¡Ã V2 ¡Ã V3 ¡Ã V4 ¡Ã V5 ¡Ã VEE

Temperature Characteristics

Parameter Symbol Rating Unit Note

Operating temperature Topr -30 ~ +85¡É

Storage temperature Tstg -55 ~ +125



25M/M-96-D00197-09-19

Electrical Characteristics

DC Characteristics

Item Symbol Condition Min Typ Max Unit Note

Operating Voltage VDD - 4.5 - 5.5

V

Input High VoltageVIH1 - 0.7VDD - VDD *1

VIH2 - 2.0 - VDD *2

Input Low VoltageVIL1 - 0 - 0.3VDD *1

VIL2 - 0 - 0.8 *2

Output High Voltage VOH IOH = -200uA 2.4 - -*3

Output Low Voltage VOL IOL = 1.6mA - - 0.4

Input Leakage Current ILKG VIN = VSS ~ VDD -1.0 - +1.0

uA

*4

Tri-state Leakage Current ITSL VIN = VSS ~ VDD -5.0 - +5.0 *5

Driver Input Leakage Current IDLKG VIN = VEE ~ VDD -10 - +10 *6

Operating CurrentIDD1 During Display - - 0.8

mA*7

IDD2 During Access - - 1.0 *8

On resistance

COM RONC VDD - VEE = 17V¡¾ILOAD = 0.1mA

- - 1.5k§Ù

*9

SEG RONS - - 7.5 *10

Oscillation frequency foscTa=25¡É, VDD=5VRf = 47k§Ù ¡¾ 2%Cf = 20pF ¡¾ 5%

315 450 585 KHz

Note :

*1. FS, CR, ADC, SHL, PCLK2, RESETB*2. CS1B, CS2B, E, RW, RS, DB0 ~ DB7*3. DB0 ~ DB7*4. Excepted DB0 ~ DB7*5. DB0 ~ DB7 at High Impedence*6. V0, V1, V2, V3, V4, V5*7. C = 20pF, R = 47 k§Ù, fose = 450 KHz, DB0 ~ DB7 = VDD, Output = No Load*8. Excepted Clock = 430KHz, RAM Access Cycle = 1MHz*9. V0 = 5V, V1 = 3.2V, V2 = 1.4V, V3 = -8.4V, V4 = -10.2V, V5 = -12V, C1 ~ C64*10. V0 = 5V, V1 = 3.2V, V2 = 1.4V, V3 = -8.4V, V4 = -10.2V, V5 = -12V, S1 ~ S128

(VDD = 4.5 ~ 5.5V, Ta = -30 ~ +85¡É)



26M/M-96-D00197-09-19

AC Characteristics

Mode Item Symbol Min Typ Max Unit

Write Mode(Refer toFigure 9)

E Cycle Time tc 1000 - -

ns

E Rise / Fail Time tr, tf - - 25

E Pulse Width(High, Low) tw 450 - -

RW and RS Setup Time tsu1 140 - -

RW and RS Hold Time th1 10 - -

Data Setup Time tsu2 200 - -

Data Hold Time th2 10 - -

Read Mode(Refer to

Figure 10)

E Cycle Time tc 1000 - -

ns

E Rise / Fall Time tr,tf - - 25

E Pulse Width (High, Low) tw 450 - -

Rw and Rs Setup Time tsu 140 - -

RW and RS Hold Time th 10 - -

Data Output Delay Time tD - - 320

Data Hold Time tDH 20 - -

(VDD = 4.5 to 5.5V, Ta = -30 to +85 ¡É)



27M/M-96-D00197-09-19

Figure 9. Write Mode Timing Diagram

RSVIH1

VIL1

VIL1 VIL1

twtf

th1

th1

VIH1

tSU1

VIL1

VIH1

VIL1

tfth2

VIL1

tCVIL1

VIH1

tSU2

VIH1VIL1

Valid Data

RW

E

DB0 ~ DB7

VIH1

VIL1

tSU

VIH1

th

VIH1

thtw

tf

VIL1

tDH

VIH1

VIL1VIL1

VIH1

tr

tc

VIH1

VIL1Valid Data

VIL1

VIH1

RS

RW

E

DB0 ~ DB7

Figure 10. Read Mode Timing Diagram

tD

preliminary specification ks0708 64com/128seg drive … notes/samsung/ks0708.pdf · 2017. 6. 5. ·...

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