practical designpractical design--forfor--test test for 2 ... · −logic dies: 5-7% of chip area...
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Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
1
SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
Erik Jan MarinissenIMEC – Leuven, Belgium
Practical DesignPractical Design--forfor--Test Test for 2.5Dfor 2.5D-- and 3Dand 3D--SICsSICs
© IMEC 2011 / CONFIDENTIAL － Erik Jan Marinissen 1
g
Practical DesignPractical Design--forfor--Test for 2.5DTest for 2.5D-- and 3Dand 3D--SICsSICs
Presentation OutlinePresentation Outline
1. Introduction2. Basic 3D DfT Architecture3. Extensions to Basic 3D DfT Architecture4 A tomation4. Automation5. Test Cases6. Conclusion
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 2
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
2
SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
1. Introduction1. Introduction
2D Test 2D Test FlowFlow
wafer fab
Conventional 2D
W f T t
3D-SIC
wafer fab 2 wafer fab 3wafer fab 1
P B dP B d
1. Introduction1. Introduction
2D Test Flow vs. 3D Test Flows2D Test Flow vs. 3D Test Flows
bl &
Wafer Test
assembly &
stacking1+2 ( )
stacking(1+2)+3
Mid-Bond Post-Bond
Pre-Bond Pre-BondPre-Bond
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 3
p g gassembly &packaging
Final Test
[Marinissen & Zorian – ITC’09][Marinissen – DATE’10, DATE’12]
g gassembly &packaging
Final Test
1. Introduction1. Introduction
3D Potential Test Moments3D Potential Test Moments
• Pre-Bond Test–Target : die (+ TSVs?)–Access : wafer probe on die
3D-SIC
wafer fab 2 wafer fab 3wafer fab 1
P B dP B d–Challenge : micro-bump probingon non-bottom dies
• Mid- and Post-Bond Test–Target : interconnects (+ dies?)–Access : wafer probe on bottom die
and Design-for-Test–Challenge : coordinated DfT up/down stack
assembly &
stacking1+2 ( )
stacking(1+2)+3
Mid-Bond Post-Bond
Pre-Bond Pre-BondPre-Bond
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 4
• Final Test–Target : dies + interconnects–Access : socket access on bottom die
and Design-for-Test–Challenge : coordinated DfT up/down stack
g pg g
assembly &packaging
Final Test
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
1. Introduction1. Introduction
DesignDesign--forfor--TestTest
• Definition: Testability features of an IC, designed to ease the development and application of manufacturing tests
• Examples of DfT− Scan chains : controllability/observability inside logic− Test Data Compression : make large SOCs look small on the ATE− Built-In Self-Test : autonomous test− IEEE Std 1500 : modular test with embedded IP cores− IEEE Std 1149.1 : board-level test access
• Cost
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 5
− Package pins: few pins for test control− Silicon area: (1) less dies per wafer and (2) lower yield− Logic dies: 5-7% of chip area for DfT is common
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
OverviewOverview
• Die Wrapperbased on IEEE Std 1500
• Leverage Existing 2D-DfT Features Di TDC BIST t
• Serial Test Access Mechanism (TAM): 1-bit– Wrapper Instruction Register (WIR)– Low-bandwidth test data access– Multiplexed onto IEEE 1149.1 pins
– Die: scan, TDC, BIST, etc.– Stack: IEEE 1149.1 Boundary Scan
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 6
• Parallel TAM: n-bits– High-bandwidth test data access– Multiplexed onto functional I/Os– n is user-defined parameter; n≥0
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
Feature: Test Data Up/Down the StackFeature: Test Data Up/Down the Stack
• Post-Bond Test Access– Via external I/Os,
typically at bottom of stack– Before packaging: probe on C4 bumpsp g g p p– After packaging: socket via package pins
• Test Data Up/Down Stack– Test stimuli up in stack– Test responses down in stack
• Terminology– “TestElevators” [Marinissen – DATE’10]
P h “ l t ”?
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 7
– Perhaps more “escalators”?
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
Feature: Modular TestingFeature: Modular Testing
• Test Data Targets– Die x
(for 1 ≤ x ≤ N)
– Interconnects between Die x and Die x+1(for 1 ≤ x < N)
• Test Wrapper Modes– Bypass : this die is not tested– Extest : Wrapper Boundary Register (WBR)– Intest : WBR + internal DfT
• TAM Direction Modes: after this die
vate
vate
Para
llelInte
stTu
rnPa
ralle
lInte
stTu
rnat
eat
eSer
ialE
xtes
tTurn
Ser
ialE
xtes
tTurn
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 8
– Turn : TAM turns down– Elevate : TAM elevates up
Para
llelB
ypas
sEle
vPa
ralle
lByp
assE
lev
• Examples− 1: ParallelBypassElevate;2: ParallelIntestTurn S
eria
lExt
estE
leva
Ser
ialE
xtes
tEle
va
− 1: SerialExtestElevate; 2: SerialExtestTurn
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
Feature: Serial vs. Parallel TAMFeature: Serial vs. Parallel TAM
• Parallel TAM: Volume Production– n-bit/clock cycle; n user-defined– Multiplexed onto functional package pins– Wider Parallel TAM impliesWider Parallel TAM implies
• Less test data volume: cheaper ATE• Less test time: less seconds on ATE
• Serial TAM: Test + Debug Back-Door– 1-bit/clock cycle– Multiplexed onto IEEE 1149.1 package pins– Provides slow test access even if 3D-SIC is
soldered onto Printed Circuit Board
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 9
Board
so de ed o to ted C cu t oa d• Via PCB-level JTAG connector
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
Feature: DaisyFeature: Daisy--Chained TAMsChained TAMs
• Serial TAM– Daisy-chain is only option
• Parallel TAMSi l TAM f b thi di d t di– Single TAM for use by this die and next die
– Full test bandwidth available to all tests– Simple coordination agreement across stack
• Test Ports– One primary test port– Zero or more secondary test ports
– Electrical role independentfrom physical location
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 10
Die 2
Die 1
Die 1
Interposer
Die 2
Die 3
from physical location
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
Feature: PreFeature: Pre--Bond Probe AccessBond Probe Access
• Non-Bottom Dies: Fine-Pitch Micro-Bumps– Today: pitch 40μm, diameter 15-25μm
25µm Ø Cu 12.5µm Ø Cu 7.5µm Ø Cu/Ni/Sn
– Tomorrow: pitch 20μm25µm Ø Cu
15µm Ø Cu/Sn
µ µ
1. Direct Micro-Bump Probing– Advanced fine-pitch probe cards
[Smith et al. – ITC’11]
2. Dedicated Pre-Bond Probe Pads
1]
40μm pitch 20μm pitch
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 11
– Larger pitch/dimensions [Marinissen & Zorian– ITC’09]– Trade-off between pad area and test time
[Sou
rce:
Sam
sung
, IS
SC
C’1
1
• I/O-Wrap at Non-Probed I/Os– Pre-bond test coverage
of I/O drivers/receivers– Turn every input/output into bi-dir
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
Feature: Low Implementation CostFeature: Low Implementation Cost
• Reuse of Existing Package Pins– P-TAM: multiplexing on functional pins– S-TAM: multiplexing on JTAG pins
T t TSV (“T tEl t ”)• Test TSVs (“TestElevators”)– S-TAM: dedicated, 8 per die– P-TAM: dedicated or shared with functional
• Dedicated: independent access• Shared: lower cost
• Wrapper Boundary Register (WBR)– Dedicated or shared with functional registers
(similar to IEEE Std 1500)
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 12
• Leverage of Existing 2D DfT Features– Especially internal scan
(similar to IEEE Std 1500)
Negligible Implementation Costs– 0 pins, 8 TSVs, <0.1% gate area
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
2. Basic 3D 2. Basic 3D DfTDfT Architecture Architecture
Feature: Flexible Test SchedulingFeature: Flexible Test Scheduling
• Test Control Pre-Amble1. Program IEEE 1149.1 TAP Controller
into “IEEE 1500” mode2. Program Wrapper Instruction Registers g pp g
(WIRs) into appropriate configuration modes
• Serial / Parallel• Bypass / Extest / Intest• Turn / Elevate
• Flexible Test Scheduling− Inclusion / exclusion of particular test
3. Streaming test data execution
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 13
− Ordering of individual tests• Abort-on-Fail: shorter avg. test time• Short and low-yielding tests first• Rescheduling if production matures
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
Extensions to Basic 3D Extensions to Basic 3D DfTDfT ArchitectureArchitecture
• Original architecture– Electrically linear tower: Die 1, Die 2, Die 3, ...– Digital logic dies
M li hi d i d i hi h i hi di– Monolithic design: no design hierarchy within die– Scan chains
• Extensions to real-life industrial dies1. Memory-on-Logic: JEDEC Wide-I/O DRAM2. Large SOCs
• On-chip embedded IP cores (IEEE 1500)
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 14
• On-chip Test Data Compression (TDC)3. Multi-tower stacks
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
• Defines Logic-Memory Interface– Four channels (a-d) with 300 micro-bumps each– Per channel
128 DQ bi di d t bit ( “Wid I/O”)
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
JEDEC WideJEDEC Wide--I/O Mobile DRAM StandardI/O Mobile DRAM Standard
• 128 DQ bi-dir data bits (= “Wide-I/O”)
• Independent address, control and clock– Shared power and ground
• Allows Various Stack ConfigurationsSt k f t f DRAM ‘ k ’
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 15
– Stack of one up to four DRAM ‘ranks’– Stacked on top of logic die (“3D”)
or next to logic die on interposer (“2.5D”)
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
JEDEC WideJEDEC Wide--I/O DRAM Boundary ScanI/O DRAM Boundary Scan
• JEDEC Wide-I/O Standard specifiesBoundary Scan DfT inside DRAMfor Logic-Memory Interconnect Test
scan-in
– Boundary scan is own JEDEC flavor,
DRAMtest
control
Logic-MemoryInterface
scan-out
• Operation modes– Functional : BS is transparent– Serial In/Out : shift BS chain– Parallel In : capture in DRAM Die
ll l O
Boundary scan is own JEDEC flavor,not compliant to IEEE Std 1149.1
– JEDEC Standard contains typos!
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 16
– Parallel Out : capture in Logic Die
• Interconnect Test is a collaborative effort between DRAM and Logic Die− DRAM test control from Logic Die− Joint test data, sent by one die,
captured by the other die
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
• Extension of 3D DfT forLogic Die to perform test ofLogic-Memory interconnect
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
Extension of 3D Extension of 3D DfTDfT for Widefor Wide--I/O DRAMI/O DRAM
• Features− On-chip generation of
DRAM test control signals− 100% coverage for
static interconnect tests− User-defined scheduling
of interconnect tests to 16 memory
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 17
yblocks (rank/channel order)
− “I/O-Wrap” for Logic:pre-bond test of I/O drivers/receivers(JEDEC standard unfortunately doesnot guarantee I/O-Wrap test for DRAM)
= Additional 3D-DfT tosupport Wide-I/O DRAM
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
MemoryMemory--onon--Logic StackLogic Stack
DRAM0
Boundary
Boundary
Mem
0D
Wide
3D Wrapper
W
Logic Die xLogic Die x
W
DRAM1
Boundary
Boundary
Mem
1D
DRAM2
Boundary
Boundary
Mem
2D
DRAM3
Boundary
Boundary
Mem
3DDRAMMemory
MBIS
MBIS
Boundary
Boundary
Mem
0C
Boundary
Boundary
Mem
0B
SDI
tt
CS_n
[0
WBR
switch
box
scan chain
scan chain
WBR
switch
box
WPO
c4
4
Boundary
Boundary
Mem
1C
Boundary
Boundary
Mem
1B
Boundary
Boundary
Mem
2C
Boundary
Boundary
Mem
2B
Boundary
Boundary
Mem
3C
Boundary
Boundary
Mem
3B
yController
STST
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 18
SDO Boundary
Boundary
Mem
0A
TestControl
cscs
:3][a:d
]
x
w
x
WPI
WSI
WSO
WSC13WIR
DRAMCtrl
SSEN
CtrlCtrl
Boundary
Boundary
Mem
1A
CtrlCtrl
Boundary
Boundary
Mem
2A
Boundary
Boundary
Mem
3A
CtrlCtrl CtrlCtrl
SSH_n[a:d]
SOE_n[a:d]
SCK[a:d]
CS_n
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
10
SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
MemoryMemory--onon--Logic Logic StackStack
DRAM0
Boundary
Boundary
Mem
0D
Wide
DRAM1
Boundary
Boundary
Mem
1D
DRAM2
Boundary
Boundary
Mem
2D
DRAM3
Boundary
Boundary
Mem
3D3D Wrapper
WW
Testing Logic Memory interconnects for Rank 0
Logic Die xLogic Die xDRAM
Memory
MBIS
MBIS
Boundary
Boundary
Mem
0C
Boundary
Boundary
Mem
0B
SDI
Boundary
Boundary
Mem
1C
Boundary
Boundary
Mem
1B
Boundary
Boundary
Mem
2C
Boundary
Boundary
Mem
2B
Boundary
Boundary
Mem
3C
Boundary
Boundary
Mem
3B
tt
CS_n
[0
WBR
switch
box
WBR
switch
box
WPO
c4
4
scan chain
scan chain
yController
STST
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 19
SDO Boundary
Boundary
Mem
0A
TestControl
Boundary
Boundary
Mem
1A
Boundary
Boundary
Mem
2A
Boundary
Boundary
Mem
3A
cscs
:3][a:d
]
x
w
x
WPI
WSI
WSO
WSC13WIR
DRAMCtrl
SSEN
CtrlCtrl CtrlCtrl CtrlCtrl CtrlCtrl
SSH_n[a:d]
SOE_n[a:d]
SCK[a:d]
CS_n
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
MemoryMemory--onon--Logic Logic StackStack
DRAM0
Boundary
Boundary
Mem
0D
Wide
DRAM1
Boundary
Boundary
Mem
1D
DRAM2
Boundary
Boundary
Mem
2D
DRAM3
Boundary
Boundary
Mem
3D
3D Wrapper
WW
Testing Logic Memory interconnects for Rank 1
Logic Die xLogic Die xDRAM
Memory
MBIS
MBIS
Boundary
Boundary
Mem
0C
Boundary
Boundary
Mem
0B
SDI
Boundary
Boundary
Mem
1C
Boundary
Boundary
Mem
1B
Boundary
Boundary
Mem
2C
Boundary
Boundary
Mem
2B
Boundary
Boundary
Mem
3C
Boundary
Boundary
Mem
3B
tt
CS_n
[0
WBR
switch
box
WBR
switch
box
WPO
c4
4
scan chain
scan chain
yController
STST
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 20
SDO Boundary
Boundary
Mem
0A
TestControl
Boundary
Boundary
Mem
1A
Boundary
Boundary
Mem
2A
Boundary
Boundary
Mem
3A
cscs
:3][a:d
]
x
w
x
WPI
WSI
WSO
WSC13WIR
DRAMCtrl
SSEN
CtrlCtrl CtrlCtrl CtrlCtrl CtrlCtrl
SSH_n[a:d]
SOE_n[a:d]
SCK[a:d]
CS_n
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
11
SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
MemoryMemory--onon--Logic Logic StackStack
DRAM0
Boundary
Boundary
Mem
0D
Wide
DRAM1
Boundary
Boundary
Mem
1D
DRAM2
Boundary
Boundary
Mem
2D
DRAM3
Boundary
Boundary
Mem
3D3D Wrapper
WW
Testing Logic Memory interconnects for Rank 2
Logic Die xLogic Die xDRAM
Memory
MBIS
MBIS
Boundary
Boundary
Mem
0C
Boundary
Boundary
Mem
0B
SDI
Boundary
Boundary
Mem
1C
Boundary
Boundary
Mem
1B
Boundary
Boundary
Mem
2C
Boundary
Boundary
Mem
2B
Boundary
Boundary
Mem
3C
Boundary
Boundary
Mem
3B
tt
CS_n
[0
WBR
switch
box
WBR
switch
box
WPO
c4
4
scan chain
scan chain
yController
STST
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 21
SDO Boundary
Boundary
Mem
0A
TestControl
Boundary
Boundary
Mem
1A
Boundary
Boundary
Mem
2A
Boundary
Boundary
Mem
3A
cscs
:3][a:d
]
x
w
x
WPI
WSI
WSO
WSC13WIR
DRAMCtrl
SSEN
CtrlCtrl CtrlCtrl CtrlCtrl CtrlCtrl
SSH_n[a:d]
SOE_n[a:d]
SCK[a:d]
CS_n
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
MemoryMemory--onon--Logic Logic StackStack
DRAM0
Boundary
Boundary
Mem
0D
Wide
DRAM1
Boundary
Boundary
Mem
1D
DRAM2
Boundary
Boundary
Mem
2D
DRAM3
Boundary
Boundary
Mem
3D
3D Wrapper
WW
Testing Logic Memory interconnects for Rank 3
Logic Die xLogic Die xDRAM
Memory
MBIS
MBIS
Boundary
Boundary
Mem
0C
Boundary
Boundary
Mem
0B
SDI
Boundary
Boundary
Mem
1C
Boundary
Boundary
Mem
1B
Boundary
Boundary
Mem
2C
Boundary
Boundary
Mem
2B
Boundary
Boundary
Mem
3C
Boundary
Boundary
Mem
3B
tt
CS_n
[0
WBR
switch
box
WBR
switch
box
WPO
c4
4
scan chain
scan chain
yController
STST
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 22
SDO Boundary
Boundary
Mem
0A
TestControl
Boundary
Boundary
Mem
1A
Boundary
Boundary
Mem
2A
Boundary
Boundary
Mem
3A
cscs
:3][a:d
]
x
w
x
WPI
WSI
WSO
WSC13WIR
DRAMCtrl
SSEN
CtrlCtrl CtrlCtrl CtrlCtrl CtrlCtrl
SSH_n[a:d]
SOE_n[a:d]
SCK[a:d]
CS_n
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
12
SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
MemoryMemory--onon--Logic Logic StackStack
DRAM0
Boundary
Boundary
Mem
0D
Wide
DRAM1
Boundary
Boundary
Mem
1D
DRAM2
Boundary
Boundary
Mem
2D
DRAM3
Boundary
Boundary
Mem
3D3D Wrapper
WW
Logic Die xLogic Die xDRAM
Memory
MBIS
MBIS
Testing Logic Memory interconnects for different ranks
Boundary
Boundary
Mem
0C
Boundary
Boundary
Mem
0B
SDI
Boundary
Boundary
Mem
1C
Boundary
Boundary
Mem
1B
Boundary
Boundary
Mem
2C
Boundary
Boundary
Mem
2B
Boundary
Boundary
Mem
3C
Boundary
Boundary
Mem
3B
tt
CS_n
[0
WBR
switch
box
WBR
switch
box
WPO
c4
4
scan chain
scan chain
yController
STST
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 23
SDO Boundary
Boundary
Mem
0A
TestControl
Boundary
Boundary
Mem
1A
Boundary
Boundary
Mem
2A
Boundary
Boundary
Mem
3A
cscs
:3][a:d
]
x
w
x
WPI
WSI
WSO
WSC13WIR
DRAMCtrl
SSEN
CtrlCtrl CtrlCtrl CtrlCtrl CtrlCtrl
SSH_n[a:d]
SOE_n[a:d]
SCK[a:d]
CS_n
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
MemoryMemory--onon--Logic Logic StackStack
DRAM0
Boundary
Boundary
Mem
0D
Wide
3D Wrapper
WW
DRAM1
Boundary
Boundary
Mem
1D
DRAM2
Boundary
Boundary
Mem
2D
DRAM3
Boundary
Boundary
Mem
3D
Testing memory from Memory BIST in DRAM Memory Controller
Logic Die xLogic Die xDRAM
Memory
MBIS
MBIS
Boundary
Boundary
Mem
0C
Boundary
Boundary
Mem
0B
SDI
tt
CS_n
[0
WBR
switch
box
WBR
switch
box
WPO
c4
4
Boundary
Boundary
Mem
1C
Boundary
Boundary
Mem
1B
Boundary
Boundary
Mem
2C
Boundary
Boundary
Mem
2B
Boundary
Boundary
Mem
3C
Boundary
Boundary
Mem
3B
scan chain
scan chain
yController
STST
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 24
SDO Boundary
Boundary
Mem
0A
TestControl
cscs
:3][a:d
]
x
w
x
WPI
WSI
WSO
WSC13WIR
DRAMCtrl
SSEN
CtrlCtrl
Boundary
Boundary
Mem
1A
CtrlCtrl
Boundary
Boundary
Mem
2A
Boundary
Boundary
Mem
3A
CtrlCtrl CtrlCtrl
SSH_n[a:d]
SOE_n[a:d]
SCK[a:d]
CS_n
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
Extension for Large SOCsExtension for Large SOCs
• Large industrial SOCs include1. On-chip embedded IP cores (IEEE 1500)2. On-chip Test Data Compression (TDC)
• Embedded IP Cores– Hierarchical design:
SOC=“parent”, Core=“child”– Intest of SOC requires core’s
IEEE 1500 wrapper in Extest– Programmable in-/exclusion
of Core WIRs
Wrapped Die
Die
Top-level logic
Wrapper
Core
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• Test Data Compression– TDC block daisy-chained test access up-/downstream– Solution
• Ser/Deserializer width adaptors• Restriction to sequential test schedules
3. Extensions to Basic 3D 3. Extensions to Basic 3D DfTDfT ArchitectureArchitecture
Extension for MultiExtension for Multi--TowersTowers
• Future 3D-SICs might contain multiple towers– First case already encountered
• Extended 3D DfT to handle Multi-Towers
WIR
WIR
WIR
WIR
Die 5
Die 3 Die 4 Die 7
– Definition of variable numberof secondary ports:k=0: top die, no die abovek=1: middle die,
single towerk ≥2: multiple towers
– Lower WIR determinesin-/exclusion of Test
Test
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WIR
WIR
WIR
Die 1
Die 2 Die 6
in /exclusion ofhigher-level WIRs
Test
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
4. 3D 4. 3D DfTDfT Automation Automation
3D 3D DfTDfT EDA FlowsEDA Flows
Die Maker Flow• Insert 3D-DfT Wrapper to given design• Automatic Test Pattern Generation (ATPG)
P e Bond Test
3D-DfT Insertion
ATPG• Pre-Bond Test ATPG
Die Test
1 2
netlist reduced netlist + patterns
regeneratepatterns
reusepatterns
HandoverOptions:
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 27
Stack Maker Flow• Test Generation
− Dies− Interconnects
• Mid-Bond/Post-Bond/Final Test
Die IntestGeneration
Interconnect ATPG
Stack Test
p
4. 3D 4. 3D DfTDfT Automation Automation
3D 3D DfTDfT Flow 1: Regenerating PatternsFlow 1: Regenerating Patterns
Die Maker Flow Stack Maker Flow
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[Marinissen et al. – CSR’11][Deutsch et al. – ATS’11]
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
4. 3D 4. 3D DfTDfT Automation Automation
3D 3D DfTDfT Flow 2: Reusing PatternsFlow 2: Reusing Patterns
Die Maker Flow Stack Maker Flow
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 29
[Marinissen et al. – CSR’11][Deutsch et al. – ATS’11]
4. 3D 4. 3D DfTDfT Automation Automation
3D 3D DfTDfT Wrapper Wrapper InsertionInsertion
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[Deutsch et al. – ATS’11]
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
4. 3D 4. 3D DfTDfT Automation Automation
3D 3D DfTDfT EDA StatusEDA Status
• Patent-pending architecture definition
• Basic 3D DfT Architecture (June 2011)– Automated DfT Insertion– Interconnect ATPG and Test Migration– In TSMC’s Reference Flow 12http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=060611_imec
• Extended 3D DfT Architecture (October 2012)– Automated DfT insertion for Wide-I/O Interconnect Test– Wide-I/O Interconnect ATPG and Test Migration– In TSMC’s CoWoS Reference Flow
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http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=7281&language=E
• Extended 3D DfT Architecture (today)– Automated DfT insertion for
Embedded IP Cores, TDC, Multi-Towers
5. Experimental Results5. Experimental Results
Test CasesTest Cases
• IMEC: Vesuvius– 3D DfT Demonstrator:
two dies, 8mm2 in65nm CMOS (GF, IMEC)65nm CMOS (GF, IMEC)
top bottom
• TSMC: Test Chip– 2.5D interposer-based (‘CoWoS’) stack
• Wide-I/O DRAM (single rank), compliant to JEDEC JESD-229 • Logic SOC: 94mm2 in 40nm CMOS
− 3D DfT inserted with Cadence RTL CompilerA t 0 024657 2 ( 0 03% li ibl )
pre-bond test
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 32
− Area costs: 0.024657mm2 (= 0.03%, negligible)• Interconnect ATPG with Cadence Encounter Test: 24 test patterns
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
6. Conclusion6. Conclusion
SummarySummary
• A 3D DfT architecture has been defined, automated, and implemented
– Test of dies and embedded cores• Support
– Pre-bond test– Test of inter-die interconnects– Mid- and post-bond test
• Features– Modular testing– Test data up/down the stack– Serial TAM
• Slow test data/instructionsT t d b “b k d ”
– Optional pre-bond probe pads• ‘I/O Wrap’ at non-probed I/Os
– Flexible test scheduling– Low implementation costs
R i TSV WBR DfT
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• Test + debug “back-door”, even on PCB
– Optional Parallel TAM• High-bandwidth test data
– Daisy-chained TAMs minimize dependencies between dies
• Reuse pins, TSVs, WBR, DfT• 0 pins, 8 TSVs/die, <0.1% area
− Recent extensions• JEDEC Wide-I/O DRAM• SOCs: IP cores, TDC• Multi-tower stacks
6. Conclusion 6. Conclusion
3D Test Access Standardization3D Test Access Standardization
• IEEE Standards Association– Home of many DfT standards: 1149.x, 1500, 1532, 1581, P1687, ...
• 3D Test Study Group3D Test Study Group– Inventory need for and timeliness of
standards in 3D test and DfT– Started Jan. 2010; PAR to IEEE-SA: Nov. 2010
• 3D Test Working Group– Working on Project P1838:
“Standard for Test Access Architecture forThree-Dimensional Stacked Integrated Circuits”
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Three Dimensional Stacked Integrated Circuits– Active after PAR approval, February 2011– Weekly conference calls– Requirements engineering phase– >55 active members from companies/institutes world-wide– More information: http://grouper.ieee.org/groups/3Dtest/
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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SEMI European 3D TSV Summit – Grenoble, France – January 22+23, 2013© Erik Jan Marinissen – IMEC, Leuven, Belgium
6. Conclusion6. Conclusion
AcknowledgementsAcknowledgements
• IMEC (Leuven, Eindhoven2)3D Team + REMO + AMSIMEC + Mario Konijnenburg2
• Cadence Design Systems (Austin1, Endicott2, München3, Noida4)Vivek Chickermane2, Sergej Deutsch3, Marc Greenberg1,Vivek Chickermane , Sergej Deutsch , Marc Greenberg ,Brion Keller2, Subhasish Mukherjee4, Christos Papameletis3
• Cascade MicroTech (Beaverton1, Dresden2)Juliane Busch2, Peter Hanaway1, Jörg Kiesewetter2,Axel Schmidt2, Ken Smith1, Eric Strid1, Thomas Thärigen2
• TEL Test Systems (Grenoble2, Kildare3, Nirasaki4)Paul Mooney3, Eric Pradel2, Dan Rishavy1, Yoichi Shimizu4
• TSMC (HsinChu1, Leuven2, San Jose3)Ji-Jan Chen1, Sandeep K. Goel2,3, Ashok Mehta3, Frank Lee1
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• Duke University (Durham)Krishnendu Chakrabarty, Sergej Deutsch, Brandon Noia
• National Tsing-Hua University (HsinChu)Po-Yuan Chen, Chun-Chuan Chi, Cheng-Wen Wu
• TU Delft (Delft)Said Hamdioui, Mottaqiallah Taouil, Jouke Verbree
6. Conclusion6. Conclusion
Related EventsRelated Events
• 3DICIEEE Intnl. 3D System Integration Conferencehttp://www.3dic-conf.jp/
– Rotating between California, Germany, and Japang , y, p– Next edition: September 30, 2013 – San Francisco, California, USA
• 3D Integration WorkshopApplications, Technology, Architecture, Design, Automation, and Testhttp://www.date-conference.com/conference/workshop-w5
– Co-located with DATE’09, DATE’10, DATE’11, DATE’12– Next edition: March 22, 2013 – Grenoble, France (with DATE’13)
IMEC/2013 | Erik Jan Marinissen | SEMI European 3D TSV Summit – January 22+23, 2013 36
• 3D-TESTIEEE Intnl. Workshop on Testing Three-Dimensional Stacked ICshttp://3dtest.tttc-events.org/
– Co-located with ITC’10, ITC’11, ITC’12– Next edition: September 12+13, 2013 – Anaheim CA (with ITC’13)
Practical Design-for-Test for 2.5D- and 3D-Stacked ICsErik Jan Marinissen
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www.imec.be