practical application of dds

www.idetic.eu

Seminar in

Broadband HF transceiverdesign experiences

Speaker: Baltasar Pérez Díaz <[email protected]>

Author: Baltasar Pérez Díaz

Multimedia Room, Polivalente II, 2nd floor

Campus de Tafira, Las Palmas 16th May, 2014

Broadband HF transceiver design experiences

BACKGROUND INFORMATION

Broadband digital HF transceiver

Wattmeter

Driver

BroadbandTransceiver

1KW Poweramplifier

DUC/DDC multichannel

(FPGA)

More than 15 years developing HF modem (software) (IDeTIC+UPM)Last 10 years hardware development HFDVL (High Frequency Data+Voice Link) architecture1MHz bandwidth (not signal) = +300 times conventional radio (3KHz)

16th May IDeTIC Seminar 2


PRESENTATION INDEX

1. HF broadband digital transceiver introductiona. Block diagram and pics

2. Main problems and solutionsa. Local oscillator (DDS spurs, reference clock)b. Filter (low availability, limited)c. AGC (algorithm and narrow band interference)d. Amplifier (intermodulation products)e. Antenna (broadband antennas)

3. Summary

INDEX

INTRODUCTION

MAIN PROBLEMSAND SOLUTIONS

SUMMARY

16th May 3IDeTIC Seminar


BROADBAND DIGITAL HF TRANSCEIVER INTRODUCTION

Digitalreceiver (DDC)

Receiverantenna

RF receiver(analog)

AUDIO

D/AConverter

STATION

A/DConverter

IF to bedigitized

Signalprocessing

Digitalreceiver (DDC)

Receiverantenna

RF receiver(analog)

AUDIO

D/AConverter

STATION

A/DConverter

IF to bedigitized

A/DConverter

IF to bedigitized

Signalprocessing

Signalprocessing

• RF-Front end moves 1MHz to IF (10.7MHz). Implements a double conversionsuperheterodyne architecture based on DDS

• A/D D/A converters and DDC/DUC : Altera FPGA (Cyclone II EP2C70)

• Signal processing: Fixed point DSP (TMS32C6416) and software runningon a GNU/Linux PC.

INDEX

INTRODUCTION


SUMMARY

Receving section block diagram




RF Front-end and FPGA setupINDEX

INTRODUCTION


SUMMARY

FPGA

RF Front-end




RF Front-end block diagramINDEX

INTRODUCTION


SUMMARY

Antenna

Relay

Receiver

Transmitter

ControlUnitOscillators

To FPGA ADC

From FPGA DAC

Antenna

Relay

Receiver

Transmitter

ControlUnitOscillators

To FPGA ADC

From FPGA DAC

• Double conversion superheterodyne architecture• Half-duplex transceiver: two common blocks• Oscillators based on DDS (v0), later DDS+PLL (v1)• Control unit: manages front-end and interacts with operator using a PC




Receiver block diagramINDEX

INTRODUCTION


SUMMARY

3-30 MHz ADC

BW = 1.0 MHz112 MHz

122.7 MHz

82-109 MHz

BW 1 MHz10.7 MHz

Image-rejection Filter 3-30MHz

Band Pass Filters 3-30MHz RF Amp

≤ 20 dB

DDS

Low Pass10.7 MHz

AGC

≤ 75 dB

RS232

Antenna

µControllerCARDS12

3-30 MHz ADC

BW = 1.0 MHz112 MHz

BW = 1.0 MHz112 MHz

122.7 MHz

82-109 MHz

BW 1 MHz10.7 MHzBW 1 MHz10.7 MHz

Image-rejection Filter 3-30MHzImage-rejection Filter 3-30MHz

Band Pass Filters 3-30MHz

Band Pass Filters 3-30MHz RF Amp

≤ 20 dB≤ 20 dB

DDS

Low Pass10.7 MHz

AGC

≤ 75 dB

RS232

Antenna

µControllerCARDS12

• Double conversion superheterodyne (up-mixing).• 1st IF: 112MHz and 2nd IF: 10.7MHz.• Frequency step: 1Hz.• Sensitivity (@1MHz): -70dBm.• Microcontroller-based RX, TX, AGC and ALC control.• Modular assembly.• TX output power +20dBm.• External power amplifier (linear class A) 5W.




INDEX

INTRODUCTION


SUMMARY

TXRX OL

ANT

Control

PS

19’’ subrack 3U form board (100x160mm) with connector DIN41612Rear: digital signalsFront: analog signalsPower Supply: 220VAC and 12VDC



MAIN PROBLEMS AND SOLUTIONS

INDEX

INTRODUCTION


SUMMARY



3. Summary



MAIN PROBLEMS AND SOLUTIONS• DDS (Direct Digital Synthesis) ⇒ is a method of producing an analog

waveform,usually a sine wave,• by generating a time-varying signal in digital form

• converted into analog signals using a DAC

• DDS is a standard in radio equipment oscillator.

• NCO (Numeric Controlled Oscillator) ⇒ also called

• Advantages

• Capable of generating a variety of waveforms (sine, triangle, square)• Preferred form of signal generation nowadays• Fast switching capability (freq. hopping systems (phase-continuous))• High precision ⇒ sub Hz (mHz) and sub degree phase tuning• Digital circuitry

• Small size (single chip) ⇒ fraction of analog synthesizer size• Fewer components per system - low cost• Small low-powered devices – portability• Easy implementation (no Barkhaussen criterion, PLL (LPF design))• Fewer assembly operations / reduced product reject rates

INDEX

INTRODUCTION


SUMMARY




Typical DDS ArchitectureINDEX

INTRODUCTION


SUMMARY

1/1/ffoutout1/1/ffoutout

1/1/ffclkclk

1/1/ffoutout

1/1/ffclkclk

1/1/ffoutout

1/1/ffclkclk

ffoutout==ffclkclkFFrr

22NNAccumAccum--ulatorulator

NN24 to24 to48bits48bits

WW14 to14 to16bits16bits

SineSineLookupLookupTableTable

RR10 to10 to14bits14bits

LowLowPassPassFilterFilter

SineSineWaveWave

FFrr

Digital CircuitsDigital Circuits

DD--toto--AAConv.Conv.

• Sampling theory (sinc(x)) • Nyquist: Fundamental signal <= Fclk/2 (1/3 better)• Filter required to eliminate unwanted products




Broadband Transceiver oscillator board (v0)INDEX

INTRODUCTION


SUMMARY

TXRX OL

ANT

Control

PS

DDS 1

DDS 2

OL 2

OL 1

Clock

DDS 1

DDS 2

OL 2

OL 1

Clock

DDS 1

DDS 2

OL 2

OL 1

Clock




Spurs !!! Worst problem in DDSINDEX

INTRODUCTION


SUMMARY

13IDeTIC Seminar

• AD9835 (fclk=50MHz)• Spurs situation and quantity depend on output frequency (become birdies)• Mix up AGC

16th May



Spurs !!! Worst problem in DDSINDEX

INTRODUCTION


SUMMARY

14IDeTIC Seminar

• AD9835 (fclk=50MHz)• Spurs situation and quantity depend on output frequency (become birdies)• Mix up AGC

16th May



Another problem: Clock reference purityINDEX

INTRODUCTION


SUMMARY

Comparison: frequency output purity 400MHz Clock vs Agilent Generator




Spurs sourcesINDEX

INTRODUCTION


SUMMARY

• A DDS have four principal sources of spurs. Most of them are predictable.• Reference clock: highest purity and freq. possible. Spurs next to carrier.

Must have constant amplitude to avoid spurs.16th May IDeTIC Seminar 17


MAIN PROBLEMS AND SOLUTIONSAnalog Devices solution:

SpurKiller Technology: The Results on a DDS Output SpurINDEX

INTRODUCTION


SUMMARY

AFTERBEFORE

500 kHz / DIVISION500 kHz / DIVISION

OUTPUT FREQUENCY = 166 MHzFclk = 500 MSPS




INDEX

INTRODUCTION


SUMMARY

Analog Devices solution:

SpurKiller Technology

• Use an auxiliary DDS channel to add in a signal at the same frequency andamplitude as the spur, but 180° out of phase with the highest spur…

AD9911 DDS core

Σ Σ COS(X)

FTW

FrequencyAccumulator

PhaseOffset

143216 10

DAC

DDS Channelfor spur reduction

DDS Channelfor amplitudemodulation

DDS Channelfor phase

modulationRegister Register Register

It’s all in the Digital Domain!

• Spurs are therefore predictable. • In addition, the relative phase of each spur does not change.




Adopted solution was: Change synthesizer topologyINDEX

INTRODUCTION


SUMMARY

DDS Used as PLL Reference

20IDeTIC Seminar16th May

nref

2RFF FNM=

÷N

Loop Filter

Phase/ Frequency Detector VCO

RFDDSFref

M

Take advantage of PLL low phase noise and spurs, and DDS frequency resolution



Broadband Transceiver oscillator board (v1)INDEX

INTRODUCTION


SUMMARY

PLL: NB4N441 DDS: AD9835

DDS

PLL TCXO: 50MHz

• DDS output: 10 to 13MHz




Comparison: oscillator board v0 (green) vs v1 (blue)INDEX

INTRODUCTION


SUMMARY

Phase noise improvement: 20dB




PLL output: ImprovesINDEX

INTRODUCTION


SUMMARY




INDEX

INTRODUCTION


SUMMARY



3. Summary




INDEX

INTRODUCTION


SUMMARY

Measurement SAW Filter bandwidth

• Limited filters with 1MHz bandwidth• Only found TFS112 (fc=112.32MHz, BW(3dB)=1.1MHz, L=12.5dB)• SAW (Surface Acoustic Wave) filter

• Low S11 (high mismatch) BRICK!! (Z=3.5Kohms)• High attenuation• 40dB band-stop• 2.55 form factor• Redesign TRX OLs




INDEX

INTRODUCTION


SUMMARY



3. Summary




INDEX

INTRODUCTION


SUMMARY

• Problem: Big/good ears in a noisy environment (HF band)• Point 1) AGC algorithm must keep constant 1MHz varying signals

power at ADC input (few bits left for weak signals)• Point 2) Narrow band interference (NBI) intentionally (jamming) or

unintentionally (Broadcast radio stations) within signal or BW

NBI demo video

Two HF broadband TCVR 10 meters apart tuned to 14MHz freq.Function generator as jammer (pure tone)Taking output at BaseBand (10.7MHz) RF Front-end receiverUsing a Agilent VSA (Vector Signals Analyzer) 89600SShowing 700KHz around 10.7MHz

Innovation #8 of the Top 10 Most Wanted Wireless Innovations(Interference Mitigation Techniques) Software Defined Radio andCognitive Radio (CR)

Source: Wireless Innovation forum




IDeTIC Seminar 2816th May

INDEX

INTRODUCTION


SUMMARY

• Wireless Innovation Forum proposed solutions(They are already used in high-end systems but want lower cost and widespread)

Power control throughout the communications systemonly enough power to maintain communications at the minimum acceptable level.

Adaptive beam-forming to maximize antenna gain in the direction of thecommunication path and minimize gain in the interference direction.

Adaptable data rate to the minimum rate needed for the communication.

Adaptive frequency control to increase frequency separation of the interferencesources from the desired radio path.

Adaptive receive filtering to provide better rejection of the interference balancedagainst possible sensitivity loss.

Improved roaming algorithms(change sites or systems to one that has a better SINR).

Change channel coding algorithms to relax the required signal to interferenceplus noise ratio at the expense of more data overhead.

Some of them are difficult to implement at HF (heavier and larger antennas,noisy environment, worldwide coverage, propagation)



INDEX

INTRODUCTION


SUMMARY

• Our proposed solution

Interference must be mitigated enough to let the ADC work under proper condx.Cancellation process after AD conversion (digital filtering)

Two phases: detection (SW) & mitigation (HW)

Detection: Zero crossing and Compressive Sensing (Random Demodulator)Mitigation: Variable notch filter (BW3dB 50KHz; BW50dB 25KHz; Tunable 10.2~11.2MHz)

Bandpass filtering (xtal), LPF+HPF (need Q > 200)technological challenge: low Q components (filters), diff. tunable and speed processing




INDEX

INTRODUCTION


SUMMARY

• Our proposed solution (cont)

Desired response Low Pass Filter + High Pass Filter

Wien-Robinson active filter Sallen-Key 2nd order

A(dB)

50

3BW=50KHz

BW=10kHz

f(MHz)10

LPF

HPF




INDEX

INTRODUCTION


SUMMARY

• Our proposed solution (end)Double T Band-reject LC filter

Schematic BW measurement




INDEX

INTRODUCTION


SUMMARY



3. Summary





INDEX

INTRODUCTION


SUMMARY

• Problem: Broadband signals on nonlinear amplifier

OFDM Signal PAPR (~10dB)

- Peak to average power ratio (PAPR)is one major drawback of OFDM.

- Requires power amplifier (PA) to beoperated in the linear region, resultingin poor efficiency.

- 1KW PA operating at 100W

- Commercial power amplifiers (PA)have nonlinear characteristics andneed to be linearized.

Innovation #5 of the Top 10 Most Wanted Wireless Innovations(Techniques to minimize power amplifier spectral regrowth innon-continuous spectral environment)

Source: Wireless Innovation forum




INDEX

INTRODUCTION


SUMMARY

• Problem: Broadband signals on nonlinear amplifier (cont) Increasing gain (spectral regrowth)

16 tones 25KHz spaced (400KHz)

- Careful design to avoid intermodulationproducts (below 1dB compress point)

- Poor effiency- Dirty spectrum- Interference to other band users



INDEX

INTRODUCTION


SUMMARY

• Problem: Broadband signals on nonlinear amplifier (cont)

SPE Expert 1K-FA E&I A1000800W 1000WAmateur equipment Professional EquipmentClass AB Class ASome segments in HF band 300KHz - 35MHz

low HD & IMD




INDEX

INTRODUCTION


SUMMARY

• Problem: Broadband signals on nonlinear amplifier (end)

Some techniques to overcome distorsioned PA ouput:

PREDISTORSION

- adds harmonic content at phaseangles that cancel out the spursthat the nonlinear RF PA creates

- allows driving RF PA closer tosaturation, which improvespower efficiency.

PAPR REDUCTION TECHNIQUES

- Clipping and Filtering: Let the signal clip and filter out of band signal- Coding schemes: Try to avoid the case with all the subcarrier with same phase.- …




INDEX

INTRODUCTION


SUMMARY



3. Summary




Problem: Most of antennas have a very narrow bandwidth (10% fc)INDEX

INTRODUCTION


SUMMARY

27MHz (higher f more BW)

SWR CurvesTransmitting 1MHz BW signal at 10MHz (fc)

Filter behaviour (S11)




Solution: Fatter elements (CAGE DP), introduce losses (T2FD) orINDEX

INTRODUCTION


SUMMARY

• Cage dipole• x2 broader BW compared to dipole

• T2FD (Tilted Terminated Folded Dipole)• 30% RF Power converted heat at resistor• -3 to +3dBi gain• Modest size and cost• No need electronic matching• Used by Army and Civil Guard




INDEX

INTRODUCTION


SUMMARY

Solution (cont.): or Log Periodic antenna

• can operate on a wide frequency band (10:1)• has the ability to provide directivity and gain (4-8dBi)• radiation and impedance characteristics repeated as a logarithmic function of freq

• NBI: different polarization• R&S HE016 antenna



SUMMARY

INDEX

INTRODUCTION


SUMMARY

Remember: Broadband system introduces a number of challenges

• It needs to coexist with traditional narrowband systems

• So need to tackle problems as sensitivity to strong narrow sigs (AGC mute)

• Take into account the low linearity of commercial PA (IMD and interferesother users).

• Necessary to have broadband antennas capable to work with these sigs.

Future Trends

• Harris 25KHz bandwidth

• New HF broadband SDR transceiver 25KHz with same form factor as HFDVL modem. TX using FPGA, RX analog front-end+FPGA


www.idetic.eu

Seminar in

Broadband HF transceiverdesign experiences

Thanks for your attention!!Any question?

Speaker: Baltasar Pérez-Díaz <[email protected]>

Author: Baltasar Pérez Díaz

Multimedia Room, Polivalente II, 2nd floor

Campus de Tafira, Las Palmas 16th May, 2014

practical application of dds

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