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7.5 Read-Only Memory (ROM)

permanent binary information is stored no data input line

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each OR gate has 2k inputs, which are connected to each of the outputs of the decoder

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programming the ROM : close or open the fuse

0 : open, 1 : connect

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data at 11110? 5

Combinational Circuit Implementation

internal operation of ROM

• memory unit that contains a fixed pattern of stored words • unit that implements a combinational circuit each output terminal is the output of a Boolean function

)29,....,3,2,0(),,,,( 012347 IIIIIAEx)

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Example 7.1

Design a combinational circuit that accepts 3-bit number and generates its square number. Use ROM.

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B0=A0 & B1=0 so need to generate four outputs with the ROM 8 x 4 ROM

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types of ROMs

mask programming the ROM PROM EPROM EEPROM

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Combinational PLDs

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7.6 Programmable Logic Array

similar to the PROM, but with no decoder does not generate all the minterms array of AND gates are programmed to generate any product term of the input variables

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For what exclusive OR?

F1=AB’+AC+A’BC’ F2=(AC+BC)’

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tabular form of the fuse map

Inputs (path between inputs and AND gates) 1 : variable is true form 0 : variable is complemented form - : variable is absent

Outputs (path between AND and OR gates) 1 : included in the product term - : open terminal

Then, T? C? 13

size of a PLA

number of inputs, product terms, outputs

Ex) for n inputs, k product terms, m outputs n buffer-inverter gates k AND gates m OR gates m XOR gates 2n x k connections in input—AND array k x m connections in AND—OR array m connections associated with XOR gates

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Design a digital system with a PLA need PLA programming table

• mask programmable • field programmable • minimize the distinct product terms because of the finite number of AND gates (simplify both true and complement of each function)

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Ex) Implement the following with a PLA

)7,6,5,0(),,(

)4,2,1,0(),,(

2

1

CBAF

CBAF

Selected combination

'''

)'(

2

1

CBAACABF

BCACABF

find both true and complement of the functions in sum of products

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7.7 Programmable Array Logic

fixed OR array and a programmable AND array not flexible as the PLA product term cannot be shared among OR gates each function is simplified by itself Boolean functions must be simplified to fit into each section

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Ex) Design the following with PAL

)13,12,8,2,1(),,,(

)15,11,10,8,7,6,5,4,3,2,0(),,,(

)15,14,13,12,11,10,9,8,7(),,,(

)13,12,2(),,,(

DCBAz

DCBAy

DCBAx

DCBAw

DCBADACwDCBADACCDBAABCz

DBCDBAy

BCDAx

CDBAABCw

''''''''''''''

'''

''''

PAL programming table

simplify

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Not used AND gates?

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FPGA & BCD Counter

FPGA ; HBE-COMBO II-DLD

• H/W


• Block Diagram


• New Project ( Using HBE-COMBO II-DLD)


• Device Setting


• Setting between FPGA Pin & Code variation



• After Setting,

Run Start->

Start Analysis &

Elaboration



Double click!


• Run Programmer


• HBE-COMBO II-DLD ‘s Pin Map.

• Pin Map data is on eclass.(Excel)

BCD Counter

• BCD Counter (Binary –Coded Decimal) in Binary system

• In computing and electronic systems, binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight

• Ex )

BCD Counter

• BCD Counter (Binary –Coded Decimal)

• Counts from 0 to 9 and then repeats.

• Ex ) 0000 (0) => 0001 (1) => 0010 (2)=> 0011 (3)=> 0100 (4)=> 0101 (5)=> 0110 (6)=> 0111 (7)=> 1000 (8)=> 1001 (9)=> 0000(0) …….

• How can we express a BCD Counter as a circuit?

BCD Counter

• BCD Counter is composed of a JK Flip-flop.

• Ex ) 4bit Hexadecimal Synchronous up counter ( 0x0000~0x1111)

BCD Counter

• 4bit Hexadecimal Synchronous up counter

• JK Flip-Flop’s code

What is this??

BCD Counter


• User Delay Delay is 1ps

BCD Counter


• 4bit Hexadecimal Synchronous up counter ‘s code

BCD Counter


• 4bit Hexadecimal Synchronous up counter testbench‘s code

BCD Counter


• 4bit Hexadecimal Synchronous up counter wave

BCD Counter


• Using this, make a BCD Synchronous up counter.

•

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