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i POWER QUALITY IMPROVEMENT BY DYNAMIC VOLTAGE RESTORER AND UNIFIED POWER QUALITY CONDITIONER USING FUZZY LOGIC FARIDULLAH KAKAR A thesis submitted in fulfilment of the requirements for the award of the degree of Master of Engineering (Electrical) Faculty of Electrical Engineering UniversitiTeknologi Malaysia SEPTEMBER 2015

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Page 1: POWER QUALITY IMPROVEMENT BY DYNAMIC VOLTAGE …eprints.utm.my/id/eprint/54071/4/FaridullahKakarMFKE2015.pdf · model ujian dibina dalam perisian Matlab / Simulink. Kedua-dua peralatan

i

POWER QUALITY IMPROVEMENT BY DYNAMIC VOLTAGE RESTORER

AND UNIFIED POWER QUALITY CONDITIONER USING FUZZY LOGIC

FARIDULLAH KAKAR

A thesis submitted in fulfilment of the

requirements for the award of the degree of

Master of Engineering (Electrical)

Faculty of Electrical Engineering

UniversitiTeknologi Malaysia

SEPTEMBER 2015

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iii

I dedicate this thesis to my friend Abdul RehmanAl-Najjar (deceased), my wife and

my sons, Shamsher Ali Khan and Altamash Ali Khan

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iv

ACKNOWLEDGEMENT

In the name of Allah almighty, the most Beneficent and the most Merciful.

With gratitude to Allah for His mercy that has given me strength, patience,

perseverance and health for timely completion of this imperative assignment.

Guidance of our Holy Prophet Hazrat Muhammad (S.A.W), throughout my life and

in this task in particular, is truly acknowledged. After that patronage, support and

backing of my supervisor Dr. Mohd Hafiz Bin Habibuddin and co-supervisor Prof.

Ir. Dr. Abdullah Asuhaimi Bin Mohd Zin is undeniable. Their encouragement and

support not only enabled me pursue new ideas but also facilitated my self

confidence. Notably, their incisive feedback afforded me to progress in the precise

direction. This task could not have been accomplished without their keen

observations, incessant advices, and persistent suggestions in each and every part of

this work.

I would like to thank every person involved in the proceedings of this final

project report preparation. I would like to extend my special gratitude to Mr. Abdul

Rehman Al-Najjar (deceased) for motivating me to proceed in the right direction

whenever I wavered.

I am greatly indebted to UniversitiTeknologi Malaysia for providing me the

platform. My sincerest thanks to Dr. Mahmoud Pasaran, Mr. SohailKhokhar and all

my colleagues and laboratory mates for their help and support. Finally, I truly

endorse the warm backing and care of my family exclusively my wife whose endless

support enhanced my agility to make her dream come to reality. I also salute my two

sons for all the bears for the sake of my studies.

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v

ABSTRACT

Voltage sag and harmonics have significant negative impact on power

quality. Propagation of distorted waveform in the system ultimately instigates a

range of power quality issues. Protection against this situation is necessary because it

adversely affects reliability and quality of power supply. Custom Power Devices

(CPD) such as Dynamic Voltage Restorer (DVR) and Unified Power Quality

Conditioner (UPQC) provide a level of reliability and power quality that is urgently

required. The basic purpose of this thesis is to implement new control strategies to

mitigate voltage sag/swell and to suppress harmonics to evaluate CPD performance.

The CPD system is controlled by Fuzzy Logic Controllers (FLCs) with 49 rules and

25 rules, respectively and their performances are compared with Proportional

Integral (PI) controller. This thesis focuses on FLC with fewer rules to avoid

complexity, reduce computation time and consume less memory space. The proposed

strategy depends on d-q transformation, phase-locked loop synchronization and

constant DC link voltage. Simulation results depict better reliability of fuzzy logic

techniques with non-linear loads when compared with PI technique. The capability

of DVR and UPQC using FLC especially with fewer rules is demonstrated using test

models built in Matlab/Simulink software. Both equipments potentially restore sags

and improve overall harmonic profile while reducing total harmonic distortion to

values within the prescribed criterion set by IEEE standards. The proposed FLC

approach with reduced rule base, is superior to PI and FLC with 49 rules, assures

effective performance, with normalization and tuning of parameters especially the

membership functions and scaling factors. It yielded excellent voltage profile with

best possible compensation during system contingencies, conforming to the IEEE

standards that affirm FLC as an effective solution for power quality problems.

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vi

ABSTRAK

Voltan lendut dan harmonik mempunyai kesan negatif yang signifikan

terhadap kualiti kuasa. Perambatan gelombang terherot dalam sistem peda akhirnaya

menyebabkan pelbagai isu kualiti kuasa yang lain. Perlindungan terhadap keadaan ini

adalah perlu kerana ia memberi kesan buruk terhadap kebolehpercayaan dan kualiti

bekalan kuasa. Peranti Kuasa Langganan (CPD) seperti Pemulih Voltan Dinamik

(DVR) dan Penyesuai Kualiti Kuasa Disatukan (UPQC) menyediakan tahap

kebolehpercayaan dan kualiti kuasa yang amat diperlukan. Tujuan asas tesis ini

adalah untuk melaksanakan strategi kawalan baru untuk mengurangkan voltan lendut

dan menyekat harmonik bagi menilai prestasi CPD. Sistem CPD dikawal oleh

pengawal logik kabur (FLC) dengan 49 peraturan dan 25 peraturan, dan prestasi

mereka dibandingkan dengan pengawal kamiran berkadaran (PI). Tesis ini

menumpukan kepada FLC dengan peraturan yang sedikit untuk mengelakkan

kekompleksan, mengurangkan masa pengiraan dan menggunakan ruang memori yarg

kecil. Strategi yang dicadangkan bergantung kepada transformasi d-q, penyegerakan

Gelung Terkunci Fasa dan voltan pautan DC malar. Keputusan simulasi

menunjukkan kebolehpercayaan yang lebih baik dengan teknik logik kabur dengan

beban tidak linear berbanding teknik PI. Keupayaan DVR dan UPQC menggunakan

FLC khususnya dengan bilangan peraturan yang rendah ditunjukkan menggunakan

model ujian dibina dalam perisian Matlab / Simulink. Kedua-dua peralatan

berpotensi menghilangkan lendut dan meningkatkan keseluruhan profil harmonik di

samping mengurangkan Jumlah Herotan Harmonik kepada nilai-nilai dalam kriteria

yang ditetapkan oleh piawaian IEEE. Pendekatan FLC yang dicadangkan dengan

asas peraturan yang dikurangkan, PI dan FLC yang baik dengan 49 peraturan akan

memastikan prestasi yang berkesan, dengan penormalan dan penalaan parameter

terutama rangkap keahlian dan faktor penskalaan, menghasilkan pengaturan voltan

yang sangat baik dan meningkatkan profil voltan sewaktu kesilapan diluar jangkaan

sistem, yang mematuhi piawaian IEEE dan mengesahkan FLC sebagai penyelesaian

yang berkesan untuk masalah kualiti kuasa.

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vii

TABLE OF CONTENTS

CHAPTER TITLE PAGE

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENTS vii

LIST OF TABLES xi

LIST OF FIGURES xiii

LIST OF ABREVIATIONS xviii

LIST OF SYMBOLS

LIST OF APPENDICES

xxi

xxii

1 INTRODUCTION 1

1.1 Background of Study 1

1.2 Problem Statement 5

1.3 Objectives of the Research 6

1.4 Scopes of the Research 6

1.5 Significances of the Research 7

1.6 Organization of Thesis 8

2 LITERATURE REVIEW 9

2.1 Power Quality (PQ) 9

2.2 Main PQ Sources, Causes and Effects 10

2.3 Solutions and methods to Improve PQ 10

2.4 Custom Power Devices (CPD) 11

2.4.1 Dynamic Voltage Restorer (DVR) 12

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2.4.1.1 Principle of Operation 12

2.4.1.2 Operating Modes of DVR 13

2.4.1.3 Configuration of DVR 15

2.4.2 Unified Power Quality Conditioner

(UPQC) 17

2.4.2.1 Basic Configuration of

UPQC 18

2.4.2.2 Series and Shunt APF’s

ratings in UPQC 19

2.4.2.3 Functions performed by

UPQC 20

2.5 Control issues related to DVR and UPQC 21

2.5.1 Review of DVR Controllers 23

2.5.1.1 PI Controller 23

2.5.1.2 Repetitive controller 28

2.5.1.3 Proportional Resonant (PR)

controller

28

2.5.1.4 Hysteresis Controller 29

2.5.1.5 Optimal Predictive Control

(OPC) 30

2.5.1.6 Adaptive Neuro-Fuzzy

Inference System (ANFIS)

31

2.5.1.7 Fuzzy Logic Control (FLC) 32

2.5.2 Review of UPQC Controllers 33

2.5.2.1 Proportional-Integral-

Derivative (PID) & PI

controllers 33

2.5.2.2

2.5.2.3

2.5.2.4

2.5.2.5

Hysteresis controller

Power Angle Control

(PAC)

Pulse Width Modulation

(PWM)

Synchronous Reference

Frame (SRF)

35

38

39

39

2.5.2.6 Artificial Nueral Netwok

(ANN) and Adaline 40

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2.5.2.7 Fuzzy Logic Control (FLC) 41

2.6 Summary 43

3 METHODOLOGY 45

3.1 Introduction 45

3.2 DVR Simulation Model 47

3.2.1 DVR Single-line Diagram 48

3.2.2 Proposed DVR Controls 51

3.2.2.1 Sag Detection 51

3.2.2.2 Reference Voltage

Compensation for PI

controller with PWM

generator 54

3.2.2.3 Reference Voltage

Compensation for FLC

with PWM Generator 57

3.3 UPQC Simulation Model 63

3.3.1 Control Philosophy 67

3.3.1.1 Shunt inverter reference

current detection ( d-q

Method) 68

3.3.2.2 Shunt inverter control based

on PWM 69

3.4 Summary 70

4 RESULTS AND DISCUSSIONS 72

4.1 DVR Simulation Results 72

4.1.1 Case 1: Linear load 72

4.1.2 Case 2: Non-linear load 78

4.1.3 Case 3: FOC-IM load 84

4.2 UPQC Simulation Results 89

4.2.1 Case 1: Linear load 90

4.2.2 Case 2: Non-linear load 101

4.2.3 Case 3: FOC-IM load 111

4.3 Comparison of DVR and UPQC for voltage

harmonics reduction 123

4.4 Comparison of FLC (49 rules) and FLC (25 124

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x

rules) with DVR

4.5

4.6

4.7

4.8

4.9

Comparison of FLC (49 rules) and FLC (25

rules) with UPQC

Comparison of FLC (49 rules) and FLC (25

rules) with DVR in terms of Memory Space

Comparison of FLC (49 rules) and FLC (25

rules) with UPQC in terms of Memory Space

Comparison of FLC (49 rules) and FLC (25

rules) with DVR in terms of Computational

Time

Comparison of FLC (49 rules) and FLC (25

rules) with UPQC in terms of Computational

Time

125

.

126

127

128

128

4.10 Summary 129

5 CONCLUSIONS AND FUTURE WORK 131

5.1

5.2

Conclusion

Significant contribution of the Thesis

131

134

5.3 Future work 134

REFERENCES

Appendices A1-C1

134

144-151

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xi

LIST OF TABLES

TABLE NO. TITLE PAGE

2.1 Summary of main PQ problems, their causes and

effects 10

3.1 Parameters of DVR test system 49

3.2 FLC with 49 rules (Mac-vicar and Whelan decision

matrix) (Hilloowala and Sharaf (1996)) 59

3.3 FLC with 25 rules 62

3.4 UPQC system parameters 64

4.1

Summary of voltage THD for DVR with PI, FLC (49

and 25 rules) with linear load 77

4.2

Summary of voltage THD for DVR with PI, FLC (49

and 25 rules) with non-linear load 83

4.3

Summary of voltage THD for DVR with PI, FLC (49

and 25 rules) with FOC-IM load 88

4.4

Summary of voltage THD for UPQC with PI, FLC

(49 and 25 rules) with linear load 96

4.5

Summary of current THD for UPQC with PI, FLC

(49 and 25 rules) with linear load 99

4.6

Summary of voltage THD for UPQC with PI, with

FLC (49 and 25 rules) with non-linear load 107

4.7

Summary of current THD for UPQC with PI, with

FLC (49 and 25 rules) with non-linear load 110

4.8

Summary of voltage THD for UPQC with PI, with

FLC (49 and 25 rules) with FOC-IM load 118

4.9 Summary of current THD for UPQC with PI, with

FLC (49 and 25 rules) with FOC-IM load 121

4.10 Summary of voltage THD comparison of DVR and

UPQC with PI, with FLC (49 and 25 rules) 123

4.11 Summary of voltage THD comparison of FLC (49

rules) and FLC (25 rules) with DVR 124

4.12 Summary of voltage THD comparison of FLC (49 126

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4.13

4.14

4.15

4.16

rules) and FLC (25 rules) with UPQC

Summary of memory space comparison of FLC (49

rules) and FLC (25 rules) with DVR

Summary of voltage THD comparison of FLC (49

rules) and FLC (25 rules) with UPQC

Summary of computational time of FLC (49 rules)

and FLC (25 rules) with DVR

Summary of computational time of FLC (49 rules)

and FLC (25 rules) with UPQC

127

128

128

129

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xiii

LIST OF FIGURES

FIGURE NO. TITLE PAGE

2.1 Protection mode of DVR (Kumari and Garg 2013) 14

2.2 Standby mode of a DVR (Ali, et al., 2013) 15

2.3 Basic DVR configuration (Dib, et al., 2011) 15

2.4 VSI using IGBT (Singh, et al., 2013) 16

2.5 Block diagram of UPQC (Axente, et al., 2011) 18

3.1 Research work flow chart 47

3.2 Single-line diagram of DVR test model 48

3.3 Matlab / Simulink DVR model 50

3.4 Matlab / Simulink Model for sag detection 52

3.5 Circuit Model of DVR Test System (Tiwari and Gupta

2010) 55

3.6 PI controller basic structure (Tiwari and Gupta 2010) 56

3.7 Phase-Modulation firing angle control δ (Kumar, S.

2007; Ganesh, S. et al., 2011] 57

3.8 FLC FIS editor 58

3.9 FLC MF’s editor, rule viewer and surface viewer 61

3.10 FLC simulink sub system for 25 rules 63

3.11 UPQC test system model 65

3.12 Matlab / Simulink UPQC model 66

4.1 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LG fault with linear load 73

4.2 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LLG fault with linear load 73

4.3 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LLLG fault with linear load 74

4.4 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LG fault

with linear load 75

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xiv

4.5 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LLG fault

with linear load 75

4.6 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LLLG fault

with linear load 76

4.7 Capacitor voltage for DVR (a) with PI (b) FLC (49

rules) and FLC (25 rules) with linear load 78

4.8 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LG fault with non-linear load 79

4.9 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LLG fault with non-linear

load

79

4.10 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LLLG fault with non-linear

load

80

4.11 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LG fault

with non-linear load

81

4.12 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LLG fault

with non-linear load

81

4.13 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LLLG fault

with non-linear load

82

4.14 Capacitor voltage for DVR (a) with PI (b) FLC (49

rules) and FLC (25 rules) with non-linear load 83

4.15 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LG fault with FOC-IM load 84

4.16 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LLG fault with FOC-IM load 85

4.17 Voltage waveform (a) without DVR (b) injected

voltage (c) with DVR for LLLG fault with FOC-IM

load

85

4.18 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LG fault

with FOC-IM load

86

4.19 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LLG fault

with FOC-IM load

87

4.20 Voltage THD (a) without DVR (b) with DVR (c) with

FLC (49 rules) (d) with FLC (25 rules) for LLLG fault

with FOC-IM load

87

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xv

4.21 Capacitor voltage for DVR (a) with PI (b) FLC (49

rules) and FLC (25 rules) with FOC-IM load 89

4.22 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LG fault with linear load 90

4.23 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LLG fault with linear load

91

4.24 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LLLG fault with linear load

91

4.25 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LG fault with linear load 92

4.26

Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LLG fault with linear load

93

4.27 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LLLG fault with linear load

93

4.28 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LG

fault with linear load

94

4.29 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLG

fault with linear load

95

4.30 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLLG

fault with linear load

95

4.31 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LG

fault with linear load

97

4.32 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLG

fault with linear load

97

4.33 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLLG

fault with linear load

98

4.34 Capacitor voltage for UPQC (a) with PI (b) FLC (49

rules) and FLC (25 rules) with linear load

100

4.35 Capacitor current for UPQC (a) with PI (b) FLC (49

rules) and FLC (25 rules) with linear load 100

4.36 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LG fault with non-linear

load

101

4.37 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LLG fault with non-linear 102

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xvi

load

4.38 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LLLG fault with non-linear

load

102

4.39 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LG fault with non-linear

load

103

4.40 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LLG fault with non-linear

load

104

4.41 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LLLG fault with non-linear

load

104

4.42 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LG

fault with non-linear load

105

4.43 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLG

fault with non-linear load

106

4.44 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLLG

fault with non-linear load

106

4.45 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LG

fault with non-linear load

108

4.46 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLG

fault with non-linear load

108

4.47 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLLG

fault with non-linear load

109

4.48 Capacitor voltage for UPQC (a) with PI (b) FLC (49

rules) and FLC (25 rules) with non-linear load 110

4.49 Capacitor current for UPQC (a) with PI (b) FLC (49

rules) and FLC (25 rules) with linear load 111

4.50 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LG fault with FOC-IM load 112

4.51 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LLG fault with FOC-IM

load

112

4.52 Voltage waveform (a) without UPQC (b) injected

voltage (c) with UPQC for LLLG fault with FOC-IM

load

113

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4.53 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LG fault with FOC-IM load 114

4.54 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LLG fault with FOC-IM

load 114

4.55 Current waveform (a) without UPQC (b) injected

current (c) with UPQC for LLLG fault with FOC-IM

load

115

4.56 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LG

fault with FOC-IM load

116

4.57 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LG

fault with FOC-IM load

116

4.58 Voltage THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLLG

fault with FOC-IM load

117

4.59 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LG

fault with FOC-IM load

119

4.60 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLG

fault with FOC-IM load

119

4.61 Current THD (a) without UPQC (b) with UPQC (c)

with FLC (49 rules) (d) with FLC (25 rules) for LLLG

fault with FOC-IM load

120

4.62 Capacitor voltage for UPQC (a) with PI (b) FLC (49

rules) and FLC (25 rules) with FOC-IM load 122

4.63 Capacitor current for UPQC (a) with PI (b) FLC (49

rules) and FLC (25 rules) with FOC-IM load 122

LIST OF ABREVIATIONS

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xviii

ANFIS - Adaptive Neuro-Fuzzy Inference System

ANN

- Artificial Neural Netwok

APF - Active Power Filters

CPD - Custom Power Devices

SCD - Synchronous Current Detection

CSI - Current Source Inverter

d - direct or real

DC - Direct Current

DFT - Discrete Fourier Transform

DOL - Direct-On-Line

d-q-0 - transformation direct-quadrature-zero transformation

DSTATCOM - Distribution STATic COMpensator

DVR - Dynamic Voltage Restorer

DWT - Discrete Wavelet Transform

EMI - Electro-Magnetic Interference filter

FACTS - Flexible AC Transmission Systems

FFT - Fast Fourier Transformer

FL - Fuzzy Logic

FLC - Fuzzy Logic Controller

FOC-IM - Field-Oriented Control Induction Motor

FORTRAN - FORula TRANslating System programming language

FT - Fourier Transform

GTO - Gate Turn Off thyristor

ICC - Indirect Current Control

IEEE - Institute of Electrical and Electronic Engineers

IGBT - Insulated-Gate Bipolar Transistor

IGCT - Integrated Gate-Commutated Thyristor

Ki - integral

Kp - proportional

LLG - Double Line-to-Ground fault

LLLG - Triple Line-to-Ground fault

LPF - Low Pass Filter

LQR - Linear Quadratic Regulator

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xix

max-min - maximum-minimum

MC-DVR - Multi Converter DVR

MRA - Multi-Resolution Analysis

MSPWM - Multiple Sinusoidal Pulse Width Modulation

MVAr - Mega Volt Ampere reactive

NB - Negative Big

NM - Negative Medium

NS - Negative Small

OCC - One Cycle Control

OCCC - One Cycle Current Control

OPC - Optimal Predictive Control

PBT - Power Balance Theory

PCC - Point of Common Coupling

PI - Proportional Integral

PID - Proportional Integral Derivative

PL - Positive Large

PLL - Phase-Locked Loop

PM - Positive Medium

PQ - Power Quality

PR - Proportional Resonant

PS - Positive Small

PSCAD - Power System Computer Aided Design

PS-SPWM - Phase-Shifted Sinusoidal Pulse Width Modulation

PV - Photo-Voltaic

PWM - Pulse Width Modulation

Ref - Reference

RMS - Root Mean Square

SLG - Single Line-to-Ground fault

SPWM - Sinusoidal Pulse Width Modulation

SRF - Synchronous Reference Frame

SVM - Space Vector Modulation

THD - Total Harmonic Distortion

UCES - Ultra-Capacitor Energy Storage

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UPQC - Unified Power Quality Conditioner

UVT - Unit Vector Template generation

VAr - Volt Ampere reactive

VSC - Voltage Source Converter

VSI - Voltage Source Inverter

Z - Zero

ZSI - Z-Source Inverter

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LIST OF SYMBOLS

A - Ampere

ce - Change in error

H - Henry

e - error

I - Current

IL - Load Current

kV - kiloVolt

kW - kiloWatt

L - Inductance

p.u - Per unit

R - Resistance

V - Voltage

VL - Load voltage

Vth - Thevenin equivalent system voltage during fault

X - Inductance

X/R - ratio of total inductive reactance to its total

resistance

Y - Star

Z - Impedance

Zth - Thevenin equivalent load Impedance

α - Alpha

β - Beta

Δ - Delta

δ - Sigma

μ - Micro

π - Pi

ω - Omega

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LIST OF APPENDICES

APPENDIX TITLE PAGE

A1 IEEE Std. 1100-1992 Recommended Practice for

Powering and Grounding Electronic Equipment

144

A2 IEEE 519-1192 “Recommended practices and

requirements for Harmonic control” for voltage

145

A3 IEEE 519-1192 “Recommended practices and

requirements for Harmonic control” for current

146

A4 IEEE 1159-1995 “Recommended Practice for

Monitoring Electric PQ” for time domain duration

147

A5 IEEE 1159-1995 “Recommended Practice for

Monitoring Electric PQ” for magnitude deviation

148

B1

Matlab / Simulink function for memory space for

DVR and UPQC

149

B2

Matlab / Simulink function for computational time

for DVR and UPQC

150

C1

Further authentication of the results produced by

Matlab / Simulink function for memory space using

task manager (for DVR and UPQC)

151

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CHAPTER 1

INTRODUCTION

1.1 Background of Study

Contemporary power system is an arrangement of composite networks

involving various generating stations and load centers integrated through extensive

transmission and distribution networks. Power supply interruptions and outages are a

nuisance affecting domestic, commercial and in particular industrial customers. This

results in considerable financial losses with high impact on production costs. In the

present competitive world market, dispersed generation trends and general awareness

of the people towards better quality of power have forced the restructuring of power

systems. Expectations on improved quality and reliability of power supply to the

customers have increased.Power Quality (PQ) is defined in IEEE Std book Electrical

Power System Quality (Dugan, et al., 1996) as “the concept of powering and

grounding sensitive electronic equipment in a manner suitable for the equipment”

(Reid, 1996). This phenomenon incorporates all possible situations in which power

system supply voltage (voltage quality) or load current (current quality) waveforms

deviate from sinusoidal waveform. PQ is a criterion for proper electrical system to

function efficiently without compromising the performance (Singh and Dwivedi,

2012).

PQ problems encompass severe disturbances such as voltage sag, voltage

swell, current and voltage harmonics, and unbalanced load. Inferior PQ leads to low

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power factor and low efficiency, generating large current unbalance. PQ disturbances

may be either caused by the quality of the supply voltage (source) or by the quality

of the current drawn by the load. Advanced power electronic devices and equipments

widely employed nowadays draw harmonic currents and reactive power from AC

mains due to their inherent non-linear V-I characteristics. Such non-linear loads

pollute the network by injecting current harmonics. This consequently deteriorates

utility voltage and causes a drop in supply voltage and amplifies losses.

Considerable attention has been given to PQ due tomodern industrial shift

towards mechanized automation. This inclination trend relies heavily on sensitive

power electronic devices. These devices are much more susceptible to distortion in

supply voltage than their previous generation counterparts. This has caused

complications not only for the utilities but also for the end-users themselves. Modern

power semiconductor devices are in all likelihood not only the prime source of

harmonic insertion but also augment reactive power in the system. Rigorous

utilization of power converters as rectifiers creates non-sinusoidal current thus

polluting the supply. Consequently, the harmonic components will contaminate

voltage at the point of common coupling. Besides, these polluted voltages and

currents proliferate into the supply system, amplify losses, cause measurement

imprecision and create severe electromagnetic compatibility problems. Introduction

of system harmonics have brought PQ issues to the fore-front and compelled

suffering utilities to provide distortion-free sinusoidal power supply. At the same

time customers are also bound by regulations through proper standards to curb the

quantity of harmonic currents and unbalance in all the three phases due to different

loading conditions which augments harmonic distortions that a load may produce.

The situation calls for alleviation of PQ issues in the shape of “Custom Power

Devices (CPD)” which are capable enough to present customized resolution to PQ

problems. CPD improve the quality and reliability of power delivered to customers

and are based on electronic power converters and provide the ability to make quick

adjustments to control the electrical system. The strength and benefits of these

devices become diverse, when they are combined and this concept leads to the

evolution of multi-type CPD. The function of CPD is not only to minimize the

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effects of voltage sag and swell, but also to limit the harmonic distortion caused by

the presence of non- linear loads in the network (Ghosh and Ledwich, 2001;

Khadkikar and Chandra, 2008; Renuga, et al., 2013).

Current harmonics are considered as the most frequent PQ issues while

voltage sag is the most detrimental. These problems incur huge financial losses.

Research reveals that voltage sag/swells and harmonic distortions at the Point of

Common Coupling (PCC) are mainly liable to severe impact on sensitive loads. Even

worse case scenario is the malfunctioning of system equipments (Kolhatkar and Das,

2007; Hari, et al., 2011; Khadkikar, 2013).

To reduce such unwanted nuisances, passive power filters were primarily

used. Well-designed passive filters can be implemented in large sizes of MVAr

ratings and provide almost maintenance free service due to absence of rotating parts.

These filters are more economical to implement than their rotating counterparts i.e.,

synchronous condensers. A fast response time of the order of one cycle or less can be

obtained. These compensation equipments have some drawbacks as they are not

suitable for variable loads, since, they are designed for a specific reactive power as

well as variation of the load impedance can detune the filter. To overcome passive

power filters characteristic limitations such as producing superfluous resonance and

augmenting harmonic currents, a step further in fruitful research efforts bore the

development and manifestation of more advanced Active Power Filters (APF)

technology. These however are presently very uneconomical but their installation

proves indispensable for solving PQ problems in distribution networks such as

compensation of harmonic current, reactive current and voltage sag. Ultimately, this

would ensure a pollution free system with increased reliability and quality. APF

family include different devices commonly called CPD. The concept of custom

power was introduced by (N.G. Hingorani) in 1995. This term illustrates the value-

added power that electric utilities will present to their customers. The enhanced level

of power consistency with minimal interruptions and less discrepancy will be

guaranteed by the application of power electronic controllers either to the utility

distribution systems or at the supply end of industrial and commercial customers.

CPD are the proficiently progressive face of APF family and are pertinent to power

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distribution systems for accomplishing stability and reliability of power supply to a

large extent. Fundamentally, APF inject harmonic currents of the same magnitude

but opposite polarity to cancel harmonics. Nevertheless harmonic distortions are only

part of the problem, while fault or load variations may cause voltage sag. CPD

comprise of DSTATCOM (Distribution STAtic COMpensator), DVR (Dynamic

voltage restorer) and Unified Power Quality Conditioner (UPQC) etc. DSTATCOM

is connected in shunt with the power system whereas DVR is a series connected

device that injects series voltage to recompense supply voltage.DVR is recognized as

the most appropriate to protect sensitive loads against PQ disturbances. DVR role is

not only voltage sag mitigation but also harmonic distortion reduction caused by

non-linear loads in the network.

UPQC is the more advanced type of CPD combining two APFs. It’s good

control methods with precise recognition of the disturbance signal, swift processing

of reference signal and high dynamic response facilitates in preferred compensation.

It charters two voltage source inverters (VSI): one act as a series APF (DVR) and the

other as shunt APF (D-STATCOM), connected back to back through common DC-

link capacitor. The former is regarded as the most fitting to prevail over voltage

related problems while the latter as the most promising to manage current related

problems. Practical implementation of such devices emerges feasible, given that

superior quality supply voltage and drawn current is stressed profoundly.

Nevertheless, simultaneous installation of both DVR and DSTATCOM may not be a

worthwhile solution. Their combined configuration with back-to-back inverter

system called UPQC was proposed by Fujita and Akagi (Fujita and Akagi, 1995).

UPQC is ever since popularly used enormously and regarded as the ultimate solution

for inferior PQ predicament by several researches (Sadaiappan, et al., 2010; Hari, et

al., 2011).

UPQC is probably the best CPD dealing with both load current and supply

voltage imperfections. It consists of two VSI sharing the same capacitive DC-link. It

is a very versatile device that can perform both the functions of load compensation

and voltage control simultaneously.

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1.2 Problem Statement

Inadequacy of conventional PQ improvement equipment has necessitated

vibrant and adaptable resolution to PQ problems. This has propelled the development

of CPD. The contemporary and promising CPD that deals with voltage related issues

is DVR, while the more flexible CPD is UPQC which deals mutually with load

current and supply voltage imperfections. Various researches have been performed in

relation to their performances under a variety of fault conditions with different

conventional linear and non-linear control systems with the application of linear,

non-linear and heavy loads. To be regarded as established equipments their

performances ought to be scrutinized further with different control strategies for

frequently utilized load conditions under frequently occurring fault conditions in the

distribution system. This needs modelling and development of both the equipments

along with their control schemes and algorithms for PQ improvement. Fuzzy Logic

Control (FLC) has gained momentum during the last decade or so especially in

power systems because it neither requires precise mathematical formulations nor fast

processors. Besides it needs less data storage in the form of knowledge base which

includes Membership Functions (MF’s) and rules.

Conventionally, the more advanced non-linear FLC system has been utilized

with 49 rules which are computationally demanding and time consuming. As the

number of the linguistic variables increases, the computational time and required

memory increase. This is because the implementation of FLC require a large

computational time for processing each step time in order to compute the appropriate

control value to be applied to the system. Therefore, a reduction of the large fuzzy

rule base is required. Although some studies have tried lesser rules (even 9 rules) but

they cannot come up with conclusive performance of the equipments. An effort is

needed to come up with the best possible number of rules for FLC system so that

both DVR and UPQC can perform satisfactorily, conforming to IEEE laid standards

for both harmonic compensation and voltage sag minimization and hence results in

enhanced PQ. Studies showed that FLC with 49 rules takes double computational

time as compared to FL with 25 rules (Karakose and Akin, 2010). Rule reduction

will definitely lessen computation effort and reduce time consumption for

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processing. Performance analysis and comparison of this reduced rule control

strategy with classical PI and FLC with 49 rules for further evidence is necessitated

under harmonic generating loads including Field Oriented Control-Induction Motor

(FOC-IM) under frequently occurring fault conditions.

1.3 Objectives of the Research

The objectives of this research are as follows:

i) To develop simulation models of DVR and UPQC in distribution system

subject to the presence of voltage sag and harmonics with various load

and fault conditions.

ii) To design PI, FLC (49 rules) and FLC (25 rules) systems for DVR and

UPQC to tackle voltage sag and harmonic problems in distribution

network.

iii) To investigate effectiveness of PI, FLC (49 rules) and FLC (25 rules)

based DVR and UPQC and tuning and normalization of FLC (25 rules) to

get similar or better performance in accordance with the IEEE 519-1159

standards.

1.4 Scopes of the Research

The scopes of this research are shown below:

i) The system is a distribution network comprising of two 11 kV adjacent

feeders

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ii) Performance of the designed models of DVR and UPQC is evaluated for

mitigating PQ issues such as voltage sag/swell and harmonic distortions.

iii) Performance of DVR and UPQC is investigated using PI control and FLC

under linear, non-linear and FOC-IM load conditions.

1.5 Significances of the Research

Significances of this research are:

i) Develop FLC knowledge base which includes MF’s and rules suitable for

proper functioning of DVR and UPQC. The increasing need is to design

highly reliable, efficient and low complexity controllers. FLC’s are able

to make effective decisions on the basis of linguistic information. The

application of FLC will definitely not only minimize computation efforts

but also improve performance of these equipments in relation to voltage

sag and harmonic mitigation.

ii) Formulate the best possible control strategy for DVR and UPQC which

will help improve PQ of the system with different load and fault

conditions. Amongst the three control strategies which are PI, FLC with

49 rules and reduced25 rules the focus will be on FLC method with 25

rules. Although, many works have been reported in literature regarding

reduction of rules at the expense of enhanced complexities. The easier

approach of tuning of parameters as well as scaling factors and

normalization help excel the performance of this strategy as compared to

PI control method. As compared to FLC 49 rules its performance will be

improved as well as reduction in the computation time and memory space

with the exception of a few results.

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1.6 Organization of Thesis

Contents of the thesis are arranged as follows.

Chapter 2 defines the different terms and concepts associated with PQ and

CPD. Literature survey is also included in this chapter.

Chapter 3 explains in detail the methodology adopted in this work. Various

control strategies employed for both DVR and UPQC are taken into consideration to

improve PQ.

Chapter 4 presents discussion of the results of PI, FLC (49 rules) and FLC

(25 rules) control strategies for DVR and UPQC Matlab / Simulink test models.

Chapter 5 summarizes the conclusion of this work and future work of this

research.

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