PLL Phase Noise Figures of Merit TI Precision Labs – Clocks and Timing

Presented by Dean Banerjee

Prepared by Liam Keese

1

Phase lock loop (PLL) overview

2

R Divider

1/D

Output DividerReference

Oscillator

1/N

1/R

VCOLoopFilterPhase

Detector/Charge Pump

N Divider

Z(s)s

KVCO

+KPD

-

Phase lock loop (PLL) transfer functions

3

fVCO

1/N

1/RZ(s)

sKVCO

+KPD

-

Block Transfer Function

OSC 1

𝑅∙

𝐺(𝑠)

1 + 𝐺(𝑠) ∙ 𝐻

R/N

Dividers

𝐺(𝑠)

1 + 𝐺(𝑠) ∙ 𝐻

Phase

Detector

1

𝐾𝑃𝐷∙

𝐺(𝑠)

1 + 𝐺(𝑠) ∙ 𝐻

VCO 1

1 + 𝐺(𝑠) ∙ 𝐻

𝑯 𝒔 = 𝑯 = 𝟏/𝑵

𝑮 𝒔 = 𝑲𝑷𝑫 × 𝒁(𝒔) × 𝑲𝑽𝑪𝑶

𝒔

𝒔 = 𝒋 ∙ 𝟐𝝅𝒇

Reference oscillator noise transfer function

4

Block Transfer

Function

Response Low Frequency

Response

High Frequency

Response

OSC 1

𝑅∙

𝐺(𝑠)

1 + 𝐺(𝑠) ∙ 𝐻

Low Pass 20 ∙ log (𝑁/𝑅) 20 ∙ log (𝐺(𝑠)/𝑅)

BW

20 x log(N/R)G

ain

(d

B)

Offset Frequency (Hz)

| G(s) |

1 R ∙

G(s)1 + G(s) ∙ H

1 R ∙

Feedback N divider noise transfer function

5

Block Transfer

Function

Response Low Frequency

Response

High Frequency

Response

N (or R)

Divider

𝐺(𝑠)

1 + 𝐺(𝑠) ∙ 𝐻

Low Pass 20 ∙ log (𝑁) 20 ∙ log (𝐺(𝑠))

BW

20 x log(N)G

ain

(d

B)

Offset Frequency (Hz)

| G(s) |

G(s)1 + G(s) ∙ H

Phase det./charge pump noise transfer function

6

Block Transfer

Function

Response Low Frequency

Response

High Frequency

Response

Phase Det./

CP gain

1

𝐾𝑃𝐷∙

𝐺(𝑠)

1 + 𝐺(𝑠) ∙ 𝐻

Low Pass 20 ∙ log (𝑁/𝐾𝑃𝐷) 20 ∙ log (𝐺(𝑠)/𝐾𝑃𝐷)

BW

20 x log(N/KPD)G

ain

(d

B)

Offset Frequency (Hz)

| G(s) |

1 KPD

∙

G(s)1 + G(s) ∙ H

1 KPD

∙

VCO noise transfer function

7

Block Transfer

Function

Response Low Frequency

Response

High Frequency

Response

VCO 1

1 + 𝐺(𝑠) ∙ 𝐻

High Pass −20 ∙ log (𝐺(𝑠)) 1

BW

1G

ain

(d

B)

Offset Frequency (Hz)

1

1 + G(s) ∙ H

1

G(s)

N ∙

-180

-170

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

0.1 1 10 100 1000 10000 100000

Ph

ase N

ois

e (

dB

c/H

z)

Offset (kHz)

PLL VCO Reference Total

PLL closed loop noise sources

The size of these regions will change depending on loop bandwidth

Ref OSC PLL VCO

PLL normalized phase noise

9

Log(Frequency)

BW

Everything Except VCO

VCO

Ga

in (

dB

)

0

20∙log(N)

• PLL flat noise FOM (PN1Hz)

– PLL noise floor normalized to1 Hz

– N-counter added noise = 20 log (N)

• PLL flicker noise (PN10kHz)

– Usually dominates at offset below 1 kHz

– PLL 1/f normalized to 1 GHz output and 10kHz offset

PLL noise simulation

10

• PLL FOM

– PN1Hz = PN – 20 ∙ log(N) – 10 ∙ log(fPD)

• PLL Flicker

– PN10kHz = PN(Δf) -20 ∙ log(fout/1GHz)

-10 ∙ log(10kHz/ Δf)

PLL phase noise shaping levers

PLL Functional Block To minimize Noise

contribution…

Why?

Phase Detector/Charge

Pump

Maximize charge pump gain

(KPD) (up to a certain point)

The phase detector noise

contribution is proportional to

1/(KPD)2

R-counter and N-counter

divide ratios

Maximize phase detector

compare frequency this

minimizes N

The noise contribution of the

R and N dividers is

proportional to N2.

Reference oscillator Use highest frequency practical

and use R > 1 if possible. If

deciding between maximizing R

and minimizing N, minimize N.

The noise contribution from

the reference oscillator is

proportional to (N/R)2

To find more technical resources and search products, visit ti.com/clocks

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Quiz

• True or false: Reducing N-divider value will decrease PLL noise by 20log(N)

• True or false: The reference oscillator does not contribute to PLL in band noise

• True or false: Increasing the charge pump current setting will reduce PLL noise

• True or false: The VCO tuning constant KVCO only has an effect on noise

outside of the PLL loop bandwidth

13

Quiz

• True or false: Reducing N-divider value will decrease PLL noise by 20log(N)

• True or false: The reference oscillator does not contribute to PLL in band noise

• True or false: Increasing the charge pump current setting will reduce PLL noise

• True or false: The VCO tuning constant KVCO only has an effect on noise

outside of the PLL loop bandwidth

14

PLL Transient Response Quiz TI Precision Labs – Clocks and Timing

Presented by Dean Banerjee

Prepared by Vibhu Vanjari

1

Quiz

• True or False: The phase margin is the phase of the open loop transfer function

when the gain of the PLL is equal to 0 dB.

• True or False: Phase margins under 30º should be avoided to enhance the

stability of the PLL and minimize ringing.

• True or False: Larger bandwidths lead to shorter lock times.

2

Quiz

• True or False: The phase margin is the phase of the open loop transfer function

when the gain of the PLL is equal to 0 dB.

– The phase margin is the distance of the phase from -180 degrees when the gain of

the PLL is equal to 0 dB.

• True or False: Phase margins under 30º should be avoided to enhance the

stability of the PLL, and minimize ringing.

– Phase margins under 30º can lead to instability, peaking in the closed loop filter

response, and ringing in the transient response.

• True or False: Larger bandwidths lead to shorter lock times.

– Wider loop bandwidths allow the PLL to track changes in frequency faster.

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