Pixel Sensors for a Linear Colliderfrom Physics Requirements to Beam Test Validation

M BattagliaUC Berkeley and LBNL

with P Denes, D Bisello, D Contarato, P Giubilato, L Glesener, B Hooberman, C Vu

KEK, January 30, 2008

Requirements for ILC VertexingRequirements for ILC Vertexing

a (m) b (m GeV)

LEP 25 70

SLD 8 33

LHC 12 70

RHIC II 14 12

ILC 5 10

tip pba /tip pba /

ILC Vertexing

Mokka+MarlinReco

Towards multi-TeVTowards multi-TeV

Requirements for the Vertex TrackerRequirements for the Vertex Tracker

tp

ba

Asymptotic I.P. Resolution [ a ]

Multiple Scattering

I.P. Term [ b ]

Polar Angle Coverage

Space / TimeGranularity

Technology (pitch, S/N)Geometry (Rin, Rout)

Technology (thickness)Geometry (Rin, NLayers)

Technology (r/o electronics)Geometry (zLayers)

Technology (pitch, r/o architecture, r/o time)Geometry (Rin)

Effect of VTX performance on accuracy of BR(H0bb, cc, gg) at 0.35-0.5 TeV already assessed by various studies using parametric simulation:

Yu et al.J. Korean Phys. Soc. 50 (2007);

Kuhl, DeschLC-PHSM-2007-001;

Ciborowski,LuzniakSnowmass 2005

Channel Change Rel. Change in

Stat. Uncertainty

Hbb

Hcc

Hgg

Geometry:5 4 layer VTXThickness: 50 m 100 m

+ 0%

+15%

+ 5%

Hccpoint:4 m 6 m4 m 2 m

+10%-10%

Hcc

Thickness:

50 m 100 m +10%

Physics vs. VTX configurationHiggs BRs accuracy vs. I.P. Resolution

Geometry IP (m)Rin 1.2 cm 1.7 cm

c purity=0.7 c = 0.49

c = 0.46

Rin 1.2 cm 2.1 cm

c purity=0.7 c = 0.49

c = 0.40

HPS c purity=0.7 c = 0.29

tp/74

tp/104

tp/145.5

tp/74

Hawking, LC-PHSM-2000-021

tp/1511

Physics vs. VTX configurationCharm Tagging vs. I.P. Resolution

Study change in efficiency of charm tagging in Z0-like flavour composition

Parametrising the Vertex Tracker Response

Provide extrap. resolutionfor various set of parameters (Rin, ladder thickness, ...) andVXD models obtained using G4 + Kalman Filter Fit:

extrap vs. p and for isolated trks and ptcs in jets.

Example:extrap vs. p for isolated s baseline VXD02 , ladder thickness x 2 , Rin = 18 mm :

Pair Background and VTX Detector

Geometry of innermost layer bound by distribution of incoherent pairs;Study z point of crossing of electrons with cylinder as function of radius Rfor various magnetic fields B;

z

R

Pair Background and VTX DetectorCompare results of GUINEA_PIG + Mokka simulation with R2 scaling:

M.B., V Telnov,Proc. 2nd Workshopon Backgrounds at MDIWorld Sci, 1998

Beam tests using 0.05 - 1.0 GeV e- beams at LOASIS and ALS to validate simulation.

LDRD-2 responseto ALS beam halo

Generate library of background pair hits to overlay to hits to perform detailed simulation of occupancy, rejection and effect on patrec.

CMOS Pixels for ILCCMOS Pixels for ILC

CMOS pixel sensors with analog, fast r/o attractive for ILC, requirements on particle extrapolation accuracy constrain pixel pitch and readout architecture,significant experience from IPHC group, applications to real experiments before ILC;

Achieving < 3 m single point resolution with pixel pitch ~ 15-20 m, requires analog readout + charge interpolation: defines requirement on ADC accuracy to 4-5 bits if pedestal can be subtracted before digitisation;

Power consumption constrains number of bits for ADC accuracy;

Machine induced backgroundsconstrain readout time;

D. Grandjean/IPHC

ILC Vertex Tracker:ILC Vertex Tracker:

SensorThickness(~50 m)

Asymptotic Resolution

MultipleScattering

+LadderSupport

+ServicesCooling

[80 mW/cm2]

S/N+

ClusterSize

Power Dissipation

[<1mW/ADC]

Backgrounds

+Physics

Airflow removes

70-100mW/cm2

< 0.5 mW/ADC

25 MHz r/o25 s/512 pixel colO(1 %) occupancy

( demonstrated)[ R&D in progress]

ReadoutSpeed

[25-50 MHz]

Pixel Size(10-20m) S/N

+ Cluster

SizeADC

Resolution[~5 bits]

5 hits/BX X 9 (20 m pixels)/hit

= 250 k hits cm-2

Requirements and R&D Streams

Monolithic Pixel Sensor R&D at LBNLMonolithic Pixel Sensor R&D at LBNL

Analog Pixel Architecture Binary Pixel Architecture

AMS 0.35m-OPTOLDRD-1 (2005):10, 20, 40m pixels

LDRD-2 (2006):20m pixels,in-pixel CDS3T and SB pixels

OKI 0.15m FD-SOILDRD-SOI-1 (2007):10m pixels,analog & binary pixels

OKI 0.20m FD-SOILDRD-SOI-2 (2008):10-15m pixels,analog & binary pixels

…

• Charge Interpolation [ ~ a/(S/N)]• In-pixel CDS & On-chip Digitisation• Fast Readout

• Small Pixels [ = pitch/ ]• In-pixel Discr. & Time Stamping• In-situ Charge Storage

12

LDRD-3 (2007):20m pixels,in-pixel CDSon-chip 5-bit ADCs

Chip Design: P. Denes

Multiple Scattering and Sensor ThicknessMultiple Scattering and Sensor Thickness

Preserving track extrapolation accuracy to bulk of particles at low momentum requires ultra-thin sensors and mechanical support:

Sensor Thickness

m

a

m

b

m

25 3.5 8.9

50 3.7 9.6

125 3.8 11.7

300 4.0 17.5

Mokka+MarlinSimulation of VXD02

tp

ba

need thin monolithic pixel sensor.

e+e- HZbb+- at 0.5 TeV

CMOS Sensor Back-thinningCMOS Sensor Back-thinning

Back-thinning of diced CMOS chips by partner Bay Area company: Aptek.Aptek uses grinding and proprietary hot wax formula for mounting die on grinding plate:

Chip mounted on PCB with reversible glue and

characterized

Chip removed from PCB

Back-thinning Chip re-mounted andre-characterized

Backthinning yield ~ 90 %, chip thickness measured at LBNL after processing:“50 m” = m , “40 m” = m; three chips fully characterised:)750( )641(

Thin sensitive epi-layer makes CMOS Pixel sensors in principle ideally suited for back-thinning w/o significant degradation of performance expected (especially S/N), but questions arise from earlier results; SEM Image of

CMOS Pixel Chip

Bulk Si

Epi SiSiO + Metal

40 40 mmBack-thinned Sensor TestsBack-thinned Sensor Tests

Study change in charge collection and signal-to-noise before and after back-thinning:Mimosa 5 sensors (IPHC Strasbourg), 1 M pixels 17 m pitch, 1.8x1.8 cm2 surface

55FeDetermine chip gain and S/N for 5.9 keV X rays

Collimated LaserCompare charge collectionin Si at different depths

1.5 GeV e- beam Determine S/N and cluster size for m.i.p.

S/N

CMOS sensors back-thinning feasibleNIM A579 (2007) 675

LDRD-2 Chip LDRD-2 Chip LDRD-2 Chip LDRD-2 Chip

LDRD-2 Chip:

AMS 0.35-OPTO process~ 14 m epitaxial layer

Chip features analog pixel cell with 20 transistors in 20x20m2 pixel pitch providing in-pixel CDS, power cycling, different bias options, 3 and 5 m diode sizes, rolling-shutter operation with two parallel outputs of 48 x 96 pixels each.

Size: 1.5x1.5 mm2

6 matrices of 20x20 m2 pixels;

LDRD-2: In-Pixel CDS LDRD-2: In-Pixel CDS

Stored reference and pixel level with pulsed laser light:

diode Cref

Cpixel

-

= pedestal subtracted signal20m

Digitisation at end of pixel column limited in precision by speed and power dissipation: advantageous to subtract pedestal level in-pixel with correlated double sampling.

LDRD-2: In-Pixel CDS LDRD-2: In-Pixel CDS

=

PixelReference

PixelLevelw/ beam

Example of observed response with 1.2 GeV e electrons

Pedestal

LDRD-2: 1.2 GeV eLDRD-2: 1.2 GeV e Beam Test Beam Test

LDRD-2 tested on

ALS 1.2 GeV e- beams;

Cluster Event Display

Noise ~ 45 ENC

LDRD-2: 120 GeV p Beam TestLDRD-2: 120 GeV p Beam Test

T966Preliminary5 m diode

T966Preliminary3 m diode

Preliminary results @ 21oCat 1.25 MHz

<Nb. of Pixels in Cluster>

4-5

<S/N> ~16

LDRD-2 tested at FNAL MTestwith T966 CMOS Pixel Telescopeon 120 GeV proton beam:

LDRD-2: 25 MHz readout testLDRD-2: 25 MHz readout test

Results show no appreciable degradation of response up to maximum tested frequency of 25 MHz (r/o time 184 s)

LDRD-21.35 GeV e beam

Cluster S/N

LDRD-255Fe

Operate LDRD-2 at different r/o speed

LDRD-3 Chip LDRD-3 Chip LDRD-3 Chip LDRD-3 Chip

LDRD-3 Chip:

AMS 0.35-OPTO process,received October 2007, ADC currently under test.

Third generation chip features same pixel cell as LDRD-2 with in-pixel CDS and 5-bit successive approximation fully differential ADCs at end of columns. CDSsubtraction performed at digitisationlevel;

Size: 4.8x2.4 mm2

matrix of 96x96 of 20x20 m2 pixels;

LDRD-SOI-1 ChipLDRD-SOI-1 ChipLDRD-SOI-1 ChipLDRD-SOI-1 Chip

Specialised 0.15m FD SOI process with high resistivity bulk and vias offered through KEK within R&D collaborative effort;

SOI appealing to industry for low-power devices, ultra-low power stand-by;

SOI process offers appealing opportunity for monolithic pixel sensors, removing limitations from commercial CMOS;

Chip with 10x10 m2 pixels, both 3T analog and digital architectures;

(courtesy Arai/KEK)

TCAD Simulation

pp Guardring

Floating|

p

LDRD-SOI-1LDRD-SOI-1 Analog Pixels: Lab Tests Analog Pixels: Lab Tests

Significant backgating effect observedin single transistor test, expect analogchip section functional for Vd < 20 V

Charge collection properties tested with fast pulsed IR laser focused to 20m:signal loss for long integration times interpreted as combined effect of backgating and leakage current:

LDRD-SOI-1LDRD-SOI-1 Analog Pixels: Lab Tests Analog Pixels: Lab Tests

Study Leakage vs. Temperature w/ 1.384 ms integration time and CDS

Study Depletion Thickness vs. SubstrateVoltage using 1060nm laser spotcurves represents dVd

LDRD-SOI-1LDRD-SOI-1 Analog Pixels: Analog Pixels: pp & & nn Irradiation Irradiation

Exposure to 1-20 MeV neutrons(1011 n/cm2) shows no appreciable degradation of noise:

First irradiation performed with 30 MeV protons (2.5x1012 p/cm2) shows evidence of charge build-up in BOX from T tests;

ALS 1.35 GeV e

Cluster Display

LDRD-SOI-1LDRD-SOI-1 Analog Pixels: Beam Test Analog Pixels: Beam Test

Vd

(V)Clusters/Evt

w/ beamClusters/Evt

w/o beam<Nb Pixels> Signal MPV

(ADC)

S/N

1 9.7 0.05 3.31 132 8.9

5 14.0 0.12 3.39 242 14.9

10 7.8 0.20 3.31 316 15.0

15 3.9 0.01 2.45 301 13.6to appear in NIM A (2007)

First Beam Signalon SOI Pixel ChipALS 1.35 GeV e

LDRD-SOI-1 LDRD-SOI-1 Digital Pixels: Beam Test Digital Pixels: Beam Test

Vd (V)

Clusters/Evt w/ beam

Clusters/Evt w/o beam

<Nb Pixels>

20 3.62 0.04 1.78

25 5.81 0.04 1.32

30 8.31 0.04 1.26

35 1.60 0.01 1.14

Digital pixel consists of 2T + comparator and latch, no internal amplification for minimum power dissipation, total 15 transistors in 10x10m2

ALS 1.35 GeV e

SOI Pixel ChipSOI Pixel Chip

VTX Simulation, Reconstruction, AnalysisVTX Simulation, Reconstruction, AnalysisVTX Simulation, Reconstruction, AnalysisVTX Simulation, Reconstruction, Analysis

Physics Benchmarks

PixelSimCluster Reconstruction

PixelAna

ALS & FNAL Beam Test Data

G4/Mokka

Sensorand Ladder

Characterization

Track Fitand Extrapolation

VTX Pattern Recognition

lcio

lcio

Jet Flavour Tagging+ CDF Vtx Fit

lcioMarlin

Sensor Simulation

Thin Pixel Pilot TelescopeThin Pixel Pilot Telescope

Layout: 4 layers of 50 m thin MIMOSA 5 sensors (17m pixels) + reference detector;

Sensor spacing: 1.5 cm

1234

beam

Beam: 1.5 GeV e- from LBNL ALS booster at BTS 120. GeV p at MTest, FNAL

• First beam telescope based on thin pixel sensors;• System test of multi-layered detector in realistic conditions.

TPPT at ALSTPPT at ALS

Run 056 Event 001

Perform detailed studies of ILC VTX particle tracking with various, controllable, levels of track density (0.2-10 tracks mm-2) under realistic conditions;

TPPT Data e+e- HZat 0.5 TeV

Distance of Closest Hit

TPPT layout chosen to closely resemble ILC VTX.

TPPT at ALSTPPT at ALS

Alignment performed using ATLAS optical survey machineand track alignment;

Extrapolation Resolutionon Layer 1: = m matches ILC requirements.

= 9.4 mTrack Sample Residual

(m)

2+3 Hits Tracks 9.43 Hits Tracks 8.9High Density 9.5Low Density 9.2

NIM A579 (2007) 675

T-966 Beam Test Experiment at FermilabT-966 Beam Test Experiment at Fermilab

TPPT-2 telescope: 4 layers of 50m thick MIMOSA-5 sensors, ILC-like geometry, extrapolation resolution on DUT ~ 4-5 m

Study LDRD sensors: • single point resolution & sensor efficiency, • response to inclined tracks,• tracking capabilities in dense environment,• vertex reconstruction accuracy with thin target,

Validate simulation, test patrec and reco algorithms.

Beam Test at FNAL MBTF 120 GeV p beam-line (T-966) (UC Berkeley + LBNL + INFN, Padova + Purdue U. Collaboration)

4mm

Cu

Tar

get

TPPT-2 DUT

4-layeredTelescope

DUT

T-966 Beam Test Experiment at FermilabT-966 Beam Test Experiment at Fermilab

Experimental Setup4 layers of 50m thick MIMOSA-5 chipsprecisely mounted on PC boards with cut through below chip, DUT on XY stage, finger scintillator coincidence for trigger

T-966 at FermilabT-966 at Fermilab

First run June-July 2007: operated in various configurations: TPPT only, w/ LDRD-2, w/ target;Operated at 20oC through forced cold air cooling, significant day/night temperature effects, need repeat track alignment daily, first preliminary results:

4

3

2

1

T-966 at FermilabT-966 at Fermilab

Cluster Pulse Height Cluster Pixel Multiplicity

Track Alignment of T966 TelescopeTrack Alignment of T966 Telescope

T-966 at FermilabT-966 at Fermilab

Preliminary

Data 5.4 m

MC 5.1 m

Residualson 1st Plane

T-966 at FermilabT-966 at Fermilab

Residual on 1st Layer vs S/N of Hits

e+e- HZbb+- at 0.5 TeVe+e- HZbb+- at 0.5 TeV

ALS

ALS

LOASIS

LOASIS

MTest

MTest

Track Extrapolation ResolutionTrack Extrapolation Resolution

TP

PT

@A

LS

T966 @

MT

est

T-966 at FermilabT-966 at Fermilab

Reconstructed 120 GeV p interaction in Cu target

T-966 at FermilabT-966 at Fermilab

Vertex Reconstruction for 120 GeV p interactions4m

m C

u T

arge

t

Very Preliminary

T-966 at FermilabT-966 at Fermilab

Vertex Reconstruction for 120 GeV p interactions

R&D program on pixel sensors for ILC is progressing despite significantbudget and manpower limitations;

Various technologies/architecture being studied, mostly complementary to concurrent efforts in Europe and Asia;

R&D at LBNL supported by Lab strategic funding and synergies with existing activities (STAR HFT, ATLAS pixels, pixel R&D for BES);

CMOS pixel chip with in-pixel CDS and fast r/o designed and tested,new chip with in-chip 5-bit ADCs under test;

First pixel chip in SOI technology successfully tested on e beam;

Experience with beam Telescope based on thin CMOS pixels for trackingand vertexing.