picture to be sent (640x480) displayed picture (800x600) host vga de2 board
TRANSCRIPT
Picture to be sent(640x480)
Displayed Picture(800x600)
HOSTVGA
DE2 Board
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
WBS
WBS
WBS
WishboneINTERCON
Host(Matlab)
VGA Display
WBM
Message Pack Decoder
CheckSum
UART RX
RX Path
WBM
Message Pack Encoder
CheckSum
UART TX
TX Path
WBM
WBS
VESACtrl
SG TOP
DisplayController
DC FIFO 100MHz40MHz
SG WBMMemoryManagement
SDRAM Arbiter
Mem CtrlWR
Mem CtrlRD
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
WBS
WBSWBS
WishboneINTERCON
Host(Matlab)
VGA Display
WBM
Message Pack Decoder
CheckSum
UART RX
RX Path
WBM
Message Pack Encoder
CheckSum
UART TX
TX Path
WBM
WBS
VESACtrl
SG TOP
DisplayController
DC FIFO 100MHz40MHz
SG WBM
MemoryManagement
SDRAM Arbiter
Mem CtrlWR
Mem CtrlRD
Flus
h
UART RX MP Dec RAM 1
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Wr
Mem Ctrl Rd
SDRAM Arbiter
WBS
RAM 2 MP Enc UART TX
WBMWBM
WBS
INTERCON
Decompressor
FIFO
VESACtrl.
req_ln_trig &Pixels, VSync
Pixel Manager(Req for Data)
WBM
MU
X
Synthetic Pic. Gen
WBS1
2
3
A
E
5 D
Flus
h
Dual Clk FIFO
WBMWBM
C
Z
wr_rd_bank
wr_cntwr_cnt_en
8 bit
8 bit8 bit
8 bit
8 bit
8 bit
Hsync,VSync
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBS4
INTERCO
N
Y
TYPEReg
Disp. Reg
Frame Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
CRC ERR
EOF ERR
R1
B
R2
R1 – Ram 816 bitsR2 – Ram 168 bits
- 100 MHz - 40 MHz
UART_SE UART_PE
OR
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
UART RX MP Dec
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Rd
SDRAM Arbiter
WBS
MP Enc UART TX
WBMWBM
WBS
INTERCON
req_ln_trigW
BM
WBS1
2
3
A
E
5 D
WBMC
Z
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBS4
INTERCO
N
Y
TYPEReg
Type Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
Mem Ctrl Wr
WBMB
Dual Clk FIFO
VESACtrl.
- 100 MHz - 40 MHz
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
SG WBM
SG TOP
SG Reg
UART RX MP Dec
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Rd
SDRAM Arbiter
WBS
MP Enc UART TX
WBMWBM
WBS
INTERCON
req_ln_trig
WBM
WBS
WBM
Z
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBSIN
TERCON
Y
TYPEReg
Type Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
Mem Ctrl Wr
WBM
Dual Clk FIFO
VESACtrl.
- 100 MHz - 40 MHz
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
SG WBM
SG TOP
Type Reg
UART RX
MP Dec
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Rd
SDRAM Arbiter
WBS
MP Enc UART TX
WBMWBM
WBS
INTERCON
req_ln_trigW
BM
WBS
WBM
Z
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBSIN
TERCON
Y
TYPEReg
Type Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
Mem Ctrl Wr
WBM
Dual Clk FIFO
VESACtrl.
- 100 MHz - 40 MHz
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
SG WBM
SG TOP
SG Reg
UART RX MP Dec
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Rd
SDRAM Arbiter
WBS
MP Enc UART TX
WBMWBM
WBS
INTERCON
req_ln_trigW
BM
WBS
WBM
Z
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBSIN
TERCON
Y
TYPEReg
Type Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
Mem Ctrl Wr
WBM
Dual Clk FIFO
VESACtrl.
- 100 MHz - 40 MHz
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
SG WBM
SG TOP
SG Reg
12
2
3
3
3
4
4
5
4
5
44
UART RX MP Dec
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Rd
SDRAM Arbiter
WBS
MP Enc UART TX
WBMWBM
WBS
INTERCON
req_ln_trigW
BM
WBS
WBM
Z
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBSIN
TERCON
Y
TYPEReg
Type Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
Mem Ctrl Wr
WBM
Dual Clk FIFO
VESACtrl.
- 100 MHz - 40 MHz
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
SG WBM
SG TOP
SG Reg
12
2
3
3
SDRAM Controller
WBS
UART RX MP Dec
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Rd
SDRAM Arbiter
WBS
MP Enc UART TX
WBMWBM
WBS
INTERCON
req_ln_trigW
BM
WBS
WBM
Z
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBSIN
TERCON
Y
TYPEReg
Type Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
Mem Ctrl Wr
WBM
Dual Clk FIFO
VESACtrl.
- 100 MHz - 40 MHz
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
SG WBM
SG TOP
SG Reg
4
4
4
SDRAM Controller
WBS
UART RX MP Dec
SDRAM Controller
WBS
WBM – Wishbone MasterWBS – Wishbone Slave
Mem Ctrl Rd
SDRAM Arbiter
WBS
MP Enc UART TX
WBMWBM
WBS
INTERCON
req_ln_trigW
BM
WBS
WBM
Z
CheckSum CheckSum
RX Path TX Path
Display Controller
MemoryManagement
WBSIN
TERCON
Y
TYPEReg
Type Reg
DBG ADDRReg
INTERCONX
Rd Burst Len
Mem Ctrl Wr
WBM
Dual Clk FIFO
VESACtrl.
- 100 MHz - 40 MHz
IS42S16400 SDRAM
DBG Command
Reg Addr
TYPE Reg
- 133 MHz - 100 MHz
System Clock: 100MHz
SG WBM
SG TOP
SG Reg
5
5
5
6
6
SDRAM Controller
WBS
WBS
WBSWBS
WishboneINTERCON
WBM
RX Path
WBM
TX Path
WBM
WBS
VESACtrl
SG TOP
DisplayController
DC FIFO
100MHz40MHz
SG WBM
MemoryManagement
TY
Ad
Frame 2(640x480)(desired)
Frame 1(800x600)
HOSTVGA
DE2 Board
Frame 2(800x600)(displayed)
VGA
Sending only changes
TX Path
MemoryManagement
RX Path
SDRAM Controller
WBSW
BS
WBMWBM
WBS
WBS
DisplayController
WBS
VGA DisplayIS42S16400
SDRAM
WBM
WBM
UART
UART
VESA
WishboneINTERCON