Performed by:DIAB MONA 036124170 HADAD BENJEMIN 037664158 Instructor: MICHAEL ITZKOVITS

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

דו”ח סיכום פרויקט Subject:

D/A

סמסטר חורף תשס"ב1

AbstractThe DAC which was produced during the project allows the user to convert

digital signals to analog ones in frequencies up to 62.5MHz and up to 14 input signals . It gets differential or single ended clock which has to be

adapted to the input signals to ensure hold and setup time . Converting is done by using the chip produced by ANALOG DEVICES – AD9772A .after

being converted , a net of capacitors , resistors and magnetics produce an analog signal that can be transfered either single ended or differentialy to

net card.Jumpers are in the card to allow certain ways of converting ( like high/low

pass and on).

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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System descriptionHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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S W 13

1

23

5

R9

R

+ 22uFCA P P OL

DCOM

0.01uFC

5V

1uFC

8

R18R

6

50ohm

R

15

S W 9

S W _S L_S P DT

123

DCOM

+ 22uFCA P P OL

0.01uFC

50ohmR

11

R4

R

C4C

L2

INDUCTOR

5V

19,20

SHIELDED LINE

U26

A D9772A _FP

3456789

10111213141516

25

2122

31

32

33

34

4546

4748

35

3839

40

2930

171826

2728

36

4342

DB 13DB 12DB 11DB 10DB 9DB 8DB 7DB 6DB 5DB 4DB 3DB 2DB 1DB 0

P LLLOCK

DV DDDV DD

CLK COM

CLK V DD

P LLCOM

P LLV DD

AV DDAV DD

DV DDDV DD

LP F

RE FLORE FIO

FS A DJ

CLK +CLK -

MOD0MOD1RS T

DIV 1DIV 0

S LE E P

IOUTAIOUTB

1K ohmR

RN1

RE S IS TOR DIP 8

12345678 9

10111213141516

41,44

CLOCK

0.1uFC

3.3V

0.01uFC

10

R3

R

U32

LT1085_T

2

1

3V OUT

A DJ

V IN

1.91K ohm

R

1K ohmR

3.3V

U30

LT1085_T

2

1

3V OUT

A DJ

V IN

0.1uF

C

50ohmR7

14

S W 6S W _S L_S P DT

1

23

R16

R

S W 8

S W _S L_S P DT

123

1

1

23

0.01uFC

41,44

+ 22uFCA P P OL

input data

+ 22uFCA P P OL

IA

50ohmR

8

2

4

0.1uFC

5V

S W 12S W _S L_S P DT

1 2 3

0.1uFC + 22uF

CA P P OL

0.1uFC

1uFC

3.3V

0.01uFC

50ohmR

50ohmR1,2

0.001uFC

0.01uFC

R10R

1uFC

S W 11S W _S L_S P DT

1

23

ACOM

C23

C

16

TG22-3506ND

JP 2

1

23

0.001uFC

AVDD

IB

+ 22uFCA P P OL

ACOM

R17R

C5

C

RJ-45

0.1uFC

CLK+

0.1uFC

CLK V DD

J6

CLOCK

0.1uFC

12

R13

R

50ohmR

0.1uFC

0.1uFC

S W 13

1

23

C3C

50ohm

R

3

L1

INDUCTOR

S W 13S W _S L_S P DT

1 2 3

75ohmR

0.01uFC

0.1uFC

CLK-

S W 3S W _S L_S P DT

1 2 3

T4

TRNS FMR TY-304P

14

36

5 2

50ohmR

T2

TRNS FMR TY-305P

26

37

CLOCK(J3)

U31

LT1085_T

2

1

3V OUT

A DJ

V IN

0.01uFC

R12R

37,41,44

0.1uFC

45, 46

1uFC

JP 1 (DF)

1 2 3

3.3V

50ohmR

ACOM

SpecificationHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

• Hardware

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System Block DiagramHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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FPGA Block DiagramHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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