Performed by: Omer Zimerman Roi Ben-Haim

Instructor: Guy Revach

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

דו”ח סיכום פרויקט )סופי(Subject

Digit recognition hardware implementation

2013/2014סמסטר חורף 1

AbstractHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Neural Network is a Machine Learning System designed for supervised learning using examples. Such network can be used for handwritten digit recognition, and when used in software is in-efficient in both time and resources. This project is the third part of a 3-parts project. Our goal is to implement an efficient hardware solution to the handwritten digit recognition problem.Implementing dedicated HW to this task is part of a new trend in VLSI architecture called heterogeneous computing- design of a system on chip with many accelerators for different tasks, which will achieve better performance/power ratio, each for its purposed task.

System descriptionHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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The system comprises of ML-605 evaluation board, including Xilinx’s Virtex 6 FPGA, connected to a PC via UART interface.A matlab GUI was created, enabling the user to easily send an input image )which is a single digit in the range 0-9, of size 29x29 pixels( to the FPGA via the UART i/f. The recognition process than takes place on dedicated circuitry in the FPGA. After the recognition process is finished, the results are sent back to the PC )via UART(, where they are presented to the user in a clear form through the matlab application.

SpecificationHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

• HardwareVirtexML-605 evaluation board, including Virtex 6 FPGA

• Software Matlab GUI for interacting with the FPGA using UART I/F

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System Block DiagramHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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PC

Matlabapplication

ML-605 board

Virtex 6FPGA

UART i/f

FPGA Block DiagramHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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