pci express 4.0 electrical...

PCI Express® 4.0 Electrical Previews

Rick Eads

Keysight Technologies, EWG Member

PCIe Technology Seminar 2

Disclaimer

The information in this presentation refers to specifications

still in the development process. This presentation reflects

the current thinking of various PCI-SIG® workgroups, but

all material is subject to change before the specifications

are released.

Copyright © 2014, PCI-SIG, All Rights Reserved

PCIe Technology Seminar

Overview

PCIe® 4.0 motivations and assumptions

Separate Reference Clocks with Independent SSC (SRIS)

Transmitter

Reference Clock

Receiver

Channel and CEM connector

3Copyright © 2014, PCI-SIG, All Rights Reserved


PCIe 4.0 Motivations and Assumptions

We continue to see a requirement to increase PCIe bandwidth

Networking, Storage, High Performance Computing

Motivations for PCIe 2.x->3.0 apply equally for 3.0->4.0

Eco-system impact of a new generation drives requirement for ≥2x increase in delivered bandwidth

Desirable to extend PCIe 3.0 infrastructure and PHY architecture for another generation

Moving to a new infrastructure such as electrical or optical waveguides likely breaks backwards compatibility

Highly desirable to preserve current usage models

With incremental improvements 3.0 PHY architecture is capable of higher data rates



PCIe 4.0 Overview

Key attributes of PCIe 4.0 16 GT/s, using scrambling, same as 8GT/s

Maintains backward compatibility with installed base of PCIe devices

Limited channel reach: approx. 12” one connector

Longer channels require retimers or lower loss channels

New features Uniform spec methodology applied across all data rates (as possible)

Support for independent Refclk clocking mode with SSC (SRIS)

Integration of Retimer ECN

This presentation focuses on 0.3 spec changes vs. the 3.0 spec and on items under discussion for potential changes in the 0.5 specification Transmitter

Reference Clock

Retimer

Receiver

Channel

Copyright © 2014, PCI-SIG, All Rights Reserved 5


Separate Reference Clocks with Independent SSC (SRIS)



Inexpensive Cabling = Independent Clock + Spread Spectrum

Challenge: PCIe spec did not support independent clock with spread spectrum

SATA cable does not include clock and is ~ $0.50

PCIe cables include reference clock, would increase cost > $1 for equivalent cable

PCIe Base Spec 3.0 ECN approved

1) Requires use of larger elasticity buffer

2) Requires more frequent insertion of SKIP ordered set

3) Requires receiver changes (CDR). Does not change transmitter or reference clock requirements.

4) Second ECN updates Model CDRs

Change will create a number of new form factor opportunities for PCIe

SATA Express: Connector for PCIe SSD compatible with SATA

Lower cost external cabled PCIe

Example of

Possible

PCIe x2 Cable

Introduce New Terms for Separate Refclk Modes of Operation

5600ppm (New - SRIS) and 600ppm (Existing - SRNS)



20 dB/dec


Model CDR Must Reject SSC

Not Enough SSC Rejection


4.0 Rev 0.3 SRIS/IR Model CDRs (First 3.x ECN CDR)

Kept 40 dB/Dec, critically damped model CDRs for 2.5/5 GT/s consistency

There were concerns about TX and Ref Clock test

9

ωn = ω3dB = 2π * 2.09 MHz for 8 GT/sωn = ω3dB = 2π * 2.43 MHz for 16 GT/sζ = 0.707

8 GT/s

16 GT/s



8GT/s Jitter Tolerance vs. CDR Model

Frequency (Hz)


Gain


New SRIS Model CDRs

11

H(s

) in

dB


Frequency (Hz)


New Model CDR Xfer Functions

The inverse of H(s) is lower than the SRIS JTOL spec

for PCIe 3.0 and PCIe 4.0

Differentiable at all points

Parameters:

8GT/s:

16GT/s:



Transmitter



Transmitter Specification

Preset definition Retain P0-P10 with same definition as PCIe 3.0 at 8GT/s

Package loss (ps21TX) Informative for root complex devices, normative for AIC devices

Architecture Specific Post Processing Embedded vs. non-embedded, Common vs. Independent Refclk

architectures

Jitter parameters Applied uniformly for all four data rates

Number of normative parameters reduced

Informative parameters added

Return Loss extended up to 8GHz Same limits as at 4.0 GHz

T-coils likely required to meet limits



Tx/Rx RL Parameters

Freq (GHz)

50

MH

z

1.2

5 G

Hz

2.5

GH

z

4.0

GH

z

8.0

GH

z

A B C D

A: 2.5, 5.0, 8.0 and 16 GT/s

B: 5.0, 8.0 and 16 GT/s

C: 8.0 and 16.0 GT/s

D: 16 GT/s only

Differential Return Loss Mask

Freq (GHz)

50

MH

z

1.2

5 G

Hz

2.5

GH

z

4.0

GH

z

8.0

GH

z

A B C D

A: 2.5, 5.0, 8.0 and 16 GT/s

B: 5.0, 8.0 and 16 GT/s

C: 8.0 and 16.0 GT/s

D: 16 GT/s only

Common Mode Return Loss Mask


Retu

rn L

oss (

dB

)

Retu

rn L

oss (

dB

)

Effective pad capacitance around 400 pf


CEM Spec – Tx Path

TXT

X

RX

RX

PCE

Conne

ctor

AC Coupling

Caps

System Board Add-in Card

System Board Tx

Add-in Card TxComponent

CEM Spec Defines Tx Requirements for Chip + Interconnect

No Separate Tx Chip Or Interconnect Only Requirements.



Summary of Base vs. CEM Differences for Tx Testing

CEM Tx Testing is at the end of the CEM reference channel

Eye can already be closed at CEM connector with long channel motherboards

Waveform-based test with reference equalizer application in post-processing was chosen as the only option to asses overall Tx interoperability of channel plus silicon

CEM Tx test is an eye test @ BER ≤10-12 after applying the reference equalizer

No jitter decomposition beyond Rj/Dj due to end of channel reference point

CEM Tx eye test only required to pass with “best” preset



Summary of Base vs. CEM Differences for Tx Testing

Motherboard Tx test is done with real motherboard clock (not a clean/lab reference clock)

Do not want to add cost/complexity and require a motherboard to provide method for external clock source

Want a method that can test real, off-the-shelf motherboards

Motherboard Tx test is done by sampling data lane under test and 100 MHz reference clock simultaneously (dual port methodology)

Explore consistency between Base (4.0) and CEM (4.0)

Specified/Recommended measurement/calibration method for eye after reference equalizer

Study possible test/reference channel commonality



Reference Clock



Refclk Specifications

Architecture independent parameters

Architecture dependent parameters

Common Clock (CC) and Independent Reference Clock (IR) filter functions

IR with SSC (SRIS) defined in 3.0 ECN and 4.0 specification

Explicit listing of all combinations of PLL and CDR limits that need to be evaluated

Normative limits for CC

Informative limits for IR (may be removed)

A PHY may support one or more modes



Architecture Independent Parameters

Note that TSSC_MAX_PHASE_SKEW is no longer defined

There is now an explicit freq vs. amplitude mask for SSC profile phase jitter


Symbol Description Limits Units Notes

FREFCLK Refclk Frequency 99.97 (min), 100.03 (max) MHz

FSSCSSC frequency range

30 (min), 33 (max) KHz

TSSC-FREQ-

DEVIATION

SSC deviation -0.5 (min), 0.0 (max) %

TTRANSPORT-DELAYTx-Rx transport delay

12 (max) Nsec 1

TSSC-MAX-FREQ-

SLEW

Max SSC df/dt 1250 ppm/usec 2


Low Frequency Reference Clock Jitter Limits (Mask)


Frequency (Hz)

Jitte

r (p

s pp

)

25000 ps

1000 ps

25 ps

30-33 KHz

100 KHz

500 KHz


Refclk Topologies

CDR

Rx PLL

Tx Latch channel

Ref clk

Jitter at Rx latch

Transfer Function:

T1T2T = |T1 – T2|

RxEQ Rx Latch

Tx PLL

H3(s) =

H2(s) =H1(s) =

[H1(s)e-sT = H2(s)]H3(s)

X(s)[H1(s)e-sT = H2(s)]H3(s)

X(s)[H2(s)e-sT = H1(s)]H3(s)

Compute both and use

larger of the two

Data In Data Out

channelRx

latch

CDR

Tx

latch

Tx

PLL

Ref clk

RxEq

Transfer function: H(s) = H1(s) * H3(s)

Jitter at Rx latch: J(s) = X(s) * H1(s) * H3(s)Refclk jitter = X(s)

Common

Refclk

Data

Clocked



IR Reference Clock Test (0.3)

24

Rx latch

CDR

Rx

PLL

Tx latch

Tx

PLL

channel

Ref clk #1

RxEq

Ref clk #2

Refclk1 jitter = X1(s)

Refclk2 jitter = X2(s)

Transfer Function: H(s) = [H1(s) + H2(s)] * H3(s)

Jitter at Rx latch: J(s)= [X1(s)H1(s) + X2(s)H2(s)] * H3(s)

Incorrect for Clock Test – Options to fix

X1(s)H1(s)*H3(s) < .7 ps (.5 ps in ECN)

8 GT/s (same as SRIS ECN) and 16GT/s

Define reference worst case H2(s)

Remove for IR/SRIS mode altogether



SRIS/IR Reference Clock Test

25

Currently informative in 4.0 Rev 0.3

Pessimistic – assumes worst case specification compliant model PLL transfer function

Difficult to meet for current discrete clock chips – even with improved model CDR

Should 100 MHz frequency be required/implied for a SRIS/IR only implementation?

Reference clock test not specified by other standards with similar PHY architectures

USB 3.0, 3.1, SATA

Current direction to remove altogether for SRIS/IR Mode

Allow maximum implementation PLL/Transmitter trade-off



Receiver



Receiver Specification

Stressed eye methodology applied to all data rates Stressed jitter and voltage as a single test

Calibration channel defined by data rate dependent mask

Tentative direction to make variable at 16GT/s

Minimize Rj/Sj/DM variation across different set-ups

Separate Root Complex and AIC behav pkg models

Behavioral Rx equalization data rate dependent 2.5 and 5.0G: none

8.0 and 16.0G: CTLE and DFE (8G: 1 tap, 16G, 2 taps)



Calibrating Stressed Eye: Rev 0.3


8 GT/s PRBS Generator

Combiner Test EquipmentCalibration ChannelReplica Channel

Fixed TX EQ

TP1 TP2

Post Processing Scripts:Rx pkg modelBehaviorial CTLE/DFEBehavioral CDR

TP2P

Rj Source

Sj Source

Diff Interfer

ence

CM Interfer

ence

EW Adjust EH Adjust

25 mV / .3 UI at E-12 BER

28


Calibrating Stressed Eye: Rev 0.5 Direction


16 GT/s PRBS Generator

Combiner Test EquipmentReplica Channel

CEM Connector

Fixed TX EQ

TP1 TP2

Post Processing Scripts:Rx pkg modelBehaviorial CTLE/DFEBehavioral CDR

TP2P

Rj Source

Sj Source

Diff Interfer

ence

CM Interfer

ence

Calibration ChannelEH or EW Adjust

Small EW Adjust

Small EH Adjust

25 mV / .3 UI at E-12 BER


Channel and Connector



PCIe Connector/Card Enablers

Mitigate conductor geometry that impairs

performance in the PCIe connector at 16GT/s

Any changes must preserve full compatibility among

combinations of Gen 25, 5, 8, 16GT/s connectors and

Add-in Card (AIC)

Keep the standard thru-hole pinfield, for thru hole

parts

For surface mount, use a common footprint

Plan to build and characterize a test board to validate

and correlate models for the proposed performance

enablers



1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

2.00 1.00

Ground traces are 10 mils wide after finger

Ground vias10 mil Drill (0.254mm)20 mil Pad

7.85

4.40

Connector body 2.2mmabove point of contact,

7.85 mm above board edge

2.25

5.60

3.91

Test Layout 0: Baseline

The trace between the via and ground finger is not addressed in the CEM spec

The length, width, and shape of the ground trace has been implementation specific

The ground traces, above the ground finger, may be straight, like here or hockey-stick, etc.

For this baseline test, use these common PCIe 3.0 edge finger dimensions 2mm long, 0.508mm (20 mil) wide ground

trace, as shown Sin

gle

Sin

gle

Sin

gle

Do

ub

le

Do

ub

le

Ground traces areunconstrained in spec



PCIe 4.0 Connector ExperimentsOn the Add-in Card PCB:

0. Baseline Typical 8GT/s

1. Adjacent ground vias

Raises resonant frequency

2. Join the ground edge fingers

Reduces crosstalk and raises resonant freq

3. Narrow the ground fingers

Improves overall insertion loss

Ground finger resistive termination

4. Ground finger resistive termination Suppresses all resonance

5. Place floating subsurface resonant structures beneath ground fingers

Suppresses resonant insertion loss/crosstalk spikes

Baseboard & Connector changes:

1. Surface mount connector

2. Thru Hole with stub

3. Thru Hole with no stub

4. Thru Hole with via stub mitigation

Reduces baseboard PCB via resonance



Combined Experiments - Simulation

Tx0: 2x Single Grounds

Tx1: 1x Double Ground

1x Single Ground

Tx2: 2x Double Grounds

Dashed: Baseline

Solid: Improved

Improved Lane 0↔1

Improved Lane 1↔2

Improved Lane 0↔2

Baseline 1↔2


Differential Insertion Loss Differential FEXT/NEXT


Combined Experiments - Simulation

Tx0: 2x Single Grounds

Tx1: 1x Double Ground

1x Single Ground

Tx2: 2x Double Grounds

Dashed: Baseline

Solid: Improved

Improved Lane 0↔1

Improved Lane 1↔2

Improved Lane 0↔2

Baseline 1↔2


Differential Insertion Loss Differential FEXT/NEXT

8GHz

Discontinuities


Channel Simulation

Aggressor

Center

Alignment

Step response

victim and

aggressors

P0/P1

Voltage step

statistical

convolution

Time

statistical

convolution

Locate and

measure

eye

Random data

TTX-CH-UPW-RJ

TTX-CH-UPW-DJ

TTX-CH-URJ

TTX-CH-UDJDD

TxEQ

PDA

Equalizer

Optimization

and

Aggressor

Center

Alignment

Step response

victim and

aggressors

EQ search

space and

FoM

Apply

CTLE

Voltage

step

statistical

convolution

Time

statistical

convolution

Locate

and

measure

eye

Random data

TTX-CH-UPW-RJ

TTX-CH-UPW-DJ

TTX-CH-URJ

TTX-CH-UDJDD

ADC

DFE

TxEQ

2.5G, 5.0G

8.0G, 16G



Target max length PCIe 3.0 (8 Gb/s) server channel is ~20” with 1 or 2 connectors

Pathfinding for 16GT/s shows ~12” with 1 connector

Even with reduced channel length mitigation is required

Improvements to the CEM connector/launch

Clean up via transitions

Minimize crosstalk

Center channel impedance ~85Ω

Retimer required for longer or 2 connector topologies

Channel Topologies



The CEM form factor is the most important usage model for PCI Express

Can be extended by another generation with improvements to CEM connector launch

Current CEM channels are electrically very complex beyond 8GT/s

Discontinuities and crosstalk from packages, sockets, vias, etch, coupling capacitors, CEM connector

Non-monotonic frequency domain behavior yields unpredictable data rate scaling

To extend current infrastructure requires enabling SIG membership to design and build ‘cleaner’ channels

Tuning via launches, minimizing layer transitions, careful layer choices

For longer reach channels, back-drilling, lower loss materials and repeaters will be required

Channel Recommendations



Thank you for attending the

PCIe Technology Seminar.

For more information please go to www.pcisig.com


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