pc card standard 8.0 volume 8 pc card host system specification

8/2/2019 PC Card Standard 8.0 Volume 8 PC Card Host System Specification

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PC CARD STANDARD

Volume 8

PC Card Host System Specification


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REVISION H ISTORYDate PC Card Host System

Specification VersionPC Card StandardRelease

Revisions

03/97 6.0 6.0 Release Initial version

Added PC Card Host Thermal Ratings

04/98 6.1 6.1 Update PCI Bus Power Management for CardBus Bridges

PCI-to-CardBus Bridge Register Description

02/99 7.0 7.0 Release Corrections to PCI Bus Power Management for CardBusBridges

03/00 7.1 7.1 Update Modified Peak, Static, and Average Current Definitions

Redefined Peak, Static, and Average Ipp Current Values

11/00 7.2 7.2 Update Added Standardized Zoomed Video Register Model

Added PC Card Socket Physical Specification

04/01 8.0 8.0 Release Added VCORE Supplemental Voltage Capability

Added 1.8 V option for VCORE

Changed to PC Card Standard Volume Number 8(was Volume Number 11)

2001 PCMCIA/ JEITA

All rights reserved.

No p art of this publication may be reprodu ced, stored in a retrieval system, or transmitted, in any form or by any m eans,

mechanical, electronic, photocopying, recording or otherwise, without prior w ritten permission of PCMCIA and JEITA.

Published in the Un ited States of America.


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PC CARD HOST SYSTEM SPECIFICATION

2001 PCMCIA/JEITA iii

CONTENTS

1. In trod uction ___________________________________________ 1

1.1 Pu rp ose ...........................................................................................................................................1

1.2 Related Documents .......................................................................................................................1

2. System Therm al and Power _____________________________ 3

2.1 Host System Thermal Measurem ent ..........................................................................................3

2.1.1 Procedu re ............................................................................................................................................................ 4

2.2 Host System Cap abilities and th e Host System Da ta Table ....................................................5

2.2.1 Data Record Hea der ........................................................................................................................................... 6

2.2.2 Base Add ress/ Contro ller ID of the Contr ollers ............................................................................................. 7

2.2.3 Thermal Descript ion .......................................................................................................................................... 8

2.2.3.1 Thermal Ratings .....................................................................................................................................8

2.2.3.2 Ad ap ter/ Sockets With in This Envir onm ent ....................................................................................... 8

2.2.4 Vcc an d Vpp Cap abilities .................................................................................................................................. 9

2.2.4.1 Pow er Sources Descript ions ................................................................................................................ 10

2.2.4.1.1 Voltage / Cur ren t Descriptions .................................................................................................. 11

2.2.4.1.2 Voltage Connection Op tions Definit ion .................................................................................... 11

2.2.4.1.3 Voltage Descrip tion ...................................................................................................................... 11

2.2.4.1.4 Curr ent Descrip tion ...................................................................................................................... 12

2.2.4.1.5 User (s) of This Pow er Sou rce (As Required ) ............................................................................ 12

2.2.4.1.6 Secondary Pow er Source Cou nt ................................................................................................. 13

2.2.4.1.7 Peak , Aver age and Static Cur ren t Defin ition ............................................................................ 13

2.2.5 Host System Cap abilities Da ta Stru ctur e ...................................................................................................... 14

3. PCI Bus Power Managemen t Interface Specification for PCI-to-Card Bus Bridges ___________________________________ 17

3.1 Introduction ..................................................................................................................................17

3.1.1 Goals of this Specification ...............................................................................................................................17

3.1.2 Target Audience ...............................................................................................................................................18

3.1.3 Over view / Scope ..............................................................................................................................................18

3.1.4 Conventions Used in Th is Docu ment ............................................................................................................ 19

3.2 PCI and Card Bus Power Managem ent Over view ..................................................................20

3.2.1 PCI and CardBus Pow er Mana gem ent States .............................................................................................. 20

3.2.1.1 PCI an d CardBus Fu nction Pow er States .......................................................................................... 20

3.2.1.2 PCI and CardBus Bus Po wer States ................................................................................................... 20

3.2.1.3 Device-Class Specifications ................................................................................................................. 20

3.2.1.4 Bus Sup por t for PCI and Card Bus Fu nction Pow er Man agem ent ................................................ 21

3.3 PCI-to-Card Bus Brid ge Power Management Interface..........................................................22

3.3.1 Cap abilities List Data Structur e...................................................................................................................... 23


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3.3.1.1 Cap abilities List Cap _Ptr Location .................................................................................................... 25

3.3.2 Pow er Man agement Register Block Defin ition ............................................................................................ 26

3.3.2.1 Cap ability Iden tifier - Cap _ID (Offset = 0) ....................................................................................... 26

3.3.2.2 Next Item Poin ter - N ext_Item_Ptr (Offset = 1)................................................................................ 27

3.3.2.3 Pow er Man agement Cap abilities - PMC (Offset = 2) ...................................................................... 27

3.3.2.4 Pow er Mana gemen t Contro l/ Status - PMCSR (Offset = 4)............................................................ 29

3.3.2.5 PMCSR PCI-to-Card Bus Brid ge Supp ort Extensions - PMCSR_BSE (Offset=6).......................... 30

3.3.2.6 Data (Offset = 7) ................................................................................................................................... 31

3.4 PCI/ Card Bus Bus Pow er States ................................................................................................33

3.4.1 PCI/ CardBusB0 State - Fully On .................................................................................................................. 33

3.4.2 PCI/ CardBusB1 State ..................................................................................................................................... 34

3.4.3 PCI/ CardBusB2 State ..................................................................................................................................... 34

3.4.4 PCI/ CardBusB3 State - Off ............................................................................................................................ 34

3.4.5 PCI Bus Pow er State Tran sition s.................................................................................................................... 35

3.4.6 PCI Clocking Consid era tions ......................................................................................................................... 36

3.4.7 Control/ Status of PCI and Card Bus Bus Pow er Man agem ent States....................................................... 363.4.7.1 Contro l of Second ary Bus Pow er Source and Clock ........................................................................ 36

3.5 PCI-to-CardBus Bridge Power Managem ent States ...............................................................37

3.5.1 PCI-to-CardBus BridgeD0 State .................................................................................................................... 38




3.5.4.1 Software AccessibleD3 (D3hot) ........................................................................................................... 39

3.5.4.2 Power Off (D3cold)................................................................................................................................. 40

3.5.5 PCI-to-Card Bus Brid ge Power State Trans itions ......................................................................................... 40

3.5.6 PCI-to-Card Bus Brid ge Pow er Man agem ent Policies ................................................................................. 45

3.5.6.1 State Tran sition Recovery Time Requir ements ................................................................................ 49

3.6 PCI-to-Car dBus Brid ges and Pow er Management .................................................................50

3.6.1 PCI-to-Card Bus Brid ge .................................................................................................................................... 55

3.7 Pow er Managem ent Even ts .......................................................................................................58

3.7.1 Pow er Management Event (PME#) Rout ing ................................................................................................ 60

3.7.2 Auxiliary Power forD3cold Pow er Man agement Event s ............................................................................. 61

3.8 Software Support for PCI Power Management ......................................................................61

3.8.1 Identify ing PCI and Card Bus Fun ction Capab ilities ................................................................................... 62

3.8.2 Placing PCI and Card Bus Functions in a Low Pow er State ....................................................................... 62

3.8.2.1 Buses ...................................................................................................................................................... 623.8.2.2 D3 State .................................................................................................................................................. 62

3.8.3 Restor ing PCI Fun ctions From a Low Pow er State...................................................................................... 63

3.8.3.1 Dx States and th e DSI Bit..................................................................................................................... 63

3.8.4 Wake Events ..................................................................................................................................................... 63

3.8.4.1 Wake Event Sup port ............................................................................................................................ 63

3.8.4.2 TheD0 Init ialized State From a Wake Event ................................................................................ 63

3.8.4.3 Device Class Specification for PCI-to-CardBus Brid ges.................................................................. 64


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3.8.4.4 PME Context for PCI-to-Card Bus Brid ges ........................................................................................ 66

3.8.5 Get Cap abilities ................................................................................................................................................ 67

3.8.6 Set Pow er State ................................................................................................................................................. 67

3.8.7 Get Pow er Status ..............................................................................................................................................67

3.8.8 System BIOS Initia lization...............................................................................................................................67

3.9 Other Con sid erations ..................................................................................................................68

4. PCI-to-Card Bus Bridge Register Descrip tion _____________ 69

4.1 Scope..............................................................................................................................................69

4.2 Overview ......................................................................................................................................69

4.2.1 Assu mpt ions ..................................................................................................................................................... 69

4.3 Funct ional Descrip tion ...............................................................................................................69

4.4 Bridge Funct ions..........................................................................................................................70

4.4.1 Data Path s ......................................................................................................................................................... 70

4.4.1.1 Buffer Con trol ....................................................................................................................................... 70

4.4.1.2 Parity ...................................................................................................................................................... 71

4.4.1.3 Locks ...................................................................................................................................................... 71

4.4.1.4 Retry ....................................................................................................................................................... 71

4.4.2 Mem ory Ad dress Map ping ............................................................................................................................ 71

4.4.3 Brid ge Arbitra tion ............................................................................................................................................72

4.4.3.1 Scenarios ................................................................................................................................................ 72

4.4.3.1.1 Write ............................................................................................................................................... 72

4.4.3.1.2 Read ................................................................................................................................................ 73

4.4.4 Interru pts ...........................................................................................................................................................73

4.4.5 Reset ................................................................................................................................................................... 74

4.4.6 ISA Mode........................................................................................................................................................... 74

4.4.7 Support for VGA d evices at ISA add resses .................................................................................................. 75

4.5 Con figu ra tion ...............................................................................................................................75

4.5.1 Brid ge Configur ation Register s ...................................................................................................................... 76

4.5.2 PCI-PC Card Brid ge Configu ra tion Registers .............................................................................................. 77

4.5.2.1 Vend or ID (Offset = 00H)..................................................................................................................... 77

4.5.2.2 Device ID (Offset = 02H) ...................................................................................................................... 77

4.5.2.3 Comman d Register (Offset = 04H)...................................................................................................... 77

4.5.2.4 Status Register (Offset = 06H).............................................................................................................. 77

4.5.2.5 Revision ID (Offset = 08H) ................................................................................................................... 77

4.5.2.6 Class Code (Offset = 09H).................................................................................................................... 77

4.5.2.7 Cache Line Size (Offset = 0CH) ........................................................................................................... 78

4.5.2.8 Latency Timer (Offset = 0DH) ............................................................................................................. 78

4.5.2.9 Head er Type (Offset = 0EH) ................................................................................................................ 78

4.5.2.10 BIST (Offset = 0FH) ............................................................................................................................... 78

4.5.2.11 PC Card Socket Status and Control Registers Base Add ress (Offset = 10H)................................. 78

4.5.2.12 Cap _Ptr (Capa bilities Pointer ) (Offset = 14H) ................................................................................... 78


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4.5.2.13 Reserved (Offset = 15H) ....................................................................................................................... 79

4.5.2.14 Second ary Status (Offset = 16H) ......................................................................................................... 79

4.5.2.15 PCI Bus N um ber (Offset = 18H).......................................................................................................... 79

4.5.2.16 Card Bus Bus Nu mber (Offset = 19H)................................................................................................. 79

4.5.2.17 Subord inate Bus Nu mber (Offset = 1AH).......................................................................................... 79

4.5.2.18 Card Bus Laten cy Timer (Offset = 1BH) ............................................................................................. 79

4.5.2.19 Memo ry Base # 0 (Offset = 1CH) ......................................................................................................... 80

4.5.2.20 Memo ry Limit # 0 (Offset = 20H) ........................................................................................................ 80

4.5.2.21 Memo ry Base # 1 (Offset = 24H).......................................................................................................... 80

4.5.2.22 Memo ry Limit # 1 (Offset = 28H) ........................................................................................................ 80

4.5.2.23 I/ O Base #0 (Lower 16 Bits) (Offset = 2CH)...................................................................................... 81

4.5.2.24 I/ O Base #0 (Upp er 16 Bits) (Offset = 2EH) ...................................................................................... 81

4.5.2.25 I/ O Limit # 0 (Lower 16 Bits) (Offset = 30H) ..................................................................................... 81

4.5.2.26 I/ O Limit #0 Up per 16 Bits (Offset = 32H)........................................................................................ 81

4.5.2.27 I/ O Base #1 (Lower 16 Bits) (Offset = 34H)....................................................................................... 82

4.5.2.28 I/ O Base #1 (Upp er 16 Bits) (Offset = 36H)....................................................................................... 82

4.5.2.29 I/ O Limit # 1 (Lower 16 Bits) (Offset = 38H) ..................................................................................... 82

4.5.2.30 I/ O Limit # 1 (Upper 16 Bits) (Offset = 3AH) .................................................................................... 82

4.5.2.31 Interr up t Line (Offset = 3CH).............................................................................................................. 82

4.5.2.32 Interrup t Pin (Offset = 3DH) ............................................................................................................... 82

4.5.2.33 Brid ge Con trol Register (Offset = 3EH) ............................................................................................. 83

4.5.2.34 Subsystem Vendor ID (Offset = 40H)................................................................................................. 84

4.5.2.35 Subsystem ID (Offset = 42H) ............................................................................................................... 84

4.5.2.36 PC Card 16 Bit IF Legacy Mode Base Add ress (Op tional) (Offset = 44H) .................................... 84

4.5.3 Socket Statu s & Contro l Register s .................................................................................................................. 84

4.5.3.1 Event (Offset = 00H) ............................................................................................................................. 86

4.5.3.2 Mask (Offset = 04H

).............................................................................................................................. 874.5.3.3 Present State (Offset = 08H)................................................................................................................. 88

4.5.3.4 Force (Offset = 0CH)............................................................................................................................. 90

4.5.3.5 Control Register (Offset = 10H)........................................................................................................... 92

4.6 Card Bus In ter face ........................................................................................................................93

4.6.1 Arbitr at ion ......................................................................................................................................................... 93

4.6.2 Ad dresses .......................................................................................................................................................... 93

4.6.3 Com ma nd s ........................................................................................................................................................ 93

4.7 Socket Man agem ent ....................................................................................................................93

4.7.1 Insertion ............................................................................................................................................................. 93

4.7.2 Remova l............................................................................................................................................................. 944.7.3 Wakeup ............................................................................................................................................................. 95

5. Socket Physical Specification __________________________ 97

5.1 Scope ..............................................................................................................................................97

5.2 Goal of th is Specification ............................................................................................................97

5.3 Host Socket Guiderail Dim ension s ...........................................................................................97


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FIGURESFigure 2-1: Determ ing System Therm al Rating: Construction of the Host System Thermal Rating

Environment .....................................................................................................................3

Figu re 2-2: Typ ical En vironment.................................................................................................5

Figure 3-1: Op erating System Directed Power Management System Architecture ..........19

Figure 3-2: . Stand ard PCI Con figuration Space H ead er Typ e 2 ..........................................23

Figu re 3-3: Capabilities Lin ked List ..........................................................................................25

Figure 3-4: Power Man agement Register Block ......................................................................26

Figu re 3-5: PCI Bus PM State Transition s ................................................................................35

Figure 3-6: PCI Fun ction Pow er Managem ent State Transitions .........................................41

Figure 3-7: Non-Bridge Card Bus Function Pow er Man agem ent Diagram .........................45

Figure 3-8: PCI Bridge Pow er Managem ent Diagr am ...........................................................51

Figure 3-9: PME# System Routing ............................................................................................60

Figure 3-10: Vcc to VAUX Transitionin g .....................................................................................61

Figure 4-1: Even t Register ..........................................................................................................86

Figure 4-2: Mask Register ...........................................................................................................87

Figure 4-3: Present State Register ..............................................................................................88

Figure 4-4: Force Register ...........................................................................................................90

Figu re 5-1: Host Socket Guide Rail Dim ension s .....................................................................97


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TABLESTable 2-1: Data Record Header ....................................................................................................6

Table 2-2: Base Ad dress/ Con troller ID of th e Controllers ......................................................7

Table 2-3: Therm al Description ...................................................................................................8

Table 2-4: Power Sources Descrip tion s ......................................................................................9

Table 2-5: Recomm end ed Minimum Curren t Per Slot Values1 ............................................13

Table 2-6: H ost System Cap abilites Data Structure ................................................................14

Table 3-1: PCI Statu s Register ....................................................................................................24

Table 3-2: Capabilities Pointer - Cap _Ptr .................................................................................24

Table 3-3: PCI Configuration Space Header Type / Cap _Ptr Mapp ings ............................25

Table 3-4: Capability Identifier - Cap_ID.................................................................................26Table 3-5: Next Item Pointer - Next_Item_Ptr .........................................................................27

Table 3-6: Pow er Managem ent Cap abilities - PMC................................................................28

Table 3-7: Pow er Management Con trol/ Status - PMCSR.....................................................30

Table 3-8: PMCSR Bridge Support Extensions - PMCSR_BSE..............................................31

Table 3-9: Data Register ..............................................................................................................31

Table 3-10: Power Consu mp tion/ Dissipation Reportin g......................................................32

Table 3-11. PCI/ CardBus Bus Power Man agement States ....................................................33

Table 3-12: PCI Bus Power and Clock Control........................................................................37

Table 3-13: State Diagram Summary ........................................................................................42

Table 3-14:D0 Power Managem ent Policies ...........................................................................46



Table 3-17:D3ho t Power Management Policies........................................................................48

Table 3-18:D3cold Power Management Policies.......................................................................49

Table 3-19: PCI-to-Card Bus Brid ge State Tran sition Delays .................................................50

Table 3-20: PCI-to-Card Bus Bridge Power Managem ent Policies........................................52

Table 3-21: PME Context: ExCA Card Status-Chan ge Interrup t Configuration Register, 805H

...........................................................................................................................................56

Table 3-22: PME Context: ExCA Card Status-Change Register , 804h .................................56

Table 3-23: PCI-to-CardBus Brid ge PME Context for Brid ge Devices.................................56

Table 4-1: CardBus Controller Configuration Space ..............................................................76


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Table 4-2: Status & Con trol Register s .......................................................................................85


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2001 PCMCIA/JEITA 1

1. INTRODUCTION

1.1 PurposeThe PC Card Host System Specification intend s to define requiremen ts for any host system containing

a PC Card socket. This curr ently includ es the following app lications:

PC Card Host Thermal Ratings

PCI Bus Pow er Managemen t Interface for PCI-to-Card Bus Bridges

PCI-to-CardBus Bridge Registers

PC Card Socket Physical Specification

1.2 Related DocumentsThe following documents which comprise the PC Card Standard:

PC Card Standard Release 8.0 (April 2001), PCMCIA / JEITA

Volum e 1. Ov erview and Glossary

Volum e 2.Elect rical Speci fi cat ion

Volum e 3. Physical Specification

Volum e 4.Metaform at Specif ica t ion

Volum e 5. Card Services Specificati on

Volum e 6. Socket Services Specification

Volum e 7. PC Card ATA Specification

Volum e 8. PC Card Host Syst ems Specification

Volum e 9. Guidelines

Volume 10.Media S torage Format s Speci fi cat ion

Volume 11.XIP Specif icat ion

PCI Local Bus Specificati on, Revi sion 2.1, Jun e 1, 1995, PCI Special Interest Gr oup

PCI t o PCI Bridge Architecture Specification , Rev ision 1.0, April 5, 1994, PCI Special Inter est Grou p

PCI Mobile Design Guide, Revision 1.0, October 27, 1994, PCI Special Interest Group

PCI Bus Pow er Management Specification, Rev ision 1.0, Mar 18, 1997, PCI Special Interest Gr oup

Adv anced Conf igurat ion and Pow er In terface Specificat ion R evis ion 1.0, Intel Corporation, Microsoft

Corporation and Toshiba

Toward the OnNow Machine: The Evolution of the PC Platform , Microsoft Technology Brief, Ap ril

1996, Microsoft Corporation

Dev ice Pow er Managem ent, Microsoft Techn ology Brief, April 1996, Microsoft Corp orat ion

Dev ice Class Pow er Managem ent Reference Specificat ions , Draft Proposals, 1996, Microsoft

Corporation

OnN ow Design Initiativ e and ACPI, Microsoft Web Page with links to many of the d ocumen ts above,

1996, Microsoft Corporation

OnN ow Pow er Management and t he Win32 Driver Model, 1996, Microsoft Corporation


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PCI Hot-Plug Specification, PCI Special Interest Grou p

ExCA Com pliance Test Procedure and Speci ficat ion


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2. SYSTEM THERMAL AND POWER

This section defines a low cost optional method wh ich can be used in d etermining the host p latform

thermal rating. The pu rpose of determining the thermal rating is to ensure that the heat generated

and dissipated within the body of the PC Card d oes not therma lly exceed the capab ilities of the host

system to remove excessive heat in order to maintain the PC Card at an acceptable temperatur e limit.

The host system method of choice shall be run at the man ufacturers wor st case environm ental up per

limits for the product being rated.

2.1 Host System Thermal MeasurementThe pu rpose of determ ining the host systems thermal rating is to measur e the ability of the host to

remove heat from the PC Card environment an d maintain the PC Card su rface temperature. This

measurement is performed using a thermal transmission d evice of the same size and physical

dimensions of a PC Card with an external power source supplying the energy to raise the

transm ission devices surface temp eratur e.

Host System Under Test

Thermal TD

Thermal Environment = manufacturer's upper limit

Thermal TDExternal Power

Thermal TD

Measuring Device

Source

Temperature

Card LoadSimulator

Note: TD = transmission

Figure 2-1: Determing System Thermal Rating: Construction of the Host System Thermal

Rating Environment

A thermal transmission d evice mu st be used to introduce heat into the host system in order to

determ ine the host systems ability to remove a PC Card s heat energy. A therma l input d evice in the

form factor of a Type II 16-bit (not Card Bus) PC Card shall be used . The thermal inp ut device can be

mad e from a Type II card frame and metal side p anels using ind ustry standard frames and p anel kits.

The therm al input d evice shall be connected to a ll PC Card pins except the VCC, VPP/VCORE and card

detect pins. A Kapton heater element or similar device is used as the heater element for the therma l


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input d evice. An adjustable external power su pp ly is used to d rive the heater and an external

temperature m easuring device is used to monitor the therm al input devices surface temp erature.

Lastly, a d evice mu st be utilized to draw as mu ch power from the h ost system pow er supp ly as what

is being input to the therm al inpu t device (see Figure 2-1). This is a simp le variable load that m ay be

connected to a second slot VCC/VPP/VCORE pins through a du mmy card if available.

2.1.1 Procedure

Power on the h ost system un it and ru n a p rogram, designed to prevent the host platform from

activating any power management features that maintains activity. The host system must be placed

on a therm ally non-cond uctive surface.

Introduce external heat into the PC Card environment via the external power sup ply. Adjust the PC

Card Load Simulator to consume as m uch pow er as that being introdu ced into the thermal inpu t

dev ice. When the tem peratu re of the therm al inpu t device stabilizes at 65C 1C for a sixty minu te

period, the thermal rating of the system h as been reached. The DC p ower read ing is the thermal

rating (voltage X current) w hich is record ed an d r eported in the H ost System Da ta Table (see Section

2.2 Host Syst em Capabilities and the Host Sy stem Dat a Table).


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2.2 Host System Capabilities and the Host System Data Table

Vcc = 5VBulk Supply

Vpp = 12VBulk Supply

Switch

Socket 0

Socket 1

ThermalEnvironment

Adapter

Constraint/restrictionControl/data

R1

R2

R3

R6

R5

R4

Figure 2-2: Typical Environment

In a typical environm ent, pow er sources are limited by the d esigns allotmen t of bulk power su pp ly

current to the PC Card sub-system and the current capability of the switching mechanism turn ing on

VCC an d VPP/VCORE to the PC Card . Restrictions R1 and R2 represen t the ded icated PC Card design

allotment and r estrictions R3 and R4 represent the limitations of the switching circuit. When

distributing p ower resou rces, the controlling software m ust ensu re that neither the switch limit northe resou rce supp ly allocation limits are violated. It is the hosts responsibility to sup ply the d esign

limits to the PC Card controlling softwa re.

A therm al environm ent is limited is imposed also by design. This limit is to ensure th at neither the PC

Card nor the host system is damaged by excessive heat.

The therma l rating indicates the ability of the host system to remove h eat. This rating repr esents the

maximum am ount of heat the unit can remove and maintain the card at a m aximu m surface

temperature of 65C at the manufacturers environmental upper limit. The format of the thermal

rating values is defined u sing the man tissa - exponent - extension (see theMetaform at Specif icat ion).

The power capabilities described within this data structure represent not only what voltages are

available, but also the am oun t of curr ent the host is capable of providing, and w hat, if any, limitations

there m ay be d ue to voltage sw itches, connector contacts, etc.The da ta structure d escribing the h ost capabilities shall be located in the Host System Data Table.


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2.2.1 Data Record Header

Table 2-1: Data Record Header

Host System PCMCIA Capabilities

Record ID

Ext Thermal and Power Record Number (6::0)

Version

major minor

8-Bit Checksum

Checksum

Byte count of total data structure (including ID)

Byte count (LSB)

Byte count (MSB)

The header begins with a record n umber. Following the record num ber is a record version nu mber

defined as ma jor (0 - 15).minor (1 - 9), followed by an 8-bit checksum wh ich resu lts in a zero

checksum. Comp leting the head er is a 16-bit byte coun t of the entire data record . Version numbers

and comments are as follows:

Version History

Major Minor Comments

1 0 Initial Release

Reserved Reserved Future Release Numbers

The record n um ber is of the bit 7 extension type. Bit 7 of each byte is the extension bit (Ext) wh ich

indicates that an other byte of cond itions follows the p resent byte. Bits 0 - 6 represent ascend ing

ordered record n um ber bits, as required , while bit 7 in each byte ind icates wh ether or not the nextbyte is an extension of the record n um ber. The following byte rep resents record nu mber xxxxxxx, no

extension:

offset n + 0 0 x x x x x x x

wh ile the following tw o bytes represent record nu mber yyyyyyyxxxxxxx:

offset n + 0 1 x x x x x x x

offset n + 1 0 y y y y y y y

The first record would have the format:

offset n + 0 0 0 0 0 0 0 0 1


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2.2.2 Base Address/Controller ID of the Controllers

Table 2-2: Base Address/Controller ID of the Controllers

Base Address/Controller ID of the controllers (as required)

Ext RFU(0) Skts Enum Bus Type (4::3) Controller ID (2::0)

Legacy controller base address 7::0 (LSB) or Device number (4::0)

Legacy controller base address 15::8 (MSB) or Bus number (7::0)

Socket Enumeration

Socket Count

PCI Sockets

Socket number Device number (if required) (4::0)

Bus number (if required) (7::0)

The first entry of the Base Add ress/ Controller ID is used to identify the bus type and the controller

ID. Also indicated in this byte is wheth er or not th e controllers sockets will be enumerated with

location information particular to this imp lementation.

If bit 7 is set, more than one controller is being defined . Bit 6 is reserved for futu re u se (0).

Bits 4::3 specify the type of system bu s and are d efined as follows:

Bits 4::3 Bus Type

0 ISA

1 PCI

2 RFU

3 RFU

Bits 2:0 specify the identification num ber this controller will use w ithin this record and is uniqu e tothis record. There is no conformity between this records ID and the host system softwares ID or any

other records ID for this controller.

While sockets are not requ ired to be enu merated , it is required to sp ecify the num ber of sockets

associated w ith this controller. If sockets are enum erated (such as for a PCI environm ent) then the Skt

Enum bit, bit 5, shall be set. The socket enum eration for each bus ar chitecture m ay be d ifferent and

will be defined wh en the bu s is defined.

The base add ress of the controllers is a physical add ress and is bus dep end ent. If the controller is a

PCI agent, the bus type w ill be 01h and the bridge can be located by the d evice num ber and bus

nu mber u sed to isolate the controller. If the PCI agent sup ports Card Bus cards and legacy cards, the

base addr ess of the legacy controller function is determ ined by r eading bytes 44:47 in the bridge

configur ation space. If the controller is an ISA only d evice, the bytes are used to denote the ISAbeginning ad dress and the bus typ e will be zero. This physical add ress is the mechanism wh ich PC

Card software u ses in correlating the softwares logical controller/ socket num ber with th e controller

ID. Socket enu meration shall begin w ith zero so as to maintain comp liance with th e PCI bridge

mu ltifun ction sp ecification. Three bits of socket ID are used to define u p to eight controllers. This ID

is used to designate controllers within this data structure only and have no correlation with the PC

Card softwares or any other record s socket num ber. Bus typ es 02h and 03h are reserved for futur e

definition.


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8 2001 PCMCIA/JEITA

2.2.3 Thermal Description

Every socket is contained in a therm al environmen t. The therm al environmen t indicates how mu ch

heat can be generated an d still maintain the PC Card surface temperature at 65C. The extension bit

is used to ind icate the presence of an extension byte (in the mantissa/ exponen t byte) or add itional

extensions.

Table 2-3: Thermal Description

Thermal Descriptions

Ext Thermal rating mantissa Thermal rating exponent

Ext Extension

Adapter/sockets within this environment (as required)

Ext Controller ID (6::4) Socket ID (3::0)

2.2.3.1 Thermal Ratings

This value is the therm al rating of the environment. This value represents the m aximum amoun t ofheat w hich the host system can receive from the card and still maintain a card su rface temp eratur e of

65C or below.

2.2.3.2 Adapter/Sockets Within This Environment

Following the environm ents therm al rating is a list of sockets wh ich exist within that therm al

environm ent. Bit 7 is used to extend th e list for as m any entries as is necessary. Bits 6::4 contain the

controller ID as defined in the record base ad dr ess/ controller ID section of the d ata stru cture. Bits 3::0

define a socket of the controller which exist within th is environmen t.


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2001 PCMCIA/JEITA 9

2.2.4 Vcc and Vpp Capabilities

This data structure defines the VCC and VPP/VCORE capabilities of the h ost system controller.

Table 2-4: Power Sources Descriptions

Power Sources Descriptions

Voltage / Current Descriptions

Ext RFU(0) RFU(0) Static I Ave I Peak I Min Max V Nom V

Voltage Connection Options Definition

RFU (0) RFU (0) RFU (0) RFU (0) Vcore Vpp = Vcc Vpp Vcc

Voltage Description

Ext Nominal voltage mantissa Nominal voltage exponent

Ext Nominal voltage extension

...or

...

Ext Minimum voltage mantissa Minimum voltage exponent

Ext Minimum voltage extensionExt Maximum voltage mantissa Maximum voltage exponent

Ext Maximum voltage extension

Current Description

Ext peak current mantissa peak current exponent

Ext Extension

Ext average current mantissa average current exponent

Ext Extension

Ext static current mantissa static current exponent

Ext Extension

User(s) of this power source (as required)



Ext Extension


Ext Extension


Ext Extension

Secondary power source count

Count of power source(s) derived from this primary source

Secondary power sources (as required)





Voltage Description



... or ...


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10 2001 PCMCIA/JEITA

Ext Minimum voltage mantissa Minimum voltage exponent

Ext Minimum voltage extension

Ext Maximum voltage mantissa Maximum voltage exponent


Current Description


Ext Extension


Ext Extension


Ext Extension

Ext multiplier mantissa multiplier exponent

Ext multiplier extension




Ext Extension


Ext Extension


Ext Extension



2.2.4.1 Power Sources Descriptions

Power sources are d ivided into two types: primary, or bu lk supp lies, and secondary. Secondarypow er sources are derived from a p rimary sup ply u sing such circuits as charge pum ps. Secondary

supp lies increase the current required from the p arent, thus this value m ust be ad ded not only to the

secondary power source accumulator, but must also be multiplied by an inefficiency number and

add ed to the current accum ulator of the parent.


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2001 PCMCIA/JEITA 11

2.2.4.1.1 Voltage / Current Descriptions

This byte specifies what typ e of voltage and wh ether or not curren t values will be defined .


Bit Description

Ext This bit is used to indicate that more voltage definitions will follow. If the value is 1, then thedefinition block will be repeated for at least one more voltage definition.

RFU(0) Reserved for future use, set to 0


Static I This bit, if set, indicates that the static current will be specified for the voltage being defined.

Ave I This bit, if set, indicates that the average current will be specified for the voltage being defined.

Peak I This bit, if set, indicates that the peak current will be specified for the voltage being defined.

Min MaxV This bit is used to denote a variable voltage is being defined, and that the maximum and minimumvalues will be defined. Min MaxV and Nom V are mutually exclusive.

NomV This bit, if set, indicates the voltage being defined is not variable, and the nominal value will bedefined. Min MaxV and Nom V are mutually exclusive.

2.2.4.1.2 Voltage Connection Options Definition

This byte specifies wh at type of voltage is being d efined .


Bit Description





Vcore If set (1), the voltage being defined can be connected to the VCORE pins of the socket. If reset (0),the voltage being defined cannot be provided to the VCORE pins.

Vpp1,2 = Vcc If set (1), the voltage being defined can only be connected to the VPP pins of the socket when thevoltage is also being used as VCC. If reset (0), the voltage is available to the VPP pins regardlessof the VCC setting. This bit is only valid when both the VPP and VCC bits are set.

Vpp If set (1), the voltage being defined can be connected to the VPP pins of the socket. If reset (0),the voltage being defined cannot be provided to the VPP pins.

Vcc If set (1), the voltage being defined can be connected to the VCC pins of the socket. . If reset (0),the voltage being defined cannot be provided to the VCC pins.

2.2.4.1.3 Voltage Description

The following bytes define either the nominal voltage value or the minimum and maximum voltages.

For a nomina l voltage as specified by b it 0, Nom V, of the byte Voltage / Curr ent Descriptions, the

following forma t is used:


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The extension bit (Ext) in the m antissa/ exponent byte, if set, ind icates an extension byte follows. If the

extension bit (Ext) in the voltage extension byte is set, ad ditional voltage extensions follow.

A Nom inal voltage mantissa value of 07H (111b) and a Nom inal voltage exponent valu e of 0FH (1111b)

and a Nominal voltage extension value of 07FH (1111111b) and no extension (bit 7 of the Nom inal

voltage extension = 0) ind icates the voltage has a value of infinite imped ance (open) with no cur rent

capability and none need be defined.

A Nom inal voltage mantissa value of 0H (000b) and a Nom inal voltage exponent valu e of 0FH (1111b)

and a Nom inal voltage extension value of 00H (0000000b) and no extension (bit 7 of the N ominal

voltage extension = 0) ind icate the voltage has a va lue of 0 (zero) imp edan ce (ground ) with no curren t

capability and none need be defined.

These values are intend ed to be u sed for specifying Vpp capabilities.

For a variable voltage, as indicated by bit 1, Min Max V, of the byte Voltage / Cur rent Descriptions,

the format to be used is:Ext Minimum voltage mantissa Minimum voltage exponent

Ext Minimum voltage extension

Ext Maximum voltage mantissa Maximum voltage exponent


2.2.4.1.4 Current Description

Following the v oltage definition ar e the curren t definitions as indicated by bits 2 - Peak Current, 3 -

Average Cu rrent and 4 - Static Cur rent of the Voltage / Curr ent Descriptions byte. The format is:

Ext peak current mantissa peak current exponentExt Extension


Ext Extension


Ext Extension

The values specified repr esent the maximu m sou rce amoun t for each category available which is

presented to the voltages user community.

2.2.4.1.5 User(s) of This Power Source (As Required)

The users of the pow er source previously d efined a re listed by controller and socket num ber. See

section 2.2.2 Base Address/Controller ID of the Cont rollersto determine the socket nu mbering and

addr ess schem e. Socket users are defined in terms of the socket num ber and the controller nu mber.

Socket specification includes p eak, average an d static current w hich is the maximu m of each category

wh ich can be p assed th rough to th e socket. When set, the extension bit, bit 7 of the socket ID byte,

indicates that an other u ser socket will be defined following th is definition.


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Ext Extension


Ext Extension


Ext Extension

2.2.4.1.6 Secondary Power Source Count

Second ary power sou rces are specified at the end o f the parent p rimary p ower sou rce specification.

After all user sockets of the p arent have been sp ecified, a Secondary power source countis provided to

indicate wh ether or not any secondary pow er sources are derived from this primary. If the Secondary

power source countis non-zero, then the d ata structu re following is a seconda ry pow er source. The

format of the second ary power sou rce is the same as a primar y except for the add ition of a multiplier.

Any u tilization of the second ary power sou rce must be reflected back to the pa rent p rimary after the

mu ltiplier effect has been app lied.

2.2.4.1.7 Peak, Average and Static Current Definition

See the Ov erview and Glossary for definition of Peak, Average, and Static Curren t.

Table 2-5: Recommended Minimum Current Per Slot Values1

Voltage Current Type Name 3.3V Value 5V Value

VCC Peak ICCP 1000 mA 660 mA

VCC Average ICCA 750 mA 500 mA

VCC Static ICCS 500 mA 330 mA

Voltage Current Type Name 1.8V Value 3.3V Value

VCORE Peak ICOREP 500mA 300mA

VCORE Average ICOREA 375mA 250mA

VCORE Static ICORES 250mA 200mA

Voltage Current Type Name Value for all Vpp Voltages2

VPP Peak IPPP 50mA

VPP Average IPPA 50 mA

VPP Static IPPS 50mA

1. PC Cards requiring more current than the host minimum recommended support values may notbe powered properly in all systems

2. Typical Vpp values are Vcc and 12V.


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2.2.5 Host System Capabilities Data Structure

Table 2-6: Host System Capabilites Data Structure

Host System PCMCIA Capabilities

Record ID

Ext Thermal and Power Record Number (6::0)

Version

major minor

8-Bit Checksum

Checksum

Byte count of total data structure (including ID)

Byte count (LSB)

Byte count (MSB)

Base Address/Controller ID of the controllers (as required)

Ext RFU(0) Skts Enum Bus Type (4::3) Controller ID (2::0)

Legacy controller base address 7::0 (LSB) or Device number (4::0)

Legacy controller base address 15::8 (MSB) or Bus number (7::0)

Socket Enumeration

Socket Count

PCI Sockets

Socket number if required (7::5) Device number (if required) (4::0)

Bus number (if required) (7::0)

Thermal Descriptions

Ext Thermal rating mantissa Thermal rating exponent

Ext Extension

Adapter/sockets within this environment (as required)


Power Sources Descriptions





Voltage Description

Ext Nominal voltage mantissa (bit 0 = 1) Nominal voltage exponent (bit 0 = 1)

Ext Nominal voltage extension (bit 0 = 1)

...or

...

Ext Minimum voltage mantissa (bit 1 = 1) Minimum voltage exponent (bit 1 = 1)

Ext Minimum voltage extension (bit 1 = 1)

Ext Maximum voltage mantissa (bit 1 = 1) Maximum voltage exponent (bit 1 = 1)

Ext Maximum voltage extension (bit 1 = 1)


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Current Description


Ext Extension


Ext Extension


Ext Extension




Ext Extension


Ext Extension


Ext Extension



Secondary power sources (as required)




RFU (0) RFU (0) RFU (0) RFU (0) RFU (0) Vpp1,2 =Vcc

Vpp Vcc

Voltage Description

Ext Nominal voltage mantissa (bit 0 = 1) Nominal voltage exponent (bit 0 = 1)

Ext Nominal voltage extension (bit 0 = 1)

...or

...

Ext Minimum voltage mantissa (bit 1 = 1) Minimum voltage exponent (bit 1 = 1)

Ext Minimum voltage extension (bit 1 = 1)

Ext Maximum voltage mantissa (bit 1 = 1) Maximum voltage exponent (bit 1 = 1)

Ext Maximum voltage extension (bit 1 = 1)

Current Description


Ext Extension


Ext Extension


Ext Extension

Ext multiplier mantissa multiplier exponent

Ext multiplier extension


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Ext Extension


Ext Extension


Ext Extension




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3. PCI BUS POWER MANAGEMENT INTERFACE

SPECIFICATION FO R PCI-TO -CARDBUS

BRIDGES

3.1 IntroductionSince its introd uction in 1993, PCI has become a v ery popu lar bus. It is used in a wid e variety of

computer systems sold today ranging from laptops to large servers. Its bandwidth and efficient

supp ort for multiple masters has allowed it to sustain high p erformance app lications while at the

same time, its low pin coun t and high integration factor has enabled very low cost solutions.

Power Managem ent in the current PC p latform is perform ed by a combination of BIOS and System

Management Mode (SMM) code utilizing hardware unique to each platform. While this strategy has

successfully brought th e PC platform into the m obile environm ent it is beset with p roblems becauseof the fact that there is no standard way to tru ly determine when the system is busy and wh en it is

actually idle. The operating system d oes have this information so it makes sense to give it the

responsibility for pow er managem ent. The reason that this has n ot happ ened u p to now is a lack of

standard s to provide the operating system w ith the required information that wou ld allow it to

control the hardware in a platform independent way. This specification addresses this need.

While the PCI Local Bus Specification is quite comp lete with a solid d efinition of pr otocols, electrical

characteristics and mechanical form factors, no prov ision w as made in the or iginal specification for

supporting power management functionality. This specification addresses this requirement by

defining four d istinct pow er states for the PCI bus and fou r d istinct pow er states for PCI fun ctions as

well as an interface for controlling these pow er states.

3.1.1 Goals of this Specification

The goal of this specification is to establish a standard set of PCI periphera l power man agemen t

hard ware interfaces and beh avioral policies. Once established th is infrastructu re enables an operating

system to intelligently man age the pow er of PCI functions, and bu ses.

Detailed Goals for PCI Power Managem ent Interface:

Enable multiple PCI fun ction power levels

Establish a stand ard for PCI function w akeup events

Establish a standard for rep orting pow er man agement capabilities

Establish a stand ard mechan ism for controlling a PCI fun ction's pow er state

Establish a stand ard mechan ism for controlling a PCI bus's pow er state

Minimal impact to the PCI Local Bus Specification

Backwards compatible with PCI Local Bus Specification, Revision 2.1, and 2.0 compliant

designs

Preserve the designers ability to deliver differentiated prod ucts

Provide a single architecture for all markets from m obile throu gh server


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PCIBUS POWER M ANAGEMENT INTERFACE SPECIFICATION FOR PCI-TO -CARD BUS BRIDGES


Key Attributes of this Specification:

Enhances the PCI Buss Plug and Play capabilities by comprehending power management

Standard ized p ower state definitions

Standar dized register interface in PCI configur ation space

Standard ized w ake events

3.1.2 Target Audience

This documen t is intended to ad dr ess the needs of developers of PCI-to-Card Bus bridges. This

document describes the hard ware requ irements of such devices to allow the pow er mana gement of

those devices in an operating system directed p ower m anagement environment.

Softwa re d evelopers are a lso a targeted aud ience for this specification. Specifically, developers of

operating systems and device drivers need to u nderstand the pow er management interfaces

presented by compliant devices to be able to manage them.

3.1.3 Overview/ScopeIn order to implement a p ower man aged system un der the d irection of the operating system, a large

array of tightly coupled h ardw are, and software ingredients needs to be d efined and integrated. The

following d iagram ou tlines, at a high level, this set of required ar chitectura l building blocks.


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OSPM specifications. Device drivers

specifications. PM policy specifications

Platform ArchitectureIntegration

Specification

I/O BusPower Management

Specifications

USB

IEEE1394

PCI

Device-ClassPower Management

Specifications

Audio

Storage

Graphics

PCI to

CardBus

Bridge

Function

SCOPE ofSpecification

Config Regs Config Regs

Function

Config Regs

Host PCI Bus

CardBus CardBus

Figure 3-1: Operating System Directed Power Management System Architecture

The scope of this specification is sharp ly focused on establishing a stand ard set of interfaces that are

requ ired to pow er manage PCI-to-CardBus Bridges, buses, devices, Card Bus cards and functions.

Devices which can only be implemented on the m otherboard are pow er managed in motherboard

specific ways (such as ACPI), and as such, m ay fall outside the scope of this specification. Docking

bridges, for example fall into the moth erboard dev ices category because the p hysical docking brid ge

component always resides logically on the m otherboard, and is never deployed as an add -in card. As

such Docking brid ges are not covered by this specification.

The PCI Bus Pow er Managemen t Interface Specification for Card Bus d escribes requ irements for

implementing p ower m anagement for PCI-to-CardBus bridge and CardBus card functions which are

capable of being u sed on an add -in card.

3.1.4 Conventions Used in This Document

Several conventions are used in this docum ent to help make it more readable. These are listed below.

Power states are shown in bold italic text such asD0.

Register nam es are shown in bold text as in PMCSR.

Names of bits or fields w ithin registers are in italic text such as PowerState.

Signal nam es are all capitalized and bold like PME# .


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All nu mbers are rep resented in d ecimal un less followed by a small letter.

Hexadecimal nu mbers are represented w ith a following "H" (e.g. DCH).

Binary nu mbers are rep resented with a following "B" (e.g. 10B).

3.2 PCI and CardBus Power Management Overview

3.2.1 PCI and CardBus Power Management States

Power management states are defined as varying, distinct levels of power savings. Power

Management states are denoted by a state num ber. Throughou t this docum ent power m anagement

states for both PCI and Car dBus buses and PCI and Card Bus functions will be defined , specified an d

discussed. Power man agemen t states for PCI buses, by convention, are prefixed w ith a B, and end

in the power management state number (0-3). The higher the number the more aggressive the

intended power savings. Similarly for PCI and CardBus functions the power management state is

prefixed w ith a D, and ends w ith the power management state number (0-3). Intended p owersavings increase with the p ower man agement state number.

3.2.1.1 PCI and CardBus Function Power States

Up to four p ower states are defined for each PCI and Card Bus function in the system. These areD0-

D3 withD0 being the maximum pow ered state, and D3 being the minimum pow ered state.D1 and

D2 pow er man agement states enable intermediate power savings states between the D0 (on) and D3

(off) power management states.

While the concept of these power states is universal for all fun ctions in the system , the mean ing, or

intended functional behavior when transitioned to a given p ower man agement state is depend ent

up on the type (or class) of the function.

3.2.1.2 PCI and CardBus Bus Power States

The pow er managemen t state of a bus can be characterized by certain attributes of the bus at a given

time such as whether or not pow er is sup plied, the speed of the clock, and wh at types of bus activities

are allowed . These states are referred to asB0,B1,B2 an d B3.

This specification defines a m echanism that enables explicit control of a PCI and Card Bus bu ss pow er

and PCI and Card Bus clock (CCLK) as a function the pow er man agemen t state of its originating

dev ice. The mechan ism can be disabled (see 3.3.2.5 PMCSR PCI-to-CardBus Bridge Support

Ext ensions - PMCSR _BSE (Offset =6), an d 3.4.7.1 Control of Secondary Bus Pow er Source and Clock).

3.2.1.3 Device-Class Specifications

The PCI and Card Bus Bus Power Managemen t Interface Specification stand ard izes the power

management hard ware interface for the PCI and Card Bus Bus, and PCI and CardBus comp onents.

How ever PCI and Card Bus fun ctions belonging to different device classes may beh ave d ifferently

wh en opera ting in the same p ower m anagem ent state. This is the notion of Device-Class specific

pow er man agemen t policy. For example, the list of capabilities that an audio subsystem w ould

sup por t in a given power managemen t state would most likely be different than th e list of capabilities

supp orted by a grap hics controller operating in the same pow er management state.


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While Device-Class Power Managem ent Specifications fall outside the scope of this specification, they

are men tioned here to inform the reader of their imp ortant relationship to the interfaces defined in

this document.

Each class of device mu st have its own class specific set of pow er m anagem ent p olicies to define their

intended behavior while in each of the pow er man agement states.

For a fully integrated p ower m anagement system, these class-specific power m anagement p olicies

must also be standardized. Each major device type must have a Device-Class Power Management

Specification that all man ufacturers can use as a gu ide to facilitate the seamless integration of their

pow er managed p rodu cts into a system.

Device-Class Specifications will generally cover the following areas:

Device-class powercharacteristics

Each class of PCI and CardBus function should have a standard definition for eachfunction power management state. This should include target power consumptionlevels, command response latencies, and state-change latencies. Implementationdetails for achieving these levels (such as whether an entire functional block ispowered-off or the clock is stopped) might be important to a particular device class and,if so, should be specified. If any of these characteristics are in conflict with therequirements of the bus specifications, the function may not be able to implement thatstate on that particular bus.

Minimum Device-Class powercapabilities

Each class of PCI and CardBus function should have a standard set of powercapabilities appropriate to the class. An example might be to require support either forall four power states or for some lesser number. Requirements might also be specifiedfor accuracy and frequency of power status updates. Finally, there might be class-specific requirements for Wakeup capabilities. For example, all modems should be ableto wake the PC from D1, and so on.

Device-class functionalcharacteristics

Each class of PCI and CardBus function should have a standard definition of theavailable subset of functioning capabilities and features in each power state. Forexample, the network adapter can receive, but cannot transmit; the sound card is fullyfunctional except that the power amps are off; and so on.

Device-class Wakeupcharacteristics

Each class of PCI and CardBus function should have a standard definition of i tsWakeup policy, including a recommended resume latency specification. This includesspecifying the various class-specific events that can wake up the system, and the powerstates from which the Wakeup can be signaled, with implementation details andexamples where appropriate.

3.2.1.4 Bus Support for PCI and CardBus Function Power Management

Four base capabilities enable a robust pow er man agemen t solution. The capabilities are defined as:

Get Capabilities operation This operation informs the operating system of the power management capabilities andfeatures of a given function. It is performed as a part of the Operating Systems deviceenumeration

1and uses the information it receives to help determine the power

management policies to implement in the system. Information required from thefunction include which power states are implemented, and the functions Wakeupcapabilities.

Set Power State operation This operation puts the function into a specific power management state and enablespower management features based on the global system power management policyand the functions specific capabilities. This includes setting the function to wake thesystem from a sleeping state if certain events occur.

Get Power Status operation This operation returns information about the current power state of the PCI function.

Wakeup operation This is a mechanism for having a PCI or CardBus function wake the system from asleeping state on specified events.

1 The PCI function pr ovides power m anagem ent capabilities reporting throug h a stand ard r egister definition as

specified in this d ocument.


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While ind ividua l PCI and Card Bus functions mu st supp ort only the first three capabilities with

wakeu p being optional, all basic power m anagement operations must be sup ported by the bus

architecture to ensure tha t PCI and CardBus functions on the bus can be pow er managed . The fourth

opera tion, Wakeup, is not optional for a PCI-to-CardBus bridge d evice: these devices must sup port

wakeup.

For multi-fun ction PCI and Card Bus comp onents there is a common portion of bus interface logic thatph ysically bind s each of the sup ported functions to the PCI or CardBus bus. This comm on logics

pow er consump tion is explicitly reported if supp orted, using the Data register of Function 0. For

further detail on the optional reporting of PCI function power consumption see 3.3.2.6 Dat a (Of fset =

7).

Control of the common logic is hand led by the mu lti-function device in a software transpar ent

fashion. For further power savings in a runtime environment, the enabling and disabling of some

portion of this common PCI or Card Bus bu s interface logic is the resp onsibility of the mu lti-function

component hard ware. This imp licit pow er control, if implemented, may be based up on the p ower

states of the functions behind it. As an example one might consider a hard wa re adm inistered logic

control policy wh ere the common logic can not be internally powered down un less all of the fun ctions

hosted by the device have been placed in theD3ho t state first.

3.3 PCI-to-CardBus Bridge Power Management InterfaceThe four basic power management operations that have been defined are: Capabilities Reporting,

Power Status Reporting, Setting Pow er State and System Wakeup . Of these four capabilities all are

requ ired of each fun ction w ith the exception of wakeup event genera tion. This section describes the

format of the registers in PCI-to-Card Bus bridge configur ation space which are used by these

operations.

The Status and Capabilities Pointer (Cap_ptr) field s have been h ighlighted to ind icate where the PCI

Power Management features app ear in the standard Configuration Space Head er.


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Device ID Vendor ID 00H

Status(with bit 4 set to 1) Command 04h

Class Code Revision ID 08h

BIST Header Type Latency Timer Cache Line Size 0Ch

10H

Cap_Ptr(type 2) 14h

Base Address Registers 18h

2Ch

34h

38h

Bridge Control Interrupt Pin Interrupt Line 3Ch

Subsystem ID Subsystem Vendor ID 40H

16-bit PC Card IF Legacy Mode Base Address 44h

Reserved 48-7Fh

User Defined 80-FFh

Figure 3-2: . Standard PCI Configuration Space Header Type 2

Softwa re mu st have a stand ard m ethod of determining if a specific function is designed in accordance

with this specification. This is accomplished by u sing a bit in th e PCI Status register to indicate the

presence of the Cap abilities List and a single byte in the stand ard PCI Configur ation Space Head er

which acts as a pointer to a linked list of ad ditional capabilities. Software can th en traver se the list

looking for the prop er ID for PCI-to-CardBus Bridge Pow er Managemen t (Cap_ID=01H). If there is no

Capabilities List (New Capabilities bit in the Status register = 0) or if the list does not contain an item

with the proper ID, the function does not su pp ort the PCI-to-CardBus Bridge Power Management

interface described in this docum ent and the Operating System w ill assum e that the function onlysupports theD0 and D3cold pow er man agemen t states. These Legacy PCI-to-Card Bus bridge functions

may also require a device specific initialization sequ ence after any transition fromD3cold to D0 (see

3.8.3 Restoring PCI Functions From a Low Pow er Sta te).

3.3.1 Capabilities List Data Structure

The New Capabilities bit in the PCI Status Register (offset=06h) indicates w hether or n ot the subject

function implements a linked list of extended capabilities. Specifically, if bit 4 is set, the Cap_Ptr

register is implemented to give the offset in configuration sp ace for the first item in the list.


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Table 3-1: PCI Status Register

Bits Default Value Read/Write Description

15:05 -- -- Definition given in PCI Local Bus SpecificationRevision 2.1

04 1B Read Only New Capabilities- This bit indicates whether this function

implements a list of extended capabilities such as PCIPower Management. When set this bit indicates thepresence of New Capabilities. A value of 0 means thatthis function does not implement New Capabilities.

03:00 0H Read Only Reserved

The location of th e Cap abilities Pointer (Cap_Ptr) depend s on the PCI-to-CardBus bridge header type.

See 3.3.1.1 Capabiliti es List Cap_Ptr Locati onfor Head er Type specific Cap_Ptr offsets.

Table 3-2: Capabilities Pointer - Cap_Ptr

Bits Default Value Read/Write Description

07:00 XXH Read Only The Cap_Ptr provides an offset into the functions PCI

Configuration Space for the location of the first item in theCapabilities Linked List. The Cap_Ptr offset is DWORDaligned so the two least significant bits are always 0s.

If a function d oes not imp lement any capabilities with IDs defined by the PCI SIG, theNew Capabilities

bit in the PCI Status register (bit 4) should read as 0 and the Cap_Ptr register should be ignored.

Values of 00H-7FH are not valid values for the Cap_Ptr because they point into the standard PCI-to-

Card Bus bridge head er. A PCI-to-CardBus bridge fun ction m ay choose any DWORD aligned offset as

indicated in Table 3-3: PCI Configuration Space Header Type / Cap_Ptr M appings.


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0 ID

Capability Y

ID

01h

Cap_Ptr

PM Regs

Capability X

8 bits

Standard PCI Config Header Type 0Offset 34h

Next Item

Next Item

Next Item

Figure 3-3: Capabilities Linked List

The figur e above show s how the capabilities list is imp lemented . The Cap_Ptr gives the location of

the first item in the list which is the PCI Power Management Registers in this examp le (although the

capabilities can be in any ord er). The first byte of each entry is required to be the ID of that capability.

The PCI Power Managemen t capability has an ID of 01H . The next byte is a pointer giving an absolute

offset in the functions PCI Configuration space to the next item in the list and m ust be DWORD

aligned. If there are no m ore entries in the list, the Next_Item_Ptr mu st be set to 0 to indicate that the

end of the linked list has been reached . Each capability can then have registers following the

Next_Item_Ptr. The definition of these registers (includ ing layou t, size and bit definitions) is specific

to each cap ability. The PCI Pow er Man agemen t Register Block is d efined in th is specification.

3.3.1.1 Capabilities List Cap_Ptr Location

There are currently three defined PCI Configur ation Space Head er types. The following table shows

wh ere to find the Cap_Ptr register for each of these Head er Types.

Table 3-3: PCI Configuration Space Header Type / Cap_Ptr Mappings

Header Type Associated PCI FunctionType

Cap_Ptr(PCI Config SpaceOffset)

Minimum Value Maximum Value

0 All other 34H 040H 0F8H

1 PCI to PCI Bridge 34H 040H 0F8H

2 PCI-to-CardBus Bridge 14H 080H 0F8H

Regardless of the imp lemented H eader Type the definition of the Cap_Ptr register and the New

Capabilities bit in the PCI Status register is common .


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3.3.2 Power Management Register Block Definition

This section describes the PCI Pow er Managemen t Interface registers.

The figure below illustrates the o rganization of the PCI Power Managemen t Register Block. The first

16 bits (Capabilities ID [offset = 0] and Next Item Pointer [offset = 1]) are used for the linked list

infrastructure.The next 32 bits (PM C [offset = 2] and PMCSR registers [offset = 4]) are requ ired for compliance with

this specification. The next 8 bit register (Bridge sup por t PMCSR extensions [offset = 6]) is requ ired

only for bridge functions, and th e remaining 8 bit Data register [offset = 8] is option al for any class of

function. As w ith all PCI configuration r egisters, these registers may be accessed as bytes, 16 bit

wor ds or 32 bit DWORDs.

Unless otherw ise specified, all wr ite operations to reserved r egisters must be treated as no-ops; that

is, the access must be completed n orma lly on the bu s and th e data is discarded . Read accesses to

reserved or un implemented registers must be completed normally and a data value of 0 returned.

Power Management Capabilities(PMC) Next Item Ptr Capability ID Offest = 0

Data PMCSR_BSE BridgeSupport Extensions

Power Management Control / Status Register(PMCSR)

Offset = 4

Figure 3-