pc card standard 8.0 volume 2 electrical specification

8/2/2019 PC Card Standard 8.0 Volume 2 Electrical Specification

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PC CARD STANDARD

Volume 2

Electrical Specification


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REVISION H ISTORYDate Electrical Specification

VersionPC Card StandardRelease

Revisions

11/90 1.0 PCMCIA 1.0 Memory only Interface

09/91 2.0 PCMCIA 2.0/JEIDA 4.1 Added I/O and Memory Interface

Defined RESET signal

Defined the WAIT# signal

11/92 2.01 PCMCIA 2.01 None

07/93 2.1 PCMCIA 2.1/JEIDA 4.2 Editorial corrections

02/95 5.0 February 1995 (5.0)Release

Added CardBus PC Card Interface

Redefined RFSH as VS1#

Defined the RFU pin in the I/O-Memory interface as VS2#

Defined multiple voltage operation

Defined Multiple Function 16-bit PC Cards

03/95 5.01 March 1995 (5.01) Update Editorial corrections

05/95 5.02 May 1995 (5.02) Update Clarification of Power Waveforms at Power-on

11/95 5.1 November 1995 (5.1)Update

Defined Custom Interfaces for PC Cards

Defined Indirect Addressing for PC Cards

Clarifications for Multifunction PC Cards

05/96 5.2 May 1996 (5.2) Update Defined Zoomed Video (ZV) Custom Interface

03/97 6.0 6.0 Release Defined Thermal Ratings for PC Cards

04/98 6.1 6.1 Update Defined Small PC Card form factor

Defined PCI Power Management for CardBus PC Cards

02/99 7.0 7.0 Release Defined Digital Video Broadcasting (DVB) CustomInterface

Defined PC Card Memory Paging

Corrections to PCI Power Management for CardBus PCCards

03/00 7.1 7.1 Update Defined OpenCable POD Custom Interface

Noted July 1, 2000 removal of references to DMA (Direct

Memory Access)Modification of CardBus Clock Control Protocol

11/00 7.2 7.2 Update Added maximum current requirements to 16-bit PC Cardinterface

Removed all references to Direct Memory Access (DMA)

04/01 8.0 8.0 Release Added CardBay PC Card Interface

Added Vcore Supplemental Voltage

Redefined VPP1 and VPP2 as VPP

2001 PCMCIA/ JEITA

All rights reserved.

No p art of this publication may be reprodu ced, stored in a retrieval system, or transmitted, in any form or by any m eans,mechanical, electronic, photocopying, recording or otherwise, without prior w ritten permission of PCMCIA and JEITA.

Published in the Un ited States of America.


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CONTENTS

1. Overview _____________________________________________ 1

1.1 Summary of Electrical Specification Changes ...........................................................................11.1.1 PCMCIA 2.0/ JEIDA 4.1 (September 1991)...................................................................................................... 1

1.1.2 PCMCIA 2.1/ JEIDA 4.2 (July 1993) ................................................................................................................. 1

1.1.3 PC Card Standard Febru ary 1995 Release (Release 5.0) ............................................................................... 1

1.1.4 PC Card Stan da rd March 1995 Update (Release 5.01) .................................................................................. 2

1.1.5 PC Card Stan da rd May 1995 Upd ate (Release 5.02)...................................................................................... 2

1.1.6 PC Card Stand ard Nov ember 1995 Update (Release 5.1)............................................................................. 2

1.1.7 PC Card Stan da rd May 1996 Upd ate (Release 5.2)........................................................................................ 2

1.1.8 PC Card Stand ard 6.0 Release (March 1997) .................................................................................................. 2

1.1.9 PC Card Stand ard 6.1 Release (April 1998) .................................................................................................... 2

1.1.10 PC Card Stand ard 7.0 Release (Febru ary 1999).............................................................................................. 2

1.1.11 PC Card Stand ard 7.1 Upd ate (March 2000) .................................................................................................. 3

1.1.12 PC Card Stand ard 7.2 Upd ate (N ovem ber 2000) ........................................................................................... 3

1.1.13 PC Card Stand ard Release 8.0 (April 2001) .................................................................................................... 3

1.2 Con ven tion s ...................................................................................................................................3

1.2.1 Signal Na min g .................................................................................................................................................... 3

1.2.2 Nu meric Repr esen tation .................................................................................................................................... 3

1.2.3 Bit Action Repr esen tation ................................................................................................................................. 4

1.2.4 Signal Summa ry ................................................................................................................................................. 4

2. Common Pin Description _______________________________ 5

2.1 Power an d Grou nd Pins ...............................................................................................................52.1.1 VCC an d GND Pin s............................................................................................................................................. 5

2.1.2 VPP/ VCORE Pin s..................................................................................................................................................5

2.1.3 Pow er (Therma l) Con sid era tions ..................................................................................................................... 6

2.2 Interface Con figu ra tion Pins........................................................................................................6

2.2.1 Card Detect P ins (CD[2::1]# and CCD[2::1]#) ................................................................................................6

2.2.2 Voltage Sense Pins (VS[2::1]# an d CVS[2::1])................................................................................................. 7

3. Card Typ e Detection Mechan ism ________________________ 9

3.1 PC Card En cod ings .......................................................................................................................9

3.2 Socket Key Selection ...................................................................................................................10

3.3 Graceful Rejection in 16bit PC Card Only Sockets ...............................................................11

3.4 Determ ining Card Type in Card Bus PC Card Cap able Sockets ...........................................11

3.5 Determ ining Card Type in Card Bay PC Card Cap able Sockets...........................................12

4. 16-bit PC Card Electrical In terface ______________________ 13


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4.1 Com patibility Issu es....................................................................................................................13

4.1.1 RESET and WAIT# Suppo rt ........................................................................................................................... 13

4.1.2 VS1# rep laces RFSH (pin 43).......................................................................................................................... 13

4.2 Pin Assignments ..........................................................................................................................13

4.3 16-bit PC Card Features ..............................................................................................................164.3.1 Mem ory Ad dress Space .................................................................................................................................. 16

4.3.2 Mem ory Only Inter face ................................................................................................................................... 17

4.3.3 I/ O Ad dress Space........................................................................................................................................... 17

4.3.4 I/ O Inter face ..................................................................................................................................................... 18

4.3.5 Custom Inter faces ............................................................................................................................................ 18

4.3.6 Configurable Cards.......................................................................................................................................... 19

4.4 Signal Descr iption .......................................................................................................................19

4.4.1 Ad dress BUS (A[25::0]).................................................................................................................................... 19

4.4.2 Data BUS (D[15::0]).......................................................................................................................................... 19

4.4.3 Card Enab le (CE[2::1]#)................................................................................................................................... 194.4.4 Ou tp ut Enable (OE#) ....................................................................................................................................... 20

4.4.5 Write Enab le (WE#) ......................................................................................................................................... 20

4.4.6 Read y (READY)................................................................................................................................................ 20

4.4.7 Interrup t Request (IREQ#) [I/ O and Memory Interface] ........................................................................... 21

4.4.7.1 Inter ru pt Request Rout ing .................................................................................................................. 21

4.4.7.2 Level and Pu lsed Mod e Interrup t Sup port ....................................................................................... 22

4.4.7.2.1 Level Mod e Interrup t Signal ....................................................................................................... 22

4.4.7.2.2 Pu lsed Mod e Inter ru pt Signal..................................................................................................... 22

4.4.8 Card Detect (CD[2::1]#) ................................................................................................................................... 23

4.4.9 Write Protect (WP) [Mem ory Only Interface] .............................................................................................. 23

4.4.10 I/ O Is 16 Bit Port (IOIS16#) [I/ O and Mem ory In terface].......................................................................... 23

4.4.11 Attr ibu te Mem ory Select (REG#) ................................................................................................................... 23

4.4.12 Battery Voltage Detect (BVD[2::1]) [Mem ory Only In terface].................................................................... 24

4.4.13 Status Chan ged (STSCHG#) [I/ O and Memory Interface]......................................................................... 24

4.4.14 Audio Digita l Waveform (SPKR#) [I/ O and Memory Inter face] .............................................................. 24

4.4.15 Program an d Peripheral Voltages (VPP) ....................................................................................................... 25

4.4.16 Voltage and Ground (VCC & GN D) ............................................................................................................... 25

4.4.16.1 Socket VCC for CIS Read ...................................................................................................................... 25

4.4.16.2 PC Card VCC for CIS Read .................................................................................................................. 26

4.4.16.3 Changing PC Card VCC ....................................................................................................................... 26

4.4.17 Voltage Sense (VS[2::1]#) ................................................................................................................................ 26

4.4.18 I/ O Read (IORD# ) [I/ O and Mem ory In terface]......................................................................................... 27

4.4.19 I/ O Write (IOWR#) [I/ O and Mem ory In terface] ....................................................................................... 27

4.4.20 Car d Reset (RESET) ......................................................................................................................................... 28

4.4.21 Exten d Bus Cycle (WAIT# )............................................................................................................................. 28

4.4.22 Inpu t Port Acknow ledge (INPACK#) [I/ O and Memor y Interface]......................................................... 28

4.5 Memory Function ........................................................................................................................28

4.5.1 Com mo n Mem ory Fun ction ........................................................................................................................... 28


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4.5.1.1 Com mo n Memory Read Fu nction for PC Cards .............................................................................. 28

4.5.1.2 Com mo n Memory Write Fun ction for PC Cards ............................................................................. 29

4.5.1.3 Comm on Memo ry Write Function for OTPROM, EPROM and Flash Mem ory .......................... 29

4.5.2 Attr ibut e Mem ory Fun ction ............................................................................................................................ 30

4.5.2.1 Attr ibute Mem ory Read Fun ction ......................................................................................................30

4.5.2.2 Attr ibute Mem ory Write Fu nction ..................................................................................................... 30

4.5.2.3 Attribute Memory Write Function for Dual Sup ply OTPROM, EPROM and Flash Memory ... 30

4.5.3 Write Pro tect Fun ction .....................................................................................................................................31

4.6 Timin g Funct ions.........................................................................................................................31

4.6.1 Common Mem ory Read Timin g .................................................................................................................... 31

4.6.2 Common and Att ribu te Memor y Write Timin g........................................................................................... 33

4.6.2.1 Com mo n Mem ory Write Timin g........................................................................................................ 34

4.6.3 Attr ibut e Memor y Read Timin g Specification ............................................................................................. 34

4.6.4 Attr ibute Memor y Write Timing Specification ............................................................................................34

4.6.5 Mem ory Timin g Diagrams ............................................................................................................................. 35

4.7 Electrical Interface .......................................................................................................................364.7.1 Signal Inter face ................................................................................................................................................. 36

4.7.2 Mem ory Ad dress Decod ing ............................................................................................................................ 38

4.7.2.1 Fun ction Configura tion Registers Add ress Decod ing ..................................................................... 39

4.7.3 I/ O Ad dress Space Decod ing .........................................................................................................................39

4.7.3.1 Ind epend ent I/ O Ad dress Wind ow .................................................................................................. 39

4.7.3.2 Over lap pin g I/ O Ad dress Wind ow .................................................................................................. 40

4.8 Card Detect ...................................................................................................................................41

4.9 Battery Voltage Detect ................................................................................................................41

4.10 Pow er-u p and Pow er-d own ...................................................................................................42

4.10.1 Pow er-u p/ Pow er-d ow n Timin g .................................................................................................................... 42

4.10.2 Aver age Cu rrent Dur ing Card Configu ra tion .............................................................................................. 43

4.10.3 Data Retent ion .................................................................................................................................................. 44

4.10.4 Sup plem ent .......................................................................................................................................................44

4.11 I/ O Function .............................................................................................................................44

4.11.1 I/ O Tran sfer Fun ction .....................................................................................................................................44

4.11.2 I/ O In pu t Fu nction for I/ O Card s .................................................................................................................44

4.11.3 I/ O Ou tput Fun ction for I/ O Car ds .............................................................................................................. 45

4.11.4 I/ O Read (Inp ut ) Tim ing Specification ......................................................................................................... 46

4.11.5 I/ O Write (Outpu t) Tim ing Specification ..................................................................................................... 48

4.12 Function Con figura tion ...........................................................................................................49

4.12.1 Overview ...........................................................................................................................................................49

4.12.2 Single Fun ction PC Cards ............................................................................................................................... 49

4.12.3 Mu ltiple Fun ction PC Cards ........................................................................................................................... 49

4.12.4 Fun ction Configura tion Register s (FCRs) ..................................................................................................... 50

4.13 Card Con figu ra tion ..................................................................................................................51

4.13.1 Configura tion Op tion Register ....................................................................................................................... 52


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4.13.2 Configura tion an d Status Register ................................................................................................................. 55

4.13.3 Pin Replacement Register ............................................................................................................................... 56

4.13.4 Socket and Cop y Register ............................................................................................................................... 57

4.13.5 Exten ded Status Regis ter ................................................................................................................................. 58

4.13.6 I/ O Base Regis ter s (0 .. 3)................................................................................................................................ 58

4.13.7 I/ O Limit Regis ter ............................................................................................................................................ 59

4.13.8 Pow er Man agement Suppo rt Register .......................................................................................................... 59

4.13.9 Ad dress Extension Register s .......................................................................................................................... 61

4.14 Ind irect Access to PC Card Mem ory .....................................................................................63

5. Card Bus PC Card Electrical Interface ___________________ 65

5.1 Card Bus PC Card Signal Descrip tion .......................................................................................65

5.1.1 Pin Assignm ents............................................................................................................................................... 66

5.1.2 Signal/ Pin Descrip tion .................................................................................................................................... 70

5.1.2.1 System Pin s ........................................................................................................................................... 70

5.1.2.2 Ad dress and Data Pins ........................................................................................................................ 705.1.2.3 Inter face Contro l Pins .......................................................................................................................... 71

5.1.2.4 Arbitra tion Pins (Bus Masters On ly) ................................................................................................. 71

5.1.2.5 Error Reportin g Pins ............................................................................................................................ 72

5.1.2.6 Inter ru pt Request Pin ........................................................................................................................... 72

5.1.2.7 Ad ditiona l Signals ................................................................................................................................ 72

5.1.3 Centra l Resou rce Fun ctions ............................................................................................................................ 73

5.2 Card Bus PC Card Op erat ion .....................................................................................................73

5.2.1 Bus Commands ................................................................................................................................................ 73

5.2.1.1 Com ma nd Definit ion ........................................................................................................................... 73

5.2.1.2 Com ma nd Usag e Rules ....................................................................................................................... 75

5.2.2 CardBus PC Card Proto col Fun dam entals ................................................................................................... 76

5.2.2.1 Basic Tran sfer Contro l ......................................................................................................................... 77

5.2.2.2 Ad dressin g ............................................................................................................................................ 77

5.2.2.3 Byte Alignm ent..................................................................................................................................... 79

5.2.2.4 Bus Driv ing and Turna rou nd ............................................................................................................. 79

5.2.3 Bus Tran saction s .............................................................................................................................................. 80

5.2.3.1 Read Tran saction .................................................................................................................................. 80

5.2.3.2 Write Tran saction ................................................................................................................................. 82

5.2.3.3 Tran saction Term ination ..................................................................................................................... 82

5.2.3.3.1 Master Initia ted Term ination ...................................................................................................... 83

5.2.3.3.2 Targ et Initia ted Term ination ....................................................................................................... 855.2.4 Arbitr at ion ......................................................................................................................................................... 89

5.2.5 Arbitra tion Signalin g Protocol ....................................................................................................................... 89

5.2.5.1 Fast Back-to-Back Tran saction s .......................................................................................................... 91

5.2.5.2 CardBus PC Card Idle Condition ....................................................................................................... 93

5.2.5.3 Latency ................................................................................................................................................... 93

5.2.5.3.1 Man agin g Laten cy on CardBus PC Card .................................................................................. 94

5.2.5.3.2 Low Laten cy Design Guid elines ................................................................................................ 95


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5.2.6 Exclus ive Access ............................................................................................................................................... 95

5.2.6.1 Startin g an Exclusive Access ............................................................................................................... 98

5.2.6.2 Continu ing an Exclusive Access.........................................................................................................99

5.2.6.3 Accessing a Locked Agen t................................................................................................................... 99

5.2.6.4 Com plet ing an Exclusive Access ...................................................................................................... 100

5.2.6.5 Supp orting CBLOCK# and Write-back Cache Coheren cy ........................................................... 100

5.2.6.6 Com plete Bus Lock............................................................................................................................. 101

5.2.7 Oth er Bus Op era tions .................................................................................................................................... 101

5.2.7.1 Dev ice Selection .................................................................................................................................. 101

5.2.7.2 Special Cycle ....................................................................................................................................... 102

5.2.7.3 Ad dress/ Data Stepp ing ..................................................................................................................... 103

5.2.7.4 Configura tion Cycle ........................................................................................................................... 104

5.2.7.4.1 Genera ting Configura tion Cycles ............................................................................................. 106

5.2.7.4.1.1 Configurat ion Mecha nism ............................................................................................... 106

5.2.7.4.1.2 Genera ting Special Cycles with the Configur ation Mechanism ................................. 108

5.2.8 Erro r Fun ctions ............................................................................................................................................... 108

5.2.8.1 Parity .................................................................................................................................................... 108

5.2.8.2 Err or Rep orting................................................................................................................................... 110

5.2.8.2.1 Par ity Error Resp onse and Rep ort ing on CPERR# ................................................................ 110

5.2.8.2.2 Erro r Resp onse an d Reportin g on CSERR# ............................................................................ 111

5.2.9 Cach e Sup port................................................................................................................................................. 112

5.2.10 Clock Con trol .................................................................................................................................................. 114

5.2.10.1 Clock Frequ ency ................................................................................................................................. 114

5.2.10.2 Clock Con trol Protocol....................................................................................................................... 114

5.2.10.2.1 Clock Stop or Slow dow n ...................................................................................................... 115

5.2.10.2.2 Clock Restar t o r Speed up .....................................................................................................116

5.2.10.2.3 Main tain ing the Inter face Clock ...........................................................................................1175.2.11 Status Changed Notification ......................................................................................................................... 118

5.2.11.1 Car d Status Chan ged ......................................................................................................................... 118

5.2.11.2 System and Inter face Wake up ......................................................................................................... 118

5.2.11.3 Regis ter Descrip tion s .........................................................................................................................120

5.2.11.3.1 Fun ction Event Register ......................................................................................................... 120

5.2.11.3.2 Fun ction Event Mask Register .............................................................................................. 122

5.2.11.3.3 Fun ction Present State Regis ter ............................................................................................ 124

5.2.11.3.4 Force Event Cap ability ........................................................................................................... 125

5.2.11.3.5 Defau lt Field Values ............................................................................................................... 127

5.2.12 Card Au dio ..................................................................................................................................................... 127

5.2.13 Special Design Consid era tions ..................................................................................................................... 128

5.2.13.1 Mu ltiple Retry Term ination .............................................................................................................. 128

5.3 CardBus PC Card Electrical Specification .............................................................................128

5.3.1 Overview .........................................................................................................................................................128

5.3.1.1 Dyn am ic v s. Static Drive Specification ............................................................................................ 129

5.3.2 Compo nen t Specifications............................................................................................................................. 129

5.3.2.1 3.3 V Signalin g Environment ............................................................................................................ 130


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5.3.2.1.1 DC Specifications........................................................................................................................ 130

5.3.2.1.2 AC Specifications........................................................................................................................ 131

5.3.2.1.3 CSTSCHG Buffer Specificatio n ................................................................................................. 131

5.3.2.1.4 CCLK AC Specifications ............................................................................................................ 131

5.3.2.1.5 Maxim um AC Ratings an d Device Protection (CCLK) ......................................................... 132

5.3.2.1.6 No ise Consid era tions................................................................................................................. 133

5.3.2.2 Timin g Specification .......................................................................................................................... 134

5.3.2.2.1 Clock Specificatio ns ................................................................................................................... 134

5.3.2.2.2 Timing Par am eters ..................................................................................................................... 135

5.3.2.2.3 Measurem ent and Test Conditions .......................................................................................... 136

5.3.2.3 Vend or Pro vid ed Specifications ....................................................................................................... 137

5.3.3 System (Moth erboard) Specifications .......................................................................................................... 137

5.3.3.1 Clock Skew .......................................................................................................................................... 137

5.3.3.2 Reset ..................................................................................................................................................... 138

5.3.3.3 Pu ll-ups................................................................................................................................................ 139

5.3.3.3.1 Pu ll-up Values for Contro l Signals .......................................................................................... 140

5.3.3.3.2 Pu ll-up Valu es for Card Detect and Voltage Sense Pins ....................................................... 140

5.3.3.3.3 Pu ll-up Resistor Requ irem ents ................................................................................................. 141

5.3.3.4 Pow er Sequen cing .............................................................................................................................. 144

5.3.3.5 System Timin g Budg et ...................................................................................................................... 144

5.3.3.6 Physical Requirem ents ...................................................................................................................... 144

5.3.3.6.1 Rout ing and Layou t of Four Layer Board s ............................................................................. 144

5.3.3.6.2 Moth erbo ard Imp ed ance........................................................................................................... 144

5.3.4 CardBus PC Card Specifications .................................................................................................................. 145

5.3.4.1 Pow er Requ irem ents.......................................................................................................................... 145

5.3.4.1.1 Decoupling .................................................................................................................................. 145

5.3.4.1.2 Extern al Pow er Supplies ........................................................................................................... 1455.3.4.2 Physical Requirem ents ...................................................................................................................... 145

5.3.4.2.1 Trace Length Limits ................................................................................................................... 145

5.3.4.2.2 Imped an ce ................................................................................................................................... 145

5.3.4.2.3 Signal Loading ............................................................................................................................ 146

5.4 CardBus PC Card Program ming Mod el ................................................................................146

5.4.1 Overview ......................................................................................................................................................... 146

5.4.2 Card Org an ization ......................................................................................................................................... 146

5.4.2.1 Configura tion Space........................................................................................................................... 151

5.4.2.1.1 Com man d .................................................................................................................................... 154

5.4.2.1.2 Status ............................................................................................................................................ 155

5.4.2.1.3 Cach e Line size ........................................................................................................................... 157

5.4.2.1.4 Latency Timer ............................................................................................................................. 157

5.4.2.1.5 Header Typ e................................................................................................................................ 158

5.4.2.1.6 Built-in Self Test (BIST).............................................................................................................. 158

5.4.2.1.7 Base Ad dr ess Register ............................................................................................................... 158

5.4.2.1.8 CIS Poin ter ................................................................................................................................... 160

5.4.2.1.9 Expansion ROM Base A ddr ess Reg ister ................................................................................. 162


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5.4.2.1.10 Cap _Ptr .................................................................................................................................... 162

5.4.2.1.11 Inter ru pt Pin ............................................................................................................................ 162

5.4.2.1.12 Tup le Space ............................................................................................................................. 163

5.4.2.1.13 Register Summary .................................................................................................................. 163

5.4.2.2 Mem ory Space .................................................................................................................................... 164

5.4.2.3 I/ O Space............................................................................................................................................. 165

5.4.2.4 Expan sion ROM.................................................................................................................................. 165

5.5 Requ irem ents For Card Bus PC Car ds and Sockets ..............................................................167

5.5.1 Overview .........................................................................................................................................................167

5.5.2 Software Requ irem ents ................................................................................................................................. 167

5.5.2.1 Socket Services .................................................................................................................................... 167

5.5.2.2 Card Services....................................................................................................................................... 168

5.5.2.3 System Resou rce Availability ........................................................................................................... 168

5.5.2.4 System Resou rce Deter min ation ....................................................................................................... 168

5.5.2.5 Enabler Sup port .................................................................................................................................. 169

5.5.3 Card Requirem ents ........................................................................................................................................ 1695.5.3.1 Configura tion Space ........................................................................................................................... 169

5.5.3.2 Requ ired CIS ....................................................................................................................................... 169

5.5.3.3 Requ ired Signals ................................................................................................................................. 170

5.5.3.4 Pu ll-up / Pull-down Resistors ............................................................................................................ 170

5.5.3.5 CSTSCHG Sup port ............................................................................................................................. 170

5.5.3.6 Pow er Consumpt ion .......................................................................................................................... 171

5.5.3.7 I/ O Space Suppo rt.............................................................................................................................. 171

5.5.4 Socket Requirem ents...................................................................................................................................... 171

5.5.4.1 16-bit PC Card Suppo rt...................................................................................................................... 171

5.5.4.2 Ad dress Spaces ................................................................................................................................... 172

5.5.4.2.1 Mem ory Space............................................................................................................................. 172

5.5.4.2.2 I/ O Sup port ................................................................................................................................. 173

5.5.4.2.2.1 CardBus PC Card w ith Memory Map ped I/ O ............................................................. 173

5.5.4.2.2.2 CardBus PC Card with I/ O Space.................................................................................. 173

5.5.4.2.2.3 ISA Support Imp lications ................................................................................................ 174

5.5.4.3 Inter ru pt Ha nd ling and Rout ing ...................................................................................................... 174

5.5.4.3.1 Fun ctional Inter ru pts (CINT# ).................................................................................................. 174

5.5.4.3.2 Statu s Chan ge Even ts ................................................................................................................. 174

5.5.4.4 Register Descrip tions ......................................................................................................................... 175

5.5.4.4.1 Socket EVENT Regis ter .............................................................................................................. 175

5.5.4.4.2 Socket MASK Regis ter ............................................................................................................... 176

5.5.4.4.3 Socket PRESENT STATE Regis ter ............................................................................................ 177

5.5.4.4.4 FORCE Even t Cap ability ........................................................................................................... 180

5.5.4.4.5 CON TROL Regis ter ....................................................................................................................182

5.5.4.5 VPP/ VCORE Pow er Requ irements ..................................................................................................... 182

5.5.4.6 Card Inser tion and Removal ............................................................................................................. 183

5.5.4.6.1 Car d Insertion .............................................................................................................................183

5.5.4.6.2 Car d Remova l ............................................................................................................................. 184


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5.5.4.7 Pow er Cycling the Inter face.............................................................................................................. 185

5.5.4.7.1 Signal Requ irem ents .................................................................................................................. 185

5.5.4.7.2 CSTSCHG Requ irements ........................................................................................................... 185

5.5.4.7.3 In-Rush Cu rr ent .......................................................................................................................... 185

5.5.4.8 Requ ired Pin s...................................................................................................................................... 186

5.5.4.9 Clock Stopp ing Sup port .................................................................................................................... 186

5.5.4.10 Specia l Cycle Sup port ........................................................................................................................ 186

5.5.4.11 Actions When Ad ap ter Is Reset........................................................................................................ 186

6. PCI Bus Power Man agemen t In terface for CardBus Cards 187

6.1 Introduction ................................................................................................................................187

6.1.1 Goals of this Specification ............................................................................................................................. 187

6.1.2 Targ et Audience ............................................................................................................................................. 188

6.1.3 Over view / Scop e ............................................................................................................................................ 188

6.1.4 Glossa ry of Term s .......................................................................................................................................... 190

6.1.5 Related Documents ........................................................................................................................................ 191

6.1.6 Conven tions Used in this Chapter ............................................................................................................... 192

6.2 CardBus Pow er Man agement Overv iew ...............................................................................192

6.2.1 CardBus Power Man agement States ........................................................................................................... 192

6.2.1.1 CardBus Fun ction Pow er States ....................................................................................................... 192

6.2.1.2 Bus Pow er States ................................................................................................................................ 193

6.2.1.3 Device-Class Specifications ............................................................................................................... 193

6.2.1.4 Bus Supp ort for Card Bus Function Pow er Management ............................................................. 194

6.3 CardBus Pow er Managem ent Inter face .................................................................................195

6.3.1 Cap abilities List D ata Structure ................................................................................................................... 196

6.3.1.1 Cap abilities List Cap _Ptr Location .................................................................................................. 197

6.3.2 Pow er Man agement Register Block Defin ition .......................................................................................... 198

6.3.2.1 Cap ability Iden tifier - Cap _ID (Offset = 0) ..................................................................................... 198

6.3.2.2 Next Item Poin ter - N ext_Item_Ptr (Offset = 1).............................................................................. 199

6.3.2.3 PMC - Pow er Man agement Cap abilities (Offset = 2) .................................................................... 199

6.3.2.4 PMCSR - Pow er Mana gemen t Control/ Status (Offset = 4).......................................................... 200

6.3.2.5 PMCSR_BSE - PMCSR PCI-to-PCI Bridg e Supp ort Extensions (Offset=6) Not Used in

Card Bus Car ds - Reserv ed .................................................................................................................... 202

6.3.2.6 Data (Offset = 7) ................................................................................................................................. 203

6.4 Card Bus Bus Power States .......................................................................................................205

6.4.1 CardBusB0 State - Fully On ......................................................................................................................... 205

6.4.2 CardBusB1 State ............................................................................................................................................ 206

6.4.3 CardBusB2 State ............................................................................................................................................ 206

6.4.4 CardBusB3 State - Off ................................................................................................................................... 206

6.4.5 CardBus Bus Pow er State Transit ions ......................................................................................................... 207

6.4.6 CardBus Clocking Considera tions............................................................................................................... 207

6.4.7 Control/ Status of Car dBus Bus Power Management States .................................................................... 208

6.4.7.1 Contro l of Second ary Bus Pow er Source and Clock ...................................................................... 208


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6.5 CardBus Fu nction Pow er Man agement States ......................................................................209

6.5.1 CardBus Function D0 State ...........................................................................................................................209




6.5.4.1 Software AccessibleD3 (D3hot) ......................................................................................................... 211

6.5.4.2 Power Off (D3cold)............................................................................................................................... 211

6.5.5 CardBus Function Pow er State Tran sition s ................................................................................................ 211

6.5.6 CardBus Card Fun ction Pow er Man agem ent Policies .............................................................................. 213

6.5.6.1 State Transition Recovery Time Requirements .............................................................................. 217

6.6 CardBus Card s an d Pow er Management ..............................................................................218

6.6.1 CardBus Card Context................................................................................................................................... 221

6.6.2 PME_En/ PME_Statu s and Card Bus Card s ................................................................................................222

6.7 Power Managem ent Even ts .....................................................................................................223

6.7.1 Auxiliary Power forD3cold Pow er Man agement Events ........................................................................... 223

6.8 Software Sup port for PCI Pow er Management ....................................................................224

6.8.1 Iden tifying Card Bus Fun ction Capabilities ................................................................................................ 224

6.8.2 Placing Card Bus Function s in a Low Power State ..................................................................................... 225

6.8.2.1 Buses..................................................................................................................................................... 225

6.8.2.2 D3 State ................................................................................................................................................ 225

6.8.3 Restoring PCI Fun ctions From a Low Pow er State .................................................................................... 225

6.8.3.1 Dx States and the DSI Bit ................................................................................................................... 225

6.8.3.2 D1 an d D2 States................................................................................................................................. 225

6.8.3.3 D3 State ................................................................................................................................................ 226

6.8.4 Wak e Even ts....................................................................................................................................................226

6.8.4.1 Wake Event Support .......................................................................................................................... 226

6.8.4.2 TheD0 "Initialized " State From a Wak e Event ............................................................................... 226

6.8.5 Get Cap abilities .............................................................................................................................................. 227

6.8.6 Set Pow er State ............................................................................................................................................... 227

6.8.7 Get Pow er Status ............................................................................................................................................ 227

6.9 Other Con sid erations ................................................................................................................227

7. CardBay PC Card Interface __________________________ 229

7.1 CardBay PC Card Electrical Interface ....................................................................................229

7.1.1 Detectin g the CardBay PC Card ................................................................................................................... 229

7.1.2 Determinin g Card Bay Card Fu nction ality .................................................................................................. 2297.1.2.1 Qu ery Pin Requ irem ents and Ch aracter istics................................................................................. 230

7.2 Card Bay PC Card Physica l Interface ......................................................................................232

7.2.1 Pin Assign ment............................................................................................................................................... 234

8. Sp ecial Cycle Messages _______________________________ 237

8.1 Message Encodings ...................................................................................................................237


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8.2 Use of Specific Encodings ........................................................................................................237

9. Card Bus PC Card Connector Test Methodology _________ 239

9.1 Backgrou nd ................................................................................................................................239

9.2 Test Hardware Recomm end ation s .........................................................................................2399.2.1 Genera l Recomm end ation s ........................................................................................................................... 239

9.2.2 Host-sid e Requ irem ents ................................................................................................................................ 240

9.2.3 Card-side Recomm end ation s ....................................................................................................................... 240

9.2.4 Measur ement Equipm ent Recomm end ation s ............................................................................................ 240

9.3 Test Board Consid erations .......................................................................................................240

9.3.1 Host-sid e Imp lementation ............................................................................................................................ 241

9.3.2 Card-side Imp lementation ............................................................................................................................ 242

9.4 Measu rement Method ology.....................................................................................................243

9.4.1 Find ing th e Worst Case Grou nd Bounce .................................................................................................... 243

10. PC Card Custom In terfaces _________________________ 245

10.1 Custom Inter face Requ irem ents...........................................................................................245

10.1.1 Pu rp ose/ Over view ........................................................................................................................................ 245

10.1.2 Com patibility .................................................................................................................................................. 245

10.1.3 Pin Assign ments ............................................................................................................................................. 245

10.1.4 Featu res ........................................................................................................................................................... 245

10.1.5 Signal Descrip tion .......................................................................................................................................... 245

10.1.6 Function s ......................................................................................................................................................... 246

10.1.7 Timing ............................................................................................................................................................. 246

10.1.8 Electr ical Interface .......................................................................................................................................... 246

10.1.9 Specific Signals and Fun ctions ..................................................................................................................... 246

10.2 ZV Port Custom Interface (0141H).......................................................................................247

10.2.1 Overview ......................................................................................................................................................... 247

10.2.2 Com patibility .................................................................................................................................................. 247

10.2.3 Pin Assign ments ............................................................................................................................................. 249

10.2.4 Featu res ........................................................................................................................................................... 251


10.2.5.1 PCLK .................................................................................................................................................... 251

10.2.5.2 VSYNC................................................................................................................................................. 251

10.2.5.3 HREF.................................................................................................................................................... 251

10.2.5.4 Y[7::0] ................................................................................................................................................... 251

10.2.5.5 UV[7::0]................................................................................................................................................ 251

10.2.5.6 LRCLK ................................................................................................................................................. 251

10.2.5.7 SDATA ................................................................................................................................................. 252

10.2.5.8 SCLK .................................................................................................................................................... 252

10.2.5.9 MCLK................................................................................................................................................... 252

10.2.6 Function s ......................................................................................................................................................... 253


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2001 PCMCIA/JEITA xiii

10.2.7 Timing .............................................................................................................................................................. 253

10.2.7.1 Video Int erface Timing ......................................................................................................................253

10.2.7.2 Au dio Interface Timing ..................................................................................................................... 254


10.2.9 Specific Signals an d Fun ctions ..................................................................................................................... 255

10.2.10 PC Card Con nector Test Meth od ology ................................................................................................... 255

10.3 DVB CI Por t Custom Inter face (0241h) ...............................................................................257

10.3.1 Overview .........................................................................................................................................................257

10.3.2 Com patibility .................................................................................................................................................. 258

10.3.3 Pin Assign ments ............................................................................................................................................. 259

10.3.4 Featu res............................................................................................................................................................ 260


10.3.5.1 MDI[7::0].............................................................................................................................................. 261

10.3.5.2 MISTRT................................................................................................................................................ 261

10.3.5.3 MIVAL ................................................................................................................................................. 261

10.3.5.4 MDO [7::0]............................................................................................................................................26110.3.5.5 MOSTRT.............................................................................................................................................. 261

10.3.5.6 MOVAL ............................................................................................................................................... 261

10.3.5.7 MCLKI ................................................................................................................................................. 261

10.3.5.8 MCLKO ................................................................................................................................................ 261

10.3.6 Funct ions .........................................................................................................................................................262

10.3.7 Timing .............................................................................................................................................................. 262


10.3.9 Specific Signals an d Fun ctions ..................................................................................................................... 264

10.4 OpenCable POD Port Custom Interface (0341h) ...........................................................265

10.4.1 Overview .........................................................................................................................................................265

Com pa tibil ity .............................................................................................................................................................. 266

10.4.3 Pin Assign ments ............................................................................................................................................. 267

10.4.4 Featu res............................................................................................................................................................ 269


10.4.5.1 MDI[7::0].............................................................................................................................................. 270

10.4.5.2 MISTRT................................................................................................................................................ 270

10.4.5.3 MIVAL ................................................................................................................................................. 270

10.4.5.4 MDO [7::0]............................................................................................................................................270

10.4.5.5 MOSTRT.............................................................................................................................................. 270

10.4.5.6 MOVAL ............................................................................................................................................... 270

10.4.5.7 MCLKI ................................................................................................................................................. 27010.4.5.8 MCLKO ................................................................................................................................................ 270

10.4.5.9 EXTCH# (Exten ded Chan nel)........................................................................................................... 271

10.4.5.10 DRX .................................................................................................................................................. 271

10.4.5.11 ETX................................................................................................................................................... 271

10.4.5.12 CRX................................................................................................................................................... 271

10.4.5.13 CTX................................................................................................................................................... 271

10.4.5.14 ITX .................................................................................................................................................... 271


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10.4.5.15 QTX .................................................................................................................................................. 271

10.4.6 Function s ......................................................................................................................................................... 271

10.4.7 Timing ............................................................................................................................................................. 272

10.4.7.1 Tran sp ort Stream Inter face Timin g.................................................................................................. 272


10.4.9 Specific Signals and Fun ctions ..................................................................................................................... 274


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2001 PCMCIA/JEITA xv

FIGURESFigu re 31 CCD[2::1]# an d CVS[2::1] Conn ections ................................................................12

Figure 4-1: Recommended PC Compatible Interrupt Request Signals................................22

Figure 4-2: Read Timin g Diagram .............................................................................................35

Figure 4-3: Write Tim ing Diagram ............................................................................................36

Figure 4-4: Card Detect ...............................................................................................................41

Figu re 4-5: Power-Up / Down Timing .......................................................................................43

Figure 4-6: Power-Dow n/ Pow er-Up Timing When Changing Vcc ....................................43

Figure 4-7: I/ O Read Tim ing .....................................................................................................46

Figu re 4-8: I/ O Wr ite Timing ....................................................................................................48

Figure 5-1 CardBus PC Card Basic Read Op era tion ...............................................................81Figure 5-2 CardBus PC Card Basic Write Op era tion ..............................................................82

Figure 5-3 CardBus PC Card Master Initiated Term ination .................................................83

Figure 5-4 CardBus PC Card Master-abor t Terminat ion .......................................................85

Figure 5-5 Target Initiated Term ina tion ...................................................................................88

Figure 5-6 CardBus PC Card Basic Arbitration.......................................................................90

Figu re 5-7 Arbitr ation for Back-to-Back Access ......................................................................93

Figu re 5-8 Com ponents of Access Latency ..............................................................................94

Figure 5-9 CardBus PC Card Starting an Exclusive Access ..................................................98

Figure 5-10 Card Bus PC Card Continu ing an Exclusive Access ..........................................99

Figure 5-11 Card Bus PC Card Accessing a Locked Agen t ..................................................100

Figure 5-12 CDEVSEL# Assertion ..........................................................................................101

Figu re 5-13 Ad dress Stepping .................................................................................................104

Figure 5-14 Typ e 0 an d Type 1 Configu ration Accesses ......................................................105

Figure 5-15 Layou t of CONFIG_ADDRESS Register ...........................................................106

Figure 5-16 Brid ge Translation for Type 0 Configu rat ion Cy cles ......................................107

Figure 5-17 Parity Operation ...................................................................................................109

Figure 5-18: CardBus PC Card Clock CCLKRUN# Unconn ected .....................................115

Figure 5-19 Card Bus PC Card Clock Stop or Slow Dow n ...................................................116

Figure 5-20 CardBus PC Card Clock Star t or Speed up .......................................................117

Figure 5-21 Mainta ining CardBus PC Card Clock................................................................118


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Figure 5-22: CardBus PC Card Fun ction Event Register .....................................................121

Figu re 5-23: Function Event Mask Register ...........................................................................122

Figu re 5-24: Function Present State Register .........................................................................124

Figu re 5-25: Function Force Event Reg ister ...........................................................................126

Figu re 5-26 V/ I Curves for 3.3 V Signa ling ...........................................................................132

Figure 5-27 Test Waveform for 3.3 V Signaling (CCLK)......................................................133

Figu re 5-28 Card Bus PC Card Clock Waveform ...................................................................134

Figure 5-29 Ou tput Timing Measu rem ent Con ditions ........................................................136

Figure 5-30 Input Timing Measurem ent Con ditions ...........................................................136

Figu re 5-31 Clock Skew Diagram ............................................................................................138

Figu re 5-32 Reset Timin g ..........................................................................................................139

Figure 5-33 Card w ith Memory and I/ O Space in Host System with no Separa te I/ O Space.........................................................................................................................................148

Figure 5-34 Mem ory-only Card in Host System ...................................................................149

Figure 5-35 I/ O Space-only Card in a H ost System w ith a Sepa rate I/ O Space..............150

Figure 5-36 Card and Host with All Spaces Described ........................................................151

Figure 5-37 Card Bus PC Card Configuration Space ............................................................153

Figu re 5-38 COMMAN D Register Layou t .............................................................................154

Figu re 5-39: STATUS Register Layout ....................................................................................156

Figu re 5-40 BIST Register .........................................................................................................158

Figure 5-41 Base Ad dress Register Map ping for Mem ory Space .......................................159

Figure 5-42 Base Ad dress Register Map ping for I/ O Space ...............................................160

Figu re 5-43 CIS POINTER Lay ou t...........................................................................................161

Figure 5-44 Expansion ROM Base Ad dress Register Layou t ..............................................162

Figu re 5-45 Socket EVENT Register ........................................................................................175

Figu re 5-46 Socket MASK Register .........................................................................................176

Figu re 5-47 Socket PRESENT STATE Register ......................................................................178

Figu re 5-48 Socket FORCE Register ........................................................................................180

Figu re 5-49 Socket CON TROL Register .................................................................................182

Figure 6-1: Op erating System Directed Power Managem ent System Architecture ........189

Figu re 6-2: Example "Or iginat ing Devices" ...........................................................................190

Figure 6-3: Standard PCI Configuration Space Header Type 0..........................................195

Figu re 6-4: Capabilities Linked List ........................................................................................197


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2001 PCMCIA/JEITA xix

TABLESTable 31 Card Detect and Voltage Sense Con nection s.........................................................10

Table 4-1: 16-bit PC Card Pin 1 To Pin 34 Assign ments ........................................................14

Table 4-2: 16-bit PC Card Pin 35 To Pin 68 Assignm ents ......................................................15

Table 4-3: Featu res of 16-bit PC Card Asyn chronou s Interface............................................16

Table 4-4: IREQ# Interru pt Signals ...........................................................................................22

Table 4-5: Vcc at Initial Power-Up and CIS Read ...................................................................27

Table 4-6: Com mon Mem ory Read Fu nction ..........................................................................29

Table 4-7: Com mon Mem ory Write Function .........................................................................29

Table 4-8: Attribute Memory Read Function...........................................................................30

Table 4-9: Attribute Memory Write Function..........................................................................30Table 4-10: Write Protect Fu nct ion ............................................................................................31

Table 4-11: Common Memory Read Timing Specification for all Types o f Memor y ........32

Table 4-12: Comm on and Attribu te Memory Write Timing Specifications ........................33

Table 4-13: Attribute Memory Read Timing Specification for all typ es of Mem ory .........34

Table 4-14: DC Specification for 5.0 V Sign aling.....................................................................37

Table 4-15: DC Specification for 3.3 V Sign aling.....................................................................37

Table 4-16: Electr ical Interface ...................................................................................................38

Table 4-17: Battery Voltage Detect ............................................................................................41

Table 4-18: Pow er-u p/ Pow er-d own Timing ...........................................................................42

Table 4-19: I/ O Inp ut Fun ction for All Cards .........................................................................45

Table 4-20: I/ O Ou tp ut Fun ction for I/ O Cards.....................................................................45

Table 4-21: I/ O Read(Input ) Timing Specification for All I/ O Cards .................................47

Table 4-22: I/ O Write(Outpu t) Timing Specification for All I/ O Card s .............................49

Table 4-23: Funct ion Con figu ra tion Registers .........................................................................50

Table 4-24: Card Memory Spaces ..............................................................................................51

Table 4-25: Funct ion Con figu ra tion Registers .........................................................................52

Table 4-26: Con figura tion Option Register ..............................................................................53

Table 4-27: Con figura tion and Sta tu s Register ........................................................................55

Table 4-28: Pin Replacem ent Register ...............................