patterning challenges for n7 and beyond at a crossroads · 2018-06-11 · 1 patterning challenges...
TRANSCRIPT
1
Patterning Challenges for N7 and Beyond At a Crossroads
Steven Scheer Director, Corporate Development Division
TOKYO ELECTRON LIMITED
Advanced Technologies in Accelerating Digital Era and IoT Forum Friday, September 4, 2015
Room 401, TWTC Nangang Exhibition Hall, Taipei
2
Analytics
Enhancement
Different Drivers – Continuous Growth
Source: IHS Q2 2015
Mobile Computing
1981, IBM PC MS-DOS
Sensing
2001 - 3G Cellphones
2007 - iPhone
2010 - iPad
2002 - Cellphones w/ camera
0
50
100
150
200
250
300
350
400
450
1976 1981 1986 1991 1996 2001 2006 2011 2016
B USD
3
More Moore
Functional Diversification
CMO
S Sc
alin
g
New Material New Structure
Advanced Packaging (3DI / WLP)
Heterogeneous
3DI
Strained Si
High-k Metal Gate
Cu/ULK
FinFET
Patterning
ArF
ArF-Immersion
EUV
More than Moore
DP/MP
NIL, EBDW
Flip-Chip 2.5D
Wire-Bonding
Si Photonics
Homogeneous
DRAM
NAND
STT-MRAM
3D NAND
ReRAM
Emerging Memory
DSA
Now
2017~
Source: Tokyo Electron Limited (based on ITRS)
Nanowire FET Cu/ELK
Technology Roadmap: Continuous Innovation
KrF
4
DRAM
Patterning Destination Set by Device Technology
Logic 3D NAND
SEM Image : TEL AR > 50
Jae-woo Im et al., ISSCC, 201
22nm (FinFET RMG) C. Auth, et al.,
VLSI tech. 2012
SADP + Cut (x1 – 2)
FinFET STI
Planar STI
193 Dry Exposure PMOS T. Ghani, et al.,
IEDM 2003
R. Coquand et al., VLSI tech. 2013
SAQP + Cut (x2 – 3)
Nanowire STI
5
Multiple Patterning
Patterning Paths Which to Choose?
Pitch Scalability
Production Ready
Edge Placement Error (EPE)
Process Complexity
DSA
Low CapEx
Materials Enabled Shrink
Self Alignment Defect
Design Flexibility
EUV
High CapEx
Tool Productivity
Process Simplicity
Design Flexibility
Source: IMEC 2015
6
Patterning at a Crossroads
7
Gate Fin Metal
Patterning Superhighway Immersion Multiple Patterning
8
Immersion Multiple Patterning Process
Key Patterning Technology
Critical Process
Step
Pre Pattern
193i Single Patterning
Litho
Material Process
LER Reduction
CDU Control
Deposition
Etch
SAMP (DP, QP, OP)
Grid Formation
LER Reduction
CDU Control
Spacer Selectivity
Litho (193i, EUV)
Planarization
Etch
LEx Multiple Patterning
Cut Pattern
Hole Shrink
Pattern Healing
Variation Control
Line Cut
Pattern Memorization
Etch
Deposition
Self Alignment
Pattern Reversal
HM Selectivity
LER Reduction
CDU Control
Spacer Selectivity
Hole Shrink
Pattern Healing
Variation Control
9
SADP Performance Enhancements
DCS cured (Enhanced Smoothing)
SiARC
TiO Spacer (Improved Selectivity)
SiO2
Photo Resist TiO
Direct Current Superposition (DCS)
Technology
H* Ar+ EB
Si Si Si
PR Curing
Si Coating
DCS & Metal Oxide Spacer Grid Pattern Formation
10
Spacer Depo Spacer RIE Middle Layer RIE Bottom Layer RIE
Higher RIE Selectivity
Improved Image Transfer
Improved LER & Resist Profile
22nm hp 44nm hp
No recess on Middle Layer
DCS applied
Photo Resist
Ox spacer
TiO spacer
Low temperature TiO and DCS process enable improved SADP process
Grid Pattern Formation DCS & Metal Oxide Spacer
11
Cut Pattern Formation
For Via, Contact 63nm 63nm
63nm
63nm
14nmΦ
66.1nm 19.9nm 19.8nm
11.8LS
Hole shrink Hole multiplication
20.0LS
41.9nm 17.5nm 18.7nm Trench shrink for cutmask
193i For Fin, Gate
Healing & Shrinking
12
63nm 63nm
63nm
63nm
14nmΦ
SiARC etch SOC etch Oxide etch Ashing Min 63nm pitch in immersion
PR SiARC
SOC TEOS
Cut Pattern Formation
In-situ polymer deposition thru-etching
Healing & Shrinking
13
-8-6-4-202468
-8 -6 -4 -2 0 2 4 6 8
Plac
emen
t err
or Y
(nm
)
Placement error X (nm)
CDU: 80% improved CER: 70% improved
Hole CD Healing Placement Error ADI
Keep Placement Error
-8-6-4-202468
-8 -6 -4 -2 0 2 4 6 8
Plac
emen
t err
or Y
(nm
)
Placement error X (nm)
AEI
Design based
Process Window
0
5
10
15
20
25
0 50 100
EL (%
)
DOF (nm)
ADI (49.3nm±10%)AEI (31.2m±10%)
EL: 60% enlarged DOF: 34% enlarged
TEL healing & shrinking improves overall process variability
0
1
2
3
4
5
6
101520253035404550556065
CER
(nm
)
hole CD(nm)
CDU 15.5nm (3sig)
CER
3.6
nm
3.4nm
1.4n
m
Nominal dose best focus
Under dose defocus
Cut Pattern Formation
*CER: Circle Edge Roughness
Healing & Shrinking
14
\ EUV Patterning Waiting for the Light
15
Resolution and LER improvement achieved using surfactant rinse FIRM® Extreme™ A
Process Condition Exposure tool: NXE3100 Resist: ESR1 Process: 2.38% TMAH DIW rinse Surfactant rinse
Pattern Size 22nm Half pitch (Top-Down SEM Image)
DIW (ref.) FIRM® ExtremeTM FIRM® ExtremeTM A
Process Window Count
Resolution Limit (nm)
Sensitivity at 22nm (mJ/cm2)
LWR at 22nm (nm)
18
22
13.9
6.4
21
20
14.3
6.2
21
19
13.9
5.7
Pattern Collapse Mitigation at 22nm HP
FIRM® Extreme is a trademark of Merck Performance Materials
16
Pre- smoothing
Post- smoothing
TEL vapor phase smoothing process can improve LWR and CER
CLEAN TRACK™ LWR & CER Improvement
10.3% Improved 11.8% Improved 13.5% Improved 11.3% Improved 13.8% Improved TEL – Jun Sung Chun / SEMATECH et. al, SPIE2014
LWR 5.20nm
LWR 4.66nm LWR 3.90nm LWR 4.74nm LWR 6.23nm CER 1.59nm
70nm pitch/ line and space
64nm pitch/ line and space
56nm pitch/ line and space
44nm pitch/ line and space
64nm pitch/ contact hole
CER 1.84nm LWR 7.03nm LWR 5.48nm LWR 4.42nm
17
Etch Hardening & LER Improvement
Post Litho Post Etch No Cure w/Cure
~ 20-30% improvement in roughness for optimized cure process as compared to non-cure
13.5nm EUV Resist Base
VUV cure can modify chemical structure of EUV resist leading
to smoothing
FTIR Data for cured & un-cured resist
LER 1.8nm
LER 2.5nm
CD 37nm
LER 2.2nm
CD 38nm
LER 2.9nm
CD 52nm CD 63nm CD 53nm
LER 3.5nm
LER 2.9nm
CD 29nm
18
DSA Patterning
Self-Aligned L/S Pitch Multiplication
Self-Aligned Hole Pitch Multiplication Simple Pitch
Multiplication with CDU/LWR
Self-Healing
Order From Chaos
19
DSA Hole Shrink Process Flow
Hole Guide BCP Coat & Bake PMMA Wet Dev. Affinity Control
Negative tone resist pattern
Wet development removes PMMA core
Affinity control processes to change template surface properties
20
Champion Hole Defectivity – 2015
1.00
0.67
0.14 0.014 0.008 Q1/13 Q2/13 Q4/13 Q1/14 Q3/14
Nor
mal
ized
Def
ect D
ensi
ty
Missing Hole 27%
DSA Failure
9%
Others 39%
On Material 25%
Missing Hole
Large Material
Small Material Embedded DSA Failure Line
Signature Others
CLEAN TRACK™ LITHIUS Pro™ Z DSA
21
Position
CD-SEM
Square scan
300K
X-SEM
CD: 21.5nm LWR: 1.84nm LER: 1.79nm
CD: 21.6nm LWR: 2.11nm LER: 1.98nm
CD: 21.9nm LWR: 1.94nm LER: 2.07nm
SiARC remain: 15.5nm
Btm CD: 23.5nm
SiARC remain: 20.9nm
Btm CD: 25.1nm
SiARC remain: 13.7nm
Btm CD: 24.3nm
DSA Etch Overall Process Optimization
Simultaneous optimization of CDU, LER, and selectivity achieved
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0 200 400 600 800
Sele
ctiv
ity
LER
, LW
R [n
m]
HF Source Power [W]
Effect of HF RF Power LER LWR Selectivity
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0 100.0 200.0 300.0
Sele
ctiv
ity
LER
, LW
R [n
m]
Vpp [V]
Effect of Ion Energy LER LWR Selectivity
Center Right Middle Right Edge
22
Crossroads or Converging Paths?
23
Summary
New drivers for increased computing power and storage continue to demand new semiconductor technologies
Traditional scaling is at an inflection point, requiring new innovation to enable cost effective patterning solutions
Developing these innovations requires partnership between customers, consortia, and suppliers
TEL is ready to support all patterning technologies…
25
Semiconductor companies’ collaborations Consortia (EIDEC, IMEC, SEMATECH) Material suppliers (Merck, TOK) Equipment suppliers (ASML, HHT, KLA-Tencor) TEL global technology teams (PSP, TDC, ATG, TTCA)
Co-authors Hidetami Yaegashi Kenichi Oyama Takashi Hayakawa Takahiro Kitano Makoto Muramatsu Kousuke Yoshihara Satoru Shimura Shinichiro Kawakami Toshikatsu Tobana
Mark Somervell Carlos Fonseca Ben Rathsack Anton deVilliers Serge Biesmans Omar Madrigal Samuel House Rob Crowell
Nagisa Sato Ken Nawa Koichi Yatsuda Seiji Fujimoto Noritaka Yokomori Hideo Nakashima Seiji Nagahara Hiroyuki Iwaki Akihiro Sonoda
Acknowledgements
TEL is a trademark of Tokyo Electron Limited.