paratek - bst tunable rf capacitor on semiconductor tcp-3027 teardown reverse costing report...
DESCRIPTION
Manufactured and sold by ON Semiconductor and based on a Paratek technology the TCP-3027 is a tunable RF capacitor of 2.7pF. The tunable RF capacitor has a better quality factor (Q) than the standard varactor diode. The TCP-3027 is a passive tunable integrated capacitor (PTIC) packaged in a WLCSP measuring 0.87 x 0.71mm. The tunability is due to the material called ParaScan™ by Paratek. A Barium Strontium Titanate (BST) doped ceramic is used as a dielectric in the capacitor. The ferroelectric characteristics of the ParaScan™ allows a large variation of the electric constant. Paratek has developed a specific capacitor structure and a DC bias compensation to reduce the parasitic acoustic wave. This reverse costing report provides an estimation of the production cost of the TCP-3027. It describes the overall manufacturing process and highlights key points of innovation developed by Paratek and ON Semiconductor and a comparison between the products of STMicroelectronics and ON Semiconductor manufactured from Paratek’s license . More information on that report at http://www.i-micronews.com/mems-sensors-report/product/paratek-bst-tunable-rf-capacitor-on-semiconductor-tcp-3027.htmlTRANSCRIPT
DISCLAIMER : System Plus Consulting provides cost studies based on its knowledge of the manufacturing and selling prices of electronic components and systems. The given values are realistic estimates which do not bind System Plus Consulting nor the manufacturers quoted in the report. System Plus Consulting is in no case responsible for the consequences related to the use which is made of the contents of this report. The quoted trademarks are property of their owners.
© 2014 by SYSTEM PLUS CONSULTING, all rights reserved. 1
Electronic Costing & Technology Experts
www.systemplus.fr21 rue la Nouë Bras de Fer44200 Nantes – France Phone : +33 (0) 240 180 916 email : [email protected]
June 2014 – Version 1 – Written by Sylvain Hallereau
ON Semiconductor PTIC - Tunable Capacitor
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Glossary1. Overview / Introduction 4
– Executive Summary
– Reverse Costing Methodology
2. Company Profile 8– ON Semiconductor
3. Blackberry Z10 Teardown 14
4. Physical Analysis 17– Synthesis of the Physical Analysis
– Physical Analysis Methodology
– Package 19
– Package Views & Dimensions
– Package Opening
– Copper Pillar
– PTIC Die 26
– View & Dimensions
– Marking
– Bond Pads
– Capacitor Structure
– Delayering
– Polysilicon traces
– Cross-Sections
– Patents
– Physical Dimensions
– STMicroelectronics STPTIC
5. Manufacturing Process Flow 60– Global Overview
– PTIC Process Flow
– PTIC Wafer Fabrication Unit
– Packaging Process Flow
– Package Assembly Unit
6. Cost Analysis 68– Synthesis of the cost analysis
– Main steps of economic analysis
– Yields Hypotheses
– PTIC Front-End Cost
– PTIC Back-End 0 : Probe Test & Dicing
– PTIC Front-End Cost per process steps
– PTIC Front-End: Equipment Cost per Family
– PTIC Front-End: Material Cost per Family
– PTIC Wafer Cost
– PTIC – Copper Pillar
– PTIC – PROBE and Dicing Cost
– Back-End : Final Test Cost
– PTIC Component Cost & Price
Contact 85
ON Semiconductor PTIC - Tunable Capacitor
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The reverse costing analysis is conducted in 3 phases:
Teardown analysis
• Package is analyzed and measured• The dies are extracted in order to get overall data: dimensions, main blocks, pad number and pin out, die marking• Setup of the manufacturing process.
Costing analysis
• Setup of the manufacturing environment• Cost simulation of the process steps
Selling price analysis
• Supply chain analysis• Analysis of the selling price
ON Semiconductor PTIC - Tunable Capacitor
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• Package: WLCSP 8 pillar
• Dimensions: 0.874 x 0.716 x 0.54mm
Package top view
Package Side View
0.716mm0.XXmm
0.874mmSolder
ON Semiconductor PTIC - Tunable Capacitor
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• The die marking includes:
P
2.7 (probably capacitor of 2.7pF)
X527
Die Marking
ON Semiconductor PTIC - Tunable Capacitor
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Capacitor stacking – Optical view
Top electrode
Top BST dielectric layer
Bottom BST dielectric layer
Capacitor line
Top electrode widt: XXµm
BST width: XXµm
Bottom electrode width: XXµm
Pitch: XXµm
Interconnection between the capacitor lines
ON Semiconductor PTIC - Tunable Capacitor
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Contact with medium and top electrodes after passivation etching –SEM view
Contact with medium and top electrodes after passivation etching –SEM view
ON Semiconductor PTIC - Tunable Capacitor
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TPIC cross-section– Optical View
ON Semiconductor PTIC - Tunable Capacitor
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Tunable capacitor
•Oxide 1 Deposition
•Polysilicon trace pattern
•Oxide 2 deposition and pattern
•CMP
Tunable capacitor
•XX
Tunable capacitor
•XXX
PolysiliconOxide 2
Oxide 1
Al2O3 substrate
ON Semiconductor PTIC - Tunable Capacitor
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ON Semiconductor PTIC - Tunable Capacitor
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© 2014 by SYSTEM PLUS CONSULTING, all rights reserved. 11Manufacturing Steps Cost (Simulated with MEMS CoSim+ Cost Simulation Tool)
ON Semiconductor PTIC - Tunable Capacitor
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Reverse costing analysis represents the best cost/price evaluation given the publically available data, and estimates completed by industry experts.
Given the hypothesis presented in this analysis, the major sources of correction would lead to a +/- 10% correction on the manufacturing cost (if all parameters are cumulated)
These results are open for discussion. We can reevaluate this circuit with your information. Please contact us:
Europe & USA Office
• Yole Développement Headquarter, France: David Jourdan, Sales Coordination & Customer Service, Tel: +33 472 83 01 90, Email: [email protected]
Japan Office• For custom research: Yutaka Katano, General Manager, Yole Japan & President, Yole K.K.Phone: (81) 362 693 457 - Cell : (81) 80 3440 6466 - Fax: (81) 362 693 448 - Email: [email protected]• For reports business: Takashi Onozawa, Sales Asia & General Manager, Yole K.K.
Email: [email protected]
Korea Office • Hailey Yang, Business Development Manager, Phone : (82) 2 2010 883 - Cell: (82) 10 4097 5810
- Fax: (82) 2 2010 8899 – Email: [email protected]