PAUL D. FRANZON

I. BRIEF RESUME

A. Resume

(i) Education (Degrees, Dates, Institutions, Locations

� Doctor of Philosophy, Electrical and Electronic Engineering: 1989, University of

Adelaide, Australia. Advisor: Kamran Eshraghian.

� Bachelor of Engineering with First Class Honours, Electrical and Electronic En-

gineering: 1984, University of Adelaide, Australia.

� Bachelor of Science, Physics and Mathematics: 1983, University of Adelaide,

Australia.

(ii) Professional Experience (Titles, Organizations, Locations, Dates of Employment

� Assistant Professor, Associate Professor, and Professor, North Carolina State

University, Department of Electrical and Computer Engineering, Raleigh, North

Carolina, January 1989 - present.

� PhD Candidate, University of Adelaide, Department of Electrical and Electronic

Engineering, Adelaide, South Australia, Australia, April 1987 { December 1988.

� Director and Co-Founder, Network Communications Pty. Ltd., Adelaide, South

Australia, Australia, April 1987 { April 1989.

� Consultant, AT&T Bell Laboratories, Holmdel NJ, January 1986 { April 1987.

� PhD Candidate, University of Adelaide, Department of Electrical and Electronic

Engineering, Adelaide, South Australia, Australia, August 1984{December 1985.

� Engineer, Defence Science and Technology Organization, Salisbury, South Aus-

tralia, Australia, January 1984{July 1984.

� Intern, Defence Science and Technology Organization, Salisbury, South Australia,

Australia, December 1982{March 1983.

� Intern, Telecom Australia, Adelaide, South Australia, Australia, December 1981{

March 1982.

� Infantry Soldier and O�cer, (Ranks held: Private { Captain), Royal Australian

Infantry Corps, Australian Army Reserve, December 1979 { December 1991.

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(iii) Scholarly and Professional Honors

� First round prize winner, SRC copper challenge, 2000.

� Teacher of the Year Award, presented by the IEEE Student Branch, 1997.

� National Science Foundation Young Investigator's Award, 1993

� Invited Paper, Asia DAC, 1999.

� Invited Paper, ASIC 96, 1996.

� Invited paper, Brazilian Microelectronics Conference, 1996.

� Invited paper, Australian Microelectronics Conference, 1995.

� The John L Young Scholarship for Research

� The Hartley Studentship

� The Mabel Tapp Prize

� The EV Clarke Prize for Electrical Engineering

� The Chamber of Commerce and Industry Prize

� The CFV Clarke Scholarship

� The Electricity Trust Prize (shared)

� The Phillips Prize for Electronics (shared)

� The Sir Robert Chapman Prize for Engineering I

� IBM Maths Competition Prize

� BHP Prize for School Leavers

� Way College Prize for Chemistry

� The Royal Australian Chemical Institute Prize

(iv) Professional Licenses, Prof. Society Memberships, and Consulting Activities

� Senior Member, Institute of Electrical and Electronic Engineers (IEEE)

� IEEE Computer Society (CS)

� IEEE Circuits and Systems Society (CAS)

� IEEE Society for Components, Packaging andManufacturingTechnology (CPMT)

� Association for Computing Machinery (ACM)

� ACM Special Interest Group in Design Automation (SIGDA)

� Consultant to MCNC, 1989. Determined Cadence skill routines for IC yield esti-

mation.

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� Consultant to Techsearch International, 1989-1991. Designed and wrote technical

reports on industry status and insertion of MCM technology. Developed new line

of business.

� Consultant to Bell Northern Research, 1992. Interconnect design.

� Consultant to Hewlett Packard, 1992. Interconnect design.

� Consultant to Sun Microsystems, 1994, 1996. Interconnect design.

� Consultant to DCT, 1995-1996. Designed DMA unit and architected an MPEG-2

chip.

� Consultant to Cadence Design Systems, 1992, 1996. Technical advisory board for

Physical Design.

� Consultant to Mentor Graphics, 1995, 1996. Technical advisory board for Kitty-

hawk project.

� Consultant to Square-D, 1996. Interconnect Design.

� Consultant to Polychip, 1994-2000. Driver/receiver circuit design for high speed

signalling.

� Consultant to Cadence, 1996. Evaluated possible company aquisition.

� Consultant to Accelerated CAD Inc., 1997. Architected hardware for CAD accel-

eration.

� Consultant to Ericson, 1997, Synthesis Methodology.

� Consultant to O'Malveny and Meyers, 2000, Patent issues.

� Consultant to Venture 2000, 2000, Due Diligance.

� Consultant to CAPPS, 1999-2000, IP Development.

� Consultant to Sofrent, 1999-2000, IP Development.

B. Summary - Dean's or Department Head's Narrative Summary of Recom-mendations

II. INSTRUCTIONAL CONTRIBUTIONS WITH EVALUATIONS

A. Teaching E�ectiveness. List courses taught, with an evaluation of teaching e�ective-

ness, including a summation of data from student evaluations for the past three years

and summary of available peer evaluations.

1. ECE 342, Design of Complex Digital Systems, Fall 1999, Instructor

Overall E�ectiveness 4.5/5.0.

2. ECE 492B, Section 001, ASIC Design, Spring 2000.

3. ECE 492B, Section 002, ASIC Design, Spring 2000.

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4. ECE 520, Section 001, ASIC Design, Spring 2000.

5. ECE 520, Section 002, ASIC Design, Spring 2000.

6. ECE 342, Design of Complex Digital Systems, Fall 1999. Instructor

Rating: 4.4/5.0

7. ECE 492B, ASIC Design, Spring 1999. Instructor Rating: 4.5/5.0

8. ECE 520, ASIC Design, Spring 1999. Section 005. Instructor Rating: 4.6/5.0

9. ECE 520, ASIC Design, Spring 1999. Section 006. Instructor Rating: 4.5/5.0

10. ECE 791D, Design Advanced Embedded Processors, Spring 1999.

11. ECE 342, Design of Complex Digital Systems, Fall 1998. Instructor Rating:

4.3/5.0.

12. ECE 791A, System on a Chip, Fall 1998.

13. ECE 492B, ASIC Design, Spring 1998. Instructor Rating: 4.7/5.0

14. ECE 520, ASIC Design, Spring 1998. Instructor Rating: 4.6/5.0.

15. ECE 544, Design of Interconnect and Packaging, Spring 1998.

16. 1997: Voted `Teacher of the Year' by the IEEE Student Branch.

17. ECE 342, Design of Complex Digital Systems, Fall 1997.

18. ECE693A CPE Graduate Seminar Series, every semester.

19. ECE 520 ASIC Design, Spring 1997. Overall Teaching E�ective Rating: 4.7/5.0

20. ECE 492B ASIC Design, Spring 1997. Overall Teaching E�ective Rating: 4.7/5.0

21. ECE 544, Design of Electronic Packaging and Interconnects, Spring 1997.

22. ECE 342 Design of Complex Digital Systems, Fall 1996, Overall Rating: 4.6/5.0.

23. ECE 592B ASIC Design, Spring 1996, Overall Rating: 4.75/5.0. (With Dr. Liu.)

24. ECE 492B ASIC Design, Spring 1996, Overall Rating: 4.00/5.0. (With Dr. Liu.)

25. ECE 544, Design of Electronic Packaging and Interconnects, Spring 1996, Overall

Rating: 4.60/5.0.

26. ECE 520, Fundamentals of Logic Systems, Fall 1995, Overall Rating: 4.50/5.0.

27. ECE 218, Computer Organization and Microprocessors, Both Sections, Spring,

1995. Overall Rating: Section 001: 4.45/5.0; Section 002: 4.62/5.0.

28. ECE 592V, VLSI Microprocessor Project, Spring 1995. (13 students but not

rated).

29. ECE 681/693A, Computer Engineering Seminar. Spring 1996 and Fall 1996.

30. ECE 521 Computer Design and Technology, Fall 1994, Overall Rating: 4.24/5.0.

31. ECE 691F, High Speed VLSI, Fall 1994, Overall Rating: 4.45/5.0.

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32. ECE 691P, Superscalar Processor Design, Spring 1994, Overall Rating: 4.67/5.0.

33. ECE 591F, Design of Electronic Packaging and Interconnects, Spring 1994, Over-

all Rating: 4.60/5.0.

B. Scholarly Contributions. Include original publications on teachingmethods, reviewed

audiovisual and computer-based educational programs, grants and contracts, textbooks

and laboratory manuals.

1. D. Smith and P. Franzon, \Verilog Styles for Synthesis of Digital Sys-

tems,", Prentice Hall, 2000.

2. P. Franzon, J.T. Schae�er, A.W. Glaser, \CAD-Centric Teaching", Microelec-

tronics Systems Educator Conference, July 1999, Washington, DC.

3. Best University Web Site, Cadence University Alliance. NCSU won this prize

for having the best content on all the Cadence web sites. This content included

design kits and tutorials.

4. Co-Principal Investigator, \DesignCenter for TeachingDigitalDesign", 1 Septem-

ber, 1990 { 31 August, 1993, awarded by NSF ($500,000). I was one of the code-

velopers of the ECE Undergraduate Design Center. This grant enabled us to

develop some materials for the course and to purchase all of the equipment used

within the Center.

5. In 1990, I originated the concept of and supervised the development of an on-line

(i.e. on EOS) Motorola 68000 CPU Simulator for use within ECE 218. This

simulator was distributed to over 50 other Universities.

6. Developed a new laboratory manual for ECE 342, Design of Complex Digital

Systems, a CpE core course. This lab manual is available on-line in the ECE342

locker.

7. Updated the laboratory manual for ECE 218, Computer Organization and Mi-

croprocessors, introducing an unstructured design project.

8. Through my funded research e�orts and Corporate Donations intro-

duced the following Computer Aided Design Tools into the cirricula:

� Cadence Design Systems. A complete suite of over 4 GB of exe-

cutables that facilitate chip, board and system design, with a retail

value of over $100,000,000.

� Synopsys. The industry leading chip (ASIC) synthesis tool, with a

retail value of over $7,000,000.

� Metasoftware Hspice. The industry leading chip simulation tool,

with a retail value of over $3,000,000.

As well as obtaining these tools, my group has spent considerable ef-

fort making these tools useful to us by writing integration scripts and

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generating `know-how'. Some of this `know-how' has been published

on the Web and in our own lockers. Most of this learning was con-

ducted driven by research needs and serves as an excellent example of

the integration of research and teaching. This work is ongoing.

9. ECE CAD Lab. $75,000. Provost O�ce, 1995.

10. Co-authored and edited the book, Multichip Modules: Basics and Alternatives,

1993 by Van Nostrand Rheinhold. This book has been used in my course, and I

believe at other Universities.

C. Instructional Development Include innovations in courses and curricula.

1. Our NSF-funded CISE Infrastructure e�ort, \Experimental High Per-

formance Computing and Communications Systems", has been funded.

(Total: $1,338,283 including $503,046 in matching.) Approximately

$283,000 of this funding will go towards out�tting the ECE Design

Center.

2. CAD Tools. Modern design is done with sosphisticated Computer-

Aided Design Tools, not with pencil and paper. I have spent consider-

able e�ort bringing such tools into the EOS environment, gaining the

`corporate knowledge' about how to use thse tools e�ectively and ob-

taining additional computers (ECE CAD Lab { See II.B) for use with

these tools. Students tell me that knowledge of these tools is highly regarded by

potential employers. In fact one student stated that `Dr. Franzon teaches courses

that gets jobs'. In addition, in 1999, we won the Cadence University Alliance

Best Web site award.

3. ECE 342, Design of Complex Digital System, Fall 1996:

� Completely redesigned and updated course to re ect modern design practices,

and use of modern Hardware Description Languages and Design Tools.

� Completed a new laboratory course ECE 342L for use with this course.

4. ECE 520 ASIC Design (formerly `Fundamentals of Logic Systems'), Spring 1997:

� Based on my teaching of ECE592B in Spring 1995, this course has been

completely updated to re ect modern design practices, modern tools, and

emphasize an understanding of algorithms used in modern tools. (`ASIC'

stands for `Application Speci�c Integrated Circuit'. For example the chips in

a satellite dish receiver are ASICs. ASIC engineering is the fastest growing

area of ECE today.)

� Once the course action forms are apprved, this course will be taught concur-

rently with ECE 420 ASIC Design.

5. ECE 544, Design of Electronic Packaging and Interconnects, Spring 1995.

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� New course emphasizing `transmission line e�ects' in electronic packages and

how to design `deep sub-micron interconnect'. I receive tremendous demand

from industry for graduates from this course.

6. ECE 691/693A, Computer Engineering Graduate Seminar

� Created new seminar course (with Dr. Tom Conte) for computer engineering

students.

� Recrutied and scheduled weekly speakers.

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D. Advisory Activities Include undergraduate academic advising, graduate committees,

postdoctoral student advising, student organizations, special projects with students.

GRADUATE COMMITTEES

Student Name Degree Chairman Membe

David Nackashi PhD X

Bruce Duewer PhD X

Steve Lipa PhD X

Alan Glaser PhD X

Andrew Stanaski PhD X

Toby Scha�er PhD X (Graduated

John Wilson PhD X

David Winick PhD X

Real Pommerleau PhD (Co-chair) X

Mouna Nakkar PhD X (Graduated

Jeremy Palmer PhD X

Karthik Sehkhar MS X

Nishith Rohatigi MS X

Rolf Enzler PhD X (student at ETH,

Michael Sche�er PhD X (student at ETH,

Etienne Hirst PhD X (Graduated 2000, ET

Vinyak Parameshwara (Co-chair) MS X (Graduated

Debu Ghosh (Co-chair) PhD X (Graduated

Krutarth Mehta MS X

Chris DeMarco PhD X

Mark Clements PhD X

Sergei Larin PhD X

As I do not keep track of the committees I am on, the list of committee

memberships is inaccurate, most likely with many students left out. I am

also the advisor of over 25 MS and ME non-thesis students.

STUDENT ORGANIZATIONS

Committee Member of 1995 `Women Student Engineer of the Year Award' for the

Society of Woman Engineers.

SPECIAL PROJECTS WITH STUDENTS

I have supervised a large number of graduate and undergraduate special project courses,

especially aimed at encouraging Undergraduates to consider Graduate work.

This year, I also supervised four students working on Research Experience

for Undergraduates (REU) awards.

E. Cross-Disciplinary Activities. Include graduate program participation, special courses,

and curricular development e�orts.

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� Collaborative research programs ongoing with Materials Science and

Engineering, and the College of Textiles.

� Full Member of Graduate Faculty.

� As chair of the CpE Cirriculum committee, I established a �ve-year

BS-MSM program with the College of Management.

III. RESEARCH CONTRIBUTIONS WITH EVALUATION

A. Scholarly Achievements.

(i) Publications (original research articles and research review articles in peerreviewed

journals, research abstracts, books), invited and uninvited research presentations, ap-

pointments or election to study sections and editorial boards.

BOOKS

1. D. Smith and P. Franzon: Verilog Styles for Synthesis of Digital Systems,

2000, by Prentice Hall.

2. D. Doane and P. Franzon: Multichip Modules: Basics and Alternatives, 1993, by

Van Nostrand Rheinhold.

3. J-D Cho and P.D. Franzon, high Performance Design Automation for Multi-Chip

Modules and Packages, 1996, World Scienti�c.

BOOK CHAPTERS

1. P. Franzon,Multichip Module Technology, to appear in the The Electronic Hand-

book, J. Whitaker (editor), (CRC Press), 1996.

2. S. Mehrotra and P. Franzon, Performance Driven Global Routing and Wiring Rule

Generation for High Speed PCBs and MCMs, in Advanced Routing of Electronic

Modules, M. Pecht (editor), (Kluwer), 1995.

3. P. Franzon and Michael Steer: Tools and Techniques for the Design of High Speed

Multichip Modules, Chapter 7 in Electronics Packaging Forum, Volume 3, J. Mor-

ris (ed), 1993 by IEEE Press.

4. P. Franzon, Comparison of Recon�guration Schemes for Defect Tolerant Mesh

Arrays, in Defect and Fault Tolerance in VLSI Systems, Volume 2, V.K. Jain

(editor), (Plenum), 1989.

5. M. Hatamian, L.A. Hornak, T. Little, S.K. Tewksbury and P. Franzon: Fun-

damental interconnection issues in, Electronic Materials Handbook, Volume 1:

Packaging, Article 1BA (ASM International), 1989, pages 1{11.

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6. P. Franzon and S.K. Tewksbury: `Chip Frame' scheme for recon�gurable mesh-

connected arrays, in Wafer Scale Integration II, R.M. Lea (editor), (North Hol-

land), 1988.

7. P.D. Franzon: Yield Modeling for Fault Tolerant VLSI, in Systolic Arrays, W.

Moore, A. McCabe and R. Urquhart (editors), (Adam Hilger), 1987.

JOURNAL PAPERS

1. Etienne Hirt, Paul Franzon, Gerhard Troster, \New Substrate Size

and Layer Estimation for Multi Chip Modules and Printe d Circuit

Boards", accepted by IEEE Trans. CPMT.

2. T. Usher, J. Manning, D. Dessent, J.A. Palmer, P. Franzon, E. Grant,

and A. Kingon, \Load characterization of high displacement pizeoelec-

tric actuators with various end conditions", submitted to IEEE Trans-

ducers and Actuators.

3. M. Nakkar, A.W. Glaser, P. Franzon, K. Williams, M. Roberson, G.

Rinne, \Three Dimensional MCM Package Assembly and Analysis,"

submitted to IEEE Transacations on Compoents, Packaging, and Man-

ufacturing Technology.

4. J.T. Scha�er, A. Glaser, S. Lipa, and P. Franzon, \7.6 Gbps Triple

DES Unit With In-Package Power Ground and Clock Distribution,"

submitted to Journal of Solid State Circuits.

5. D. Winick, B. Duewer, and P. Franzon, \Reduced overhead control

scheme for MEMS arrays," in preparation for submission to IEEE Jour-

nal on MEMS.

6. M. Nakkar, J. Harding, D. Schwartz, P. Franzon, C. Gloster, T. Conte,

\Dynamically Programmable Cache Machine with Low Power FPGA

Fabric", in preparation for submission to IEEE Transactions on VLSI.

7. M. Nakkar, P. Franzon, \Achieving low power through data reorgani-

zation," in preparation for submission to IEEE Transactions VLSI.

8. Mir Azam, Paul Franzon and Wentai Liu, \Signal Alignment to Reduce

Glitches," in preparation for submission to he Journal of Solid State

Circuits.

9. H.L. Lo, J.F. Kau�mann and P.D. Franzon, \High frequency loss and electro-

magnetic �eld distribution for striplines and microstrips", IEEE Transactions on

Components, Packaging and Manufacturing Technology, Part B., Advanced Pack-

aging, Vol. 22, No. 1, pp. 16-25, Jan. 1999.

10. S.F. Al-sarawi, D. Abbott, and P. Franzon, \A review of 3D Packaging Technol-

ogy", IEEE Transactions on Components, Packaging and Manufacturing Tech-

nology, Feb. 1998, Vol. 21, No. 1, pp.2-14.

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11. H.Y. Hseih, W. Liu, P. Franzon and R. Cavin III, \Clocking Optimization and

Distribution of Digital Systems with Scheduled Skews", International Journal of

VLSI Signal Processing, April 1997, Vol. 16., pp.19-36.

12. P. Franzon, Andrew Stanaski, Yusuf Tekmen, Sanjeev Banerjia, \System Design

Optimization for MCM-D/Flip-Chip", IEEE Trans. on Components Packaging

and Manufacturing Technology, Part B, Vol. 18, No. 4, pp. 620-627.

13. S. Lipa, M.B. Steer, A.C. Cangellaris and P.D. Franzon, \Experimental Charac-

terization of Transmission Lines in Thin-Film Multichip Modules," IEEE Trans.

on Components Hybrids and Manufacturing Technology, Part A, Vol. 19, No. 1,

Feb. 1996, pp. 74-82.

14. R.J. Evans and P.D. Franzon, Energy consumption modeling and optimization for

SRAMs, IEEE Journal of Solid State Circuits, Vol. 30, no. 5, May 1995, pp.

571-579.

15. S. Mehrotra, Y. Tekmen, P. Franzon, and W. Liu, Stochastic Optimization Ap-

proach to Component Sizing for High Performance Circuits, Submitted for publi-

cation to IEEE Transactions on Computer-Aided Design.

16. S. Washabaugh, P.D. Franzon and H.T. Nagle, SABSA: Switching-Activity Based

State Assignment, International Journal of High Speed Electronics and Systems,

Vol. 5, No. 2 (1994), 203-212.

17. M.S. Basel, M.B. Steer and P.D. Franzon \Simulation of High Speed Interconnects

Using a Hierarchical Packaging Simulator," IEEE Trans. on Components Hybrids

and Manufacturing Technology/Advanced Packaging.

18. Slobodan Simovich, Sharad Mehrotra, Paul Franzon and Michael Steer, Delay

and Re ection Noise Macromodeling for Signal Integrity Management of PCBs

and MCMs, in IEEE Trans. CPMT, Part B: Advanced Packaging, vol. 17, no. 1,

Feb., 1994, pp. 15-21.

19. D. Doane and P. Franzon, The Case for MCMs, in Semiconductor International,

April 1994, pp. 85{86.

20. S. Simovich, P.D. Franzon and M.B. Steer, Method for automated waveform anal-

ysis of transient in digital circuits, Electronics Letters, 15th April 1993, Vol. 29,

No. 8, pp. 681{693.

21. S. Lipa, M.B. Steer, A.S. Morris and P.D. Franzon, Comparison of methods for

determining the capacitance of planar transmission lines with with application

to multichip module characterization, IEEE Trans. on Components Hybrids and

Manufacturing Technology/Advanced Packaging, May 1993.

22. S. Ma and P. Franzon: Energy Control in CMOS Bu�ers, IEEE Journal of Solid

State Circuits, Vol. 29, No. 9, September 1994, pp. 1150{1153.

23. P. Franzon, and R. Evans, An MCM Design Process with Application to a Laptop

Computer Design, April 1993, Vol. 26, No. 4, pp. 41{49, IEEE Computer

Magazine.

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24. A. Dalal, M. Lorenzetti, and P. Franzon, A Layout-Driven Yield Predictor and

Fault Generator for VLSI, IEEE Trans. Semi. Manu., February 1993 (Vol. 6,

No. 1), pp. 77-82.

25. M.B. Steer, S.B. Goldberg and P.D. Franzon, \Comment on an accurate measure-

ment technique for line properties, junction e�ects and dielectric and magnetic

parameters," IEEE Trans. Microwave Theory Tech., February 1992.

26. Steven B. Goldberg, Michael B. Steer, Paul D. Franzon, and Je�rey S. Kast

en Experimental electrical characterization of interconnects and discontinuities in

high speed digital systems, IEEE Trans. CHMT, Vol. 14, No. 4, December 1991.

pp. 761-765.

27. D. Van den Bout, P. Franzon, J. Paulos, T. Miller III, W. Snyder, T. Nagle and

W. Liu: Scalable VLSI implementations for neural networks, Journal of VLSI

Signal Processing, Volume 1, pp. 367-385, April, 1990.

28. P. Franzon: Modeling interconnect yield in recon�gurable circuits, Electronics

Letters, Volume 25, Number 18, pages 1225{1226, 31 August 1989.

29. P. Franzon and K. Eshraghian: Achieving ULSI through defect tolerance, in the

Int. J. of Computer Aided VLSI Design, Volume 1, Number 1, 1989, pages 73{90.

30. M. Hatamian, L.A. Hornak, T. Little, S.K. Tewksbury and P. Franzon: Fun-

damental interconnection issues, AT&T Technical Journal, July/August 1987,

Volume 66, Issue 4, pages 13 { 30.

31. S.K. Tewksbury, M. Hatamian, P. Franzon, L.A. Hornak, C.A. Siller, Jr., and V.B.

Lawrence: FIR �lters for high sample rate applications, IEEE Communications,

Vol. 25, July 1987, pp. 62-72.

PEER REFEREED CONFERENCE PUBLICATIONS

1. P.D. Franzon, B. Duewer, J. Wilson and D.A. Winick, "Programmable

MEMS Capacitor Arrays", in Proc. SPIE Int. Symposium on Micro-

electronics and Micromechanical Systems, November, 1999.

2. R. Pomerleau, G. Bilbro, and P. Franzon, \Improved delay prediction

for on-chip buses," Proceedings 1999 Design Automation Conference

(Cat. No. 99CH36361). IEEE, Piscataway, NJ, USA; 1999; xxxii+1003

pp. p.497-501.

3. P. Franzon, \Accuracy Issues in Full-Chip Extraction", Panel Session

Chair and Organizer, DAC 1999.

4. P.D. Franzon, W. Lui, C. Gloster-C, T. Scha�er, A. Glaser, and A.

Stanaski, "Infrastructure and course progression for complex IC de-

sign education," in Proceedings 1999 IEEE International Conference

on Microelectronic Systems Education (MSE'99) `Systems Education

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in the 21st Century' (Cat. No.99-63794). IEEE Comput. Soc, Los

Alamitos, CA, USA; 1999; x+104 pp. p.88-9.

5. Bruce Duewer, DavidWinick, JohnWilson, Jeremy Palmer, Paul Franzon "Method-

ology for Design of Electrostatic MEMS Devices Using the SUMMiT Process",

Proceedings of the 45th International Instrumentation Symposium, Albequerue,

NM, May 1999, p511-520.

6. M. Nakkar, A.W. Glaser, P. Franzon, K. Williams,M. Roberson, G. Rinne, \Three

Dimensional MCM Package Assembly and Analysis," in Proc. IEEE/IMAPS

Conference on High Density Packaging and MCMS, Denver, CO., May 1999, pp.

188-192.

7. B.E. Duewer, J.M. Wilson, D.A. Winick, P. Franzon, \MEMS-based switches for

Digital and RF Switching," in Proc. Advanced Research in VLSI, Atlanta GA,

April 1999, pp.369-377.

8. Mouna Nakkar, Paul Franzon, John Harding, and David Schwartz, \Dynamically

Programmable Cache, Evaluation and Virtualization" in Proc. ACM/SIGDA

FPGA 99, Feb. 1999, Monterey, CA, pp. 246.

9. Paul Franzon, \Design Automation and Design Challenges for Package/Systems,"

Invited paper, in Proc. IEEE Asia Design Automation Conference, Hong Kong,

Jan. 1999, pp.372-.

10. T. Scha�er, A. Stanaski, A. Glaser, P. Franzon, "The NCSU Design Kit for IC

Fabrication Through MOSIS,", Proc. 1998 International Cadence User Group

Conference, Sept. 13-17, 1998, pp. 71-80. Won best paper award.

11. Mouna Nakkar, David G.Bentlage, John Harding, David Schwartz, Paul Franzon,

and Thomas Conte, \Dynamically Programmable Cache," in Proc. SPIE Confer-

ence on Recon�gurable Computing, October, 1998, Boston MA, pp. 218-226.

12. S. Lipa, A.W. Glaser, P.D. Franzon, "Flip-chip Power Distribution", in Proc.

Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting

on , Page(s): 39 -41

13. M.Azam, R. Evans, and P.D. Franzon, \Power Reduction by low activity datapath

design and SRAM energy models", in Proc. Workshop on Low Power Techniques,

ISCA98, July 1998.

14. H-Y Hsieh, W. Lui, M. Clements, P. Franzon, \Self-calibrating clock distribution

with scheduled skews," in Proc. ISCAS '98, Volume: 2 , Page(s): 470 -473 vol.2

15. S.P. Chaudhury and P.D. Franzon, \Accurate Lumped-Parameter modeling for

dynamic simulation of electrostaticMEMS Actuators", Proc. InternationalWork-

shop on Modeling of MEMS Systems, April 1998.

16. J.T. Scha�er, S.Lipa, A. Glaser, P. Franzon, \Issues in Chip-Package Codesign

with MCM-D/Flip-Chip Technology", Proc. IEEE International Symposium on

Chip-Package Codesign, Feb. 1998, pp 88-92.

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17. D. Winick, B. Duewer, S. Chaudry, J. Wilson, J. Ticker, U. Eksi and P. Franzon,

\MEMS-based di�ractive optical beam steering system", Proceedings SPIE, Vol

3276, pp. 81-87, February, 1998.

18. McClellan, K.J., Jr.; Wailes, T.S.; Franzon, P.D, \An accurate, computationally

e�cient crosstalk model for routing high-speed MCMs," in Proc. ASIC Confer-

ence and Exhibit, 1997, Page(s): 110 -114

19. K.J. McClellan, T.S. Wailes, and P.D. Franzon, \Simulation vs. Calculation of

Crosstalk", Proc. IEEE Topical Meeting on Electrical Performance of Electronic

Packaging, Oct. 1997, pp.131-134.

20. Baribrata Biswas, Allen Glasser, Steven Lipa, Michael Steer, Paul Franzon, Di-

eter Gri�s, Phillip Russell, \Experimental Electrical Characterization of On-Chip

Interconnects", accpeted by the IEEE Topical Meeting on Electrical Performance

of Electronic Packaging, Oct. 1997, pp. 57-59.

21. A.W. Glaser, M. Nakkar, P.D. Franzon, T.M. Conte G. Rinne, M. Roberson, V.

Rogers, C.K. Williams, \A Low-cost, High Performance Three-DimensionalMem-

ory Module", in Proc. IEEE Memory Technology, Design and Testing Workshop,

August 1997.

22. Mouna Nakkar, Paul Franzon, A.W. Glaser, V Rogers, K.C. Willimas, and Glenn

Rinne, \Thermal/mechanical analysis and design of three dimensional high den-

sity MCM package", in Proc. Next Generation Package Design Workshop, June

11 1997.

23. M. Azam, P. Franzon, T. Conte, \Low Power Data Processing by Elimination

of Redundant Computations", in Proc. 1997 International Symposium on Low

Power Electronics and Design, Aug 18{20th, Monterey, California, pp.259-264.

24. Glaser, A.; Nakkar, M.; Franzon, P.; Rinne, G.; Roberson, M.; Rogers, V.;

Williams, C.K.; \A low cost, high performance three-dimensional memory mod-

ule", Proc. Int. Workshop Memory Technology, Design and Testing, 1997.

Page(s): 2 -7.

25. D.A. Winick, B.E. Duewer, S. Palchaudhury and P.D. Franzon, \Performance El-

valuation of Micromechanical Binary Phase-Only Holographic Optical Elements",

in Proc. IEEE Electronic Technology and Components Conference, May 1997, pp.

419-424.

26. Toby Schae�er, Alan Glaser, Steve Lipa and Paul Franzon,MCM Implementation

of a Data Encryption Standard (DES) Processor, in Proc. 1997 IEEE MCM

Conference, Feb. 1997, pp.13-17.

27. Wes Hansford Jennifer Peltier, Paul Franzon, Steve Lipa, and Jonathan Schae�er,

MIDAS Flip-Chip Service, in Proc. 1997 IEEE MCM Conference, Feb. 1997,

pp.133-135.

14

28. Paul D. Franzon, Tom Conte, Sanjeev Banerjia, Alan Glaser, Steve Lipa, Toby

Scha�er, Andrew Stanaski and Yusuf Tekmen, Computer Design Strategy for

MCM-D/Flip-Chip Technology, in Proceedings 1996 Topical Meeting on Electrical

Performance of Electronic Packaging, Oct. 1996, pp.6-8..

29. Raj Lakhani, Craig Deutschle and Paul Franzon, High Speed Bus Design Using

HSPICE Optimization Techniques Based on Worst Case Design Approach, in Pro-

ceedings 1996 Topical Meeting on Electrical Performance of Electronic Packaging,

Oct. 1996, pp.93-96.

30. P. Franzon, Computer Design Strategy for MCM-D/Flip-Chip Technology, In-

vited paper, in Proceedings 1996 ASIC Conference, Oct. 1996, pp35-39.

31. P. Franzon, System Design Optimization With Multichip Module Technology, In-

vited Paper, in Proceedings 1996 Conference of the Brazilian Microelectronics

Society, July 1996.

32. Christoforos Harvatis, Yusuf C. Tekmen, Grif L. Bilbro, Paul D. Franzon, Pin As-

signment for High-Performance MCM Systems, in Proceedings 1996 IEEE ISCAS

Conference. pp. 771-774.

33. Sanjeev Banerjia, Alan Glaser, Christoforos Harvatis, Steve Lipa, Real Pomerleau,

Toby Scha�er, Andrew Stanaski, Yusuf Tekmen, Grif Bilbro, and Paul Franzon,

Issues in Partitioning Integrated Circuits for MCM-D/Flip-Chip Technology, in

Proceedings 1996 IEEE MultiChip Module Conference.

34. P. Franzon, Optimal System Design with MultiChip Module Technology, Invited

Paper, in Proceedings of Microeletronics'95.

35. A.W. Glaser, M.B. Steer and P.D. Franzon, Measurement of on-IC Capacitance

Structures, in Proceedings 1995 IEEE Topical Meeting on Electrical Performance

of Electronic Packaging.

36. D. Winick, M. Teague, and P. Franzon, A Micro-machined Approach to Optical

Interconnect, in Proc. 1995 Electronic Components and Technology Conference.

pp. 620-627. Won best student paper award.

37. Sharad Mehrotra, Paul Franzon, Michael Steer, Performance Driven Global Rout-

ing and Wiring Rule Generation for High Speed PCBs and MCMs, in Proceedings

1995 Design Automation Conference, pp. 36-40.

38. Paul Franzon, Andrew Stanaski, Yusuf Tekmen, Sanjeev Banerjia, \System De-

sign Optimization for MCM", in Proc. 1995 IEEE MultiChip Module Conference.

39. S. Mehrotra, P. Franzon, G. Bilbro and M. Steer, CAD tools for Managing Signal

Integrity and Congestion Simultaneously, Proc. 1994 Topical Meeting on Electri-

cal Performance of Electrical Packaging, pages 30-32.

40. D. Winick, M. Teague, and P. Franzon, Applications of MEMS to Recon�gurable

Free Space Optical Interconnect, Proc. NSF Optical Packaging Workshop, Breck-

enridge CO, August 15-17, 1994.

15

41. S. Mehrotra, P. Franzon and W. Liu, Skew and Delay Minimization of High Speed

CMOS Circuits using Stochastic Optimization, Proc. 1994 Custom Integrated

Circuits Conference, pp. 45-48.

42. S. Mehrotra, P. Franzon and W. Liu, Stochastic Optimization Approach to Tran-

sistor Sizing for CMOS Circuits, Proc. 1994 IEEE Design Automation Confer-

ence, pp. 36-40.

43. M. Sengupta, S. Lipa, P. Franzon, M. Steer, Control of Crosstalk Noise, Proc.

1994 ECTC Conference.

44. M.S. Basel, M.B. Steer, and P.D. Franzon, \Hierarchical simulation of high speed

digital interconnects using a packaging simulator," Proceedings 44th Electronic

Components and Technology Conference, May 1994.

45. Slobodan Simovich, Sharad Mehrotra, Paul Franzon, Michael Steer, Zaki Rakib

and Garrett Simpson, A Signal Integrity Advisor for Automated Packaging Design,

in Proc. 1993 IEEE Topical Meeting on Electrical Performance of Electronic

Packaging, Monterey CA, October 20{22.

46. Todd A. Cook, P.D. Franzon, and Thomas K. Miller III: \LISAS: A Language

for Instruction Set Architecture Speci�cation", Proc. 1993 ICCD Conference, pp.

552-557.

47. M. Steer, S. Lipa, and P. Franzon, Experimental characterization of interconnects

and discontinuities in thin-�lm multichip module substrates, in Proc. 1993 IEEE

Topical Meeting on Electrical Performance of Electronic Packaging,Monterey CA,

October 20{22.

48. Paul Franzon, Slobodan Simovich, Sharad Mehrotra, Michael Steer, Macromod-

els for Generating Signal Integrity and Timing Management Advice for Package

Design, in Proc. IEEE 1993 ECTC Conference. pp. 523-529.

49. Paul Franzon, Slobodan Simovich, Sharad Mehrotra and Michael Steer, Auto-

matic A-Priori Generation of Delay and Noise Macromodels and Wiring Rules

for MCMs, IEEE 1993 MCM Conference.

50. Slobodan Simovich and Paul Franzon, A simple method for noise tolerance char-

acterization of digital circuits, Proc. 1993 Great Lakes VLSI Conference.

51. Todd A. Cook, Ed Harcourt, Thomas K. Miller III, and Paul D. Franzon: Be-

harvioral modeling of processors from instruction set speci�cations, to appear in

the Open Verilog International 1993 Conference.

52. P.D. Franzon, S. Simovich, M. Steer, M. Basel, S. Mehrotra, and T.D. Mills,

\Tools to aid in Wiring Rule Generation for High Speed Interconnects", Proc.

1992 Design Automation Conference, pp.466-471.

53. P.D. Franzon, M. Mehrotra, S. Simovich, and M. Steer: Automating Design for

Signal Integrity, 1992 IEEE Topical Meeting on Electrical Performance of Elec-

tronic Packaging,Tuscon AZ, Proc. pp.10{13.

16

54. M. Steer and P.D. Franzon: Microwave characterization of thin-�lm multi-chip

module substrates and printed wiring boards accounting for frequency-dependent

characteristic impedance, 1992 IEEE Topical Meeting on Electrical Performance

of Electronic Packaging,Tuscon AZ, Proc. pp.125-127.

55. A. Dholakia, T.M. Lee, D.L. Bitzer, M.A. Vouk, L. Wang, and P.D. Franzon,

An e�cient table-driven decoder for one-half rate convolutional codes, Proc. 30th

ACM SouthEastCon, pp.116-123.

56. E.J. Vardaman andM.W. Hartnett and L.H. Ng and P.D. Franzon, \Cost/performance

issues in multichip module packaging", Proc. Japan Int. Conf. on Microelectron-

ics, 1992.

57. Paul Franzon, Sharad Mehrotra, Slobodan Simovich, Michael Steer, \Automat-

ing Design for Signal Integrity", Topical Meeting on Electrical Performance of

Electronic Packaging, Tucson, Arizona, April 23, 1991.

58. M.B. Steer and P.D. Franzon, \Microwave characterization of thin-�lm multi-chip

module substrates and printed wiring boards accounting for frequency-dependent

characteristic impedance," Topical Meeting on Electrical Performance of Elec-

tronic Packaging, Tucson, Arizona, April 23, 1991.

59. M.B. Steer, S.B. Goldberg, G. Rinne, P.D. Franzon, I. Turlik and J.S. Kasten,

\Introducing the through-line deembedding procedure," 1992 IEEE MTT-S In-

ternational Microwave Symposium Digest, June 1992.

60. Paul Franzon, Michael Steer, Ronald Gyurcsik, Tools and Techniques for the

Design of High Speed Multichip Modules, Proc. Japan IEMT, July, 1991.

61. D. Van den Bout, T. Nagle, T. Miller and P. Franzon, The NCSU Design Center,

in Proc. 1991 Microsystems Educators Conference, July 1991, San Jose CA.

62. P.D Franzon and M.B. Steer, Interconnect Modeling and Simulation for High

Speed MCM, in Proc. Multichip Module Workshop, March 28th-29th, 1991, pp.

122{129.

63. P. Franzon and Michael Steer: Tools and Techniques for the Design of High Speed

Multichip Modules, in Proc. Third Annual Electronics Packaging Symposium,

May 13{14, 1991, Binghamton NY.

64. M.S. Basel, M.B. Steer, P.D. Franzon and D. Winkelstein, High Speed Digital Sys-

tem Simulation using Frequency Dependent Transmission Line Network Modeling,

1991 IEEE MTT-S International Microwave Symposium Digest, June 1991.

65. S.B. Goldberg, M.B. Steer, and P.D. Franzon, Accurate experimental character-

ization of three-ports , 1991 IEEE MTT-S International Microwave Symposium

Digest, June 1991.

66. S.B. Goldberg, M.B. Steer, and P.D. Franzon, Experimental electrical characteri-

zation of high speed interconnects, 41 st Electronic Components and Technology

Conference, May 1991.

17

67. M.B. Steer and P.D. Franzon: Circuit Simulation with Distributed Elements,

Workshop on Circuit and Process Simulation, Microelectronics Center of North

Carolina, Research Triangle Park, Nov. 6, 1990.

68. P. Franzon, et al: CAD Tools for the Automated Design of High Speed Multichip

Modules, Proceedings of the 1990 International Packaging Symposium.

69. M. Lorenzetti, A. Dalal, and P. Franzon: McYield: A CAD Tool for Functional

Yield Projections for VLSI, 1990 International Workshop on Defect and Fault

Tolerance in VLSI Systems.

70. P. Franzon, D. VanDenBout J. Paulos, T. Miller III, W. Snyder, T. Nagle, and W.

Liu: Defect tolerant implementations for feed-forward and recurrent neural net-

works, Proceedings of 1990 International Conference on Wafer-Scale Integration,

January 1990, pages 160{166.

71. P. Franzon: Comparison of Recon�guration Schemes for Defect Tolerant Mesh

Arrays, in Proceedings of the 1989Workshop on Defect Tolerance, Tampa Florida,

22 { 24 October, 1989.

72. P.D. Franzon: Yield Modeling for Fault Tolerant VLSI, in the Proceedings of the

International Workshop on Systolic Arrays, University of Oxford, England, July

1986.

73. P. Franzon and S.K. Tewksbury: `Chip Frame' scheme for recon�gurable mesh-

connected arrays, in the Proceedings of the 1987 International workshop on Wafer

Scale Integration, Uxbridge England, Sept., 1987.

74. L.A. Hornak, S.K. Tewksbury, M. Hatamian, A. Ligtenberg, B. Sugla and P.

Franzon: Through-Wafer Optical Interconnects for Multi-Wafer Wafer-Scale Inte-

grated Architectures, in the Proceedings of SPIE 86, San Diego California, August

1986.

75. P.D. Franzon: Interconnect Strategies for Fault Tolerant 2D VLSI Arrays, in the

Proceedings of the International Conference on Computer Design, ICCD-86, Rye

Town NY, October 1986, pp. 230-234.

76. K.Eshraghian. R.C.Bryant, A.Dickinson, D.S.Fensom, P.D.Franzon, M.T.Pope,

J.E.Rockli�, G.Zyner: The Transform and Filter Brick: A new architecture for

signal processing, VLSI 85, Tokyo Japan, 25-28 August, 1985.

(ii) Invited Research Presentations

1. Title: Structures and CAD for Chip-Package Codesign

Organizaton: Texas Instruments

Place: Hong Kong

Date: 5/16/00

18

2. Title: High Bandwidth On-Chip Interconnect

Organizaton: Texas Instruments

Place: Hong Kong

Date: 5/16/00

3. Title: Heteregenous System Integration

Organizaton: Texas Instruments

Place: Hong Kong

Date: 5/17/00

4. Title: Design Automation and Design Challenges for Package/Systems

Organizaton: IEEE Asia Design Automation Conference

Place: Hong Kong

Date: 1/22/99

5. Title: MEMS Applications and Fabrication

Organizaton: Ford Microelectronics

Place: Colorado Springs, CO

Date: 12/15/98

6. Title: Chip Package CoDesign

Organization: Georgia Inst. of Technology

Place: Atlanta, GA

Date: 10/2/98

7. Title: Integrated Package Design of a DES Processor

Organization: IMAPS

Place: Oqunquit, MN

Date: 7/16/97

8. Title: Chip-Package Codesign

Organization: SRC

Place: RTP, NC

Date: 4/12/97

9. Title: Chip-Package Codesign

Organization: Intel

Place: Santa Clara, CA

Date: 10/12/97

10. Title: Chip-Package Codesign

Organization: DEC

Place: Hudson, MA

Date: 12/15/97

19

11. Title: Computer Design Strategy for MCM-D/Flip-Chip Technology

Organization: IEEE ASIC `96 Conference

Place: Rochestor NY

Date: 9/23/96

12. Title: System Design Optimization With Multichip Module Technology

Organization: Brazilian Microelectronics Society

Place: Agua Du Lindonia, Brazil

Date: 8/1/96

13. Title: Optimal Computer Design with MCM-D/Flip Chip Technology

Organization: Sun MicroSystems

Place: Mountain View, CA

Date: 5/7/96

14. Title: Signal Integrity Tools

Organization: Sun MicroSystems SI Study Group

Place: Mountain View, CA

Date: 5/7/96

I have given invited presentations at the following organizations: Stanford University,

University of Adelaide, Silicon Graphics, Intel, Ross Technology, Cadence, Mentor

Graphics, LSI Technology, Tandem Computer, IBM, Bell Northern Research, MCNC.

Dates and exact titles unrecorded.

(iii) Appointments or election to study sections and editorial boards.

� Associate Editor, IEEE Transactions on VLSI Systems.

� Associate Editor, IEEE Transactions on Components, Packaging and

Manufacturing Technology (CPMT).

� Editorial Board, Journal of Microelectronics System Integration.

� Reviewer for the journals: IEEE Transactions on Computer Aided

Design, IEEE Transactions on Computers, IEEE Trans CPMT, IEEE

Trans VLSI Systems, IEEE Journal of Solid State Circuits, IEEE Trans.

Semiconductor Manfuacturing.

� NSF Reviewer. NSF Panel Member for Research Initiation Awards.

NSF Panel Member for SBIR Awards. NSF Study Group Member for

Impact of FPGAs on Education.

B. Recognized Creative and Professional Achievement. Include publication of cre-

ative or professional works, exhibitions, honors, awards, fellowships, prizes, competi-

tions, and other pertinent evidence.

Please See Section I A.

20

C. Research Project Record. Include externally and internally sponsored grants and

contracts and unsponsored and independent research.

1. P. Franzon and A. Cangelleris, \Inductance control for on-chip signal

integrity,", 8/15/00 - 8/14/02, National Science Foundation, $420,000.

2. R. Hodges, et.al. and P. Franzon, \Applications of MEMS to textiles"

National Textiles Foundation, 4/15/00 - 4/14/01, ECE share: $35,000.

3. P. Franzon, andW. Lui, \ACCoupled Interconnect," 10/1/99 - 9/30/02,

Semiconductor Research Corporation, $321,166.

4. P. Franzon, \VLSI Approaches to Chip-Package Codesign," 1/1/00

- 6/30/00, Semiconductor Research Corporation Exploratory Grant,

$25,000.

5. P. Franzon, \Molecular Circuits," 2/1/00 - 1/31/01, DARPA, $53,015.

6. P.D. Franzon, T. Conte, \SHOCC Demonstrator Study," 7/1/99 -

5/26/00, Northrop Grumman, $128,857.

7. P.D. Franzon, A. Kingon, E. Grant, \Planar Processed Robots", DARPA,

6/28/98 - 6/27/00, $1,274,527.

8. P.D. Franzon, MEMS-based Di�ractive Beam Steerer, STTR Phase 2

under sub-contract to NIPT from the USAF, Jan 1, 1998 { June 30,

2000, ($170,000).

9. P. Franzon, T. Conte, W. Liu, C. Gloster, \Experimental High Perfor-

mance Computing and Communications Systems", NSF CISE Infras-

tructure Award, July 1, 1997 { June 30, 2002, ($1,338,283 including

$503,046 in NCSU matching).

10. P. Franzon, W. Liu, M. Steer, Low-Power, High-Performance MEMS-

based Switch Fabric, Oct. 1, 1996{Sept. 30, 1999, DARPA, ($1,047,658).

11. P. Franzon, T. Conte, W. Liu, Three Dimensional High Density ElectronicModule

Design and Manufacturing, Jan. 1, 1997{Dec 31., 1998, From MCMC under sub-

contract from DARPA, ($257,285).

12. P. Franzon, MEMS-based Di�ractive Beam Steerer, STTR under sub-contract to

NIPT from the USAF, Sept. 14, 1996{ Sept. 13, 1997, ($35,000).

13. P. Franzon, M. Steer, Unrestricted Gift, Cadence, ($60,000 per year).

14. P. Franzon, W. Liu, Unrestricted Gift, Mitsubishi, ($40,000 per year).

15. P. Franzon, Unrestricted Gift, Motorola, ($21,100).

16. M. Steer, P. Russel, P. Franzon, \Experimental Determination of On-Chip In-

terconnect Capacitances", January 1, 1995 to October 31, 1995, Awarded by

Sematech ($127,341).

21

17. G. Bilbro, P. Franzon, \Performance Driven System Design", awarded by Intel

Corporation ($35,000 per year).

18. P. Franzon, G. Bilbro, M. Steer, \Methodology, Tools and Demonstration of MCM

System Optimzition", November 1, 1993 to April 30, 1997, awarded by ARPA

($675,440).

19. P. Franzon, NSFYoung Investigators Award, October 1993{March, 2000, ($285,000).

20. J. Bahler, J. Bowen, P. Franzon, \A Generic Architecture for Intelligent Net-

worked Colocation in Concurrent Engineering" (with speci�c application to early

system decision making vis electonic packaging), October 1, 1992 to March 31,

1996, awarded by NSF ($599,986).

21. P. Franzon, \P2E Transformation Engine for the Generation of Wiring Rules

for Signal Integrity and Timing Management", May 1, 1992 to April 30, 1993,

Cadence Design Systems ($35,009).

22. W. Alexander, P. Franzon, W. Liu, M. Steer, \Equipment for building and testing

very high speed digital systems", awarded by NSF ($250,000).

23. P. Franzon, M. Steer, \Interconnect models for computer aided design of high

speed, multichip modules and integrated circuits", 15 February, 1991 to 30 June,

1993, awarded by NSF ($273,466).

24. P. Franzon, A. Kelley, \New Approaches to Low Energy Computing", 28 February

to 31 December, 1991, awarded by IBM ($29,994).

25. J. Bowen, J. Bahler, P. Franzon, \Design for Testability, Part II", 1 January, 1991

to 31 December, 1991, awarded by IntegratedManufacturing Systems Engineering

Institute ($19,000).

26. H.T. Nagle, D. Van Den Bout, T. Miller, P. Franzon, \Design Center for Teach-

ing Digital Design", 1 September, 1990 { 31 August, 1993, awarded by NSF

($500,000).

27. P. Franzon, \Evaluation of CAD tools for teaching", MCNC, 1 January, 1991 {

15 May, 1991, $4,500.

28. P. Franzon, \CAD Tools for MCMs", MCNC. ($24,008), 16 May 1989 { 15

September 1990.

29. Principal Investigator, \CAD tools for yield modeling", MCNC. ($8,694), 16 Au-

gust 1989 { 15 May 1990.

Summary: Over $9,000,000 in Externally Funded Research.

PENDING PROPOSALS

1. P. Franzon, P. Deane, \AC Coupled Interconnect", submitted to NSA

via congress as a congressional set-aside.

22

2. P. Franzon, A. Cangelleris, \On-chip inductance extraction", submit-

ted to the National Science Foundation. (To be funded and included

above.)

3. P. Franzon, \The electronic guide-dog", submitted to the National Sci-

ence Foundation.

4. W. Lui, P. Franzon, N. Dugan, \SOI Radio", submitted to NASA.

D. Master's and Doctoral Theses Directed

Toby Scha�er, Chip-package Codesign, Ph.D.

Mouna Nakkar, Dynamically Programmable Cache, Ph.D.

Debu Ghosh (co-chair), Synthesis of Benchmarking Expiriments, Ph.D.

V. Parameshawara (co-chair), Enhancement of NC Agricultural Auto-

mated Weather Network and Development of Advanced Communica-

tion, Data Acquisitions amd Dissemation System, MS.

Jeremy Palmer, Design and Analysis of a VLSI-MEMS-Based Di�ractive Optical

Beam Steering System, MS.

Mir Azam, CustomCMOS Design and Architecture for Low-PowerHigh-Performance

Circuits, PhD.

Som Chaudry, MEMS devices for laser radar, MS.

Srisai Rao, Design, place and route of an IDEA processor, MS.

Chris Harvatis, Performance Driven Partitioning for MCMs, PhD.

Kevin Mock, IDEA Implementation, MS.

Sibi Kuruvilli, Synthesized SAND Issue Unit, MS.

SharadMehrotra, Automated Synthesis of High Speed DigitalCircuits and Package-

Level Interconnect, PhD.

Slobodan Simovich, Computer-Aided Analysis of Interconnect, PhD.

Scott Washabaugh, Low energy FSM Design, PhD.

Todd Cook, Instruction Set Architecture Speci�cation, PhD.

Robert Evans, Energy Consumption for Modeling and Optimization of SRAMs,

PhD.

Tom Mills, Macromodelling of high speed digital drivers and receivers, MS.

Matreiya Sengupta, Managing Crosstalk in Interconnect Design, MS.

Andrew Stanaski, Optimizing Memory Design for Packagability, MS.

Jonathon Schae�er, A 400 MHz CMOS Multiplier, MS.

23

Harsh Deshmane, MCM Extractor in Magic, MS.

Sha Ma, Circuits for Low Energy Computing, MS.

Shauki Elassaad, Placement tools for multi-chip modules, MS.

Alex Dalal, CAD tools for yield estimation, MS.

(Please See II. D for students currently being directed.)

E. Technology Transfer. Include invention disclosures, patents �led and patents awarded,

new cultivars developed and released, major software packages, design patents, and

other pertinent evidence.

� M. Azam, P. Franzon, Glitch resistant low power circuit design technique, �led

with NCSU, December 1997. Patent �ling negotions in progress with Mitsubshi

America.

� P. Franzon. DLX RTL Design. This copyrighted microprocessor design has been

released to several companies to help them evalaute their Computer Aided Design

tools.

� P. Franzon. DES RTL Design. This copyright encryption design has been released

to several companies to help them evalaute their Computer Aided Design tools.

� P. Franzon, D. Winick, MEMS-based di�ractrive modulators, �led with NCSU,

1993.

� P. Franzon, D. Winick, B. Duewer, W. Liu, MEMS-based crossbar switch, �led

with NCSU, 1996.

� P. Franzon, A. Stanaski, D. Winick, Capacitive Sensor for Flip-Chip Debug, �led

with NCSU, 1997.

� S. Lipa, A. Glaser, M. Steer, P. Franzon, Spice2Ibis software, available on the

ERL Web Site.

� Y. Tekmen, S. Mehotra, P. Franzon, Signal Integrity Advisor software, available

on the ERL Web Site.

F. Cross-Disciplinary Activities. Include participation in Centers, Institutes, and other

organized research e�orts between departments within and across colleges

� Member, Electronics Research Laboratory.

� Member, Center for Advanced Computing and Communications.

IV. EXTENSION ANDPUBLIC SERVICE CONTRIBUTIONSWITH EVAL-UATION

24

A. Scholarly Achievement and Publications. Include referreed publications, brochures, re-

ports, nonrefereed publications, computer software, educational video tapes, slides sets,

popular press articles and other pertinent evidence.

For refereed publications, See Section II A. part (i).

For software, see Section III E. part (ii).

I have contributed to the following brochures, reports, and training tapes:

� PE Exam Review, Communications, on-going.

� Worldwide Multichip Module Market Analysis, Techsearch Int. 1991. (A consult-

ing report that sold over 1,000 copies.)

� MCM Market Sources Directory, Techsearch Int., 1992/3/4/5. (A directory series

that sold over 5,000 copies.)

� ECE Department Undergraduate Recruiting Brochure. 1996/7. (Used at Open

House and other activities to help recruit students to NCSU.)

B. Technology Transfer. Include major accomplishments, program impacts.

See Section III.E. Note that in the course of both my research and teaching, we have

developed a number of chip designs and software packages that are being used, or are

considered being used by Industry. In addition, to those documented above, we are in

ongoing discussions with local companies (Mitsubishi, Paracom, and Secant).

C. Recognized Creative and Professional Achievement. Inlcude exhibitions, honors, awards,

prizes, grants and contracts, and otehr pertinent evidence.

Please see Section III A (ii), III B, I A (iii) and III C.

D. Public Service. Include seminars and meetings arranged, special intervention programs,

workshops, special projects, design assistance, and other pertinent evidence.

� General Chair, 1997 IEEE MultiChip Module Conference.

� Technical Program Chair, 1996 IEEE MultiChip Module Conference.

� Co-Chair, 1993 SouthEastern Universities Undergraduate Design Conference.

� Co-Chair, 1997 IEEE Workshop on Clock Design.

I have provided design assistance to many companies, including BNR, IBM,Mitsubishi,

Cadence, Mentor, Square-D, Ericson, Elliot Technologies, Silicon Graphincs Inc., Sun

Microsystems, etc.

E. Cross-DisciplinaryActivities. Include contributions to special University-wide initiatives.

Partipated in NSF ERC proposal, 1999.

Conducting collaborative research with the COllege of Textiles.

25

V. OTHER CONTRIBUTIONS WITH EVALUATION:Include University service (department, college, and NCSU committees), state and regional,

and national and international activities and committee work.

WITHIN NCSU

� Chair, ECE Research Planning Committee.

� Supervisor, Departmental System Administrator.

� Organized e�ort to fund and hire Computer System Administrator to support

research computing in the ECE Department.

� Head, 1996 Computer Engineering Search Committee (sucessfully hired A. Eichen-

berger).

� Member, 1995 Computer Engineering Search Committee (sucessfully hired T. Conte).

� Member, 1995 ECE Department Head Search Committee.

� Member, Engineering Computing Commitee, 1994-1995.

� Member, ECE Graduate Committee, 1992-1993.

NATIONAL AND INTERNATIONAL

� General Chair, 1997 IEEE MultiChip Module Conference.

� Technical Program Chair, 1996 IEEE MultiChip Module Conference.

� Program Committee, 1996/1997 IEEE Innovative Systems In Silicon Conference.

� Program Committee, 1997, 1998 IEEE Int. Conference on Computer Design.

� Program Committee, 1997, 1998 ISIS.

� Tutorial Chair, 1994, 1995 IEEE MultiChip Module Conference.

� Education Committee Chair, IEEE CPMT Society, 1992-1995.

� Program Committee and Tutorial Chair, 1993-2000 IEEE Topical Meeting

on Electrical Performance of Electronic Packaging.

� Program Committee, MICRO/MEMS'99.

� Program Committee, MICRO/MEMS'00.

� Program Committee, CPD-99, CPD-00.

� Program Committee, 1998 IPID.

26

� Program Committee, 1998 IMAPS MCM Conference.

� Reviewer, Design Automation Conference.

� Reviewer, National Science Foundation.

� Reviewer, Swiss National Science Foundation.

� Reviewer, Hong Kong Engineering Research Council.

27