output pad and driver
DESCRIPTION
OUTPUT Pad and Driver. CLOCK DRIVER. Buffering. S = scaling or tapering factor CL = S N+1 Cg ……………… All inverters have identical delay of t o = delay of the first stage (load =Cd+Cg). 5. S. 4. 3. 0 1 2 3. Cd/Cg. Buffering. - PowerPoint PPT PresentationTRANSCRIPT
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OUTPUT Pad and Driver
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CLOCK DRIVER
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Buffering
S = scaling or tapering factor
CL = SN+1 Cg ………………
All inverters have identical delay ofto = delay of the first stage (load =Cd+Cg)
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Buffering
0 1 2 3
3
4
5
Cd/Cg
S
If the diffusion capacitance Cd is neglected,S = e = 2.7
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Layout of Large Device
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Large Transistor Layout
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Output Drivers
Standard CMOS Driver
Open Drain/Source Driver: Single Transistors
Tri-state Driver
Bi-directional Circuit
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Tri-state Driver
In
VDD
En
EnOut
Tri-state or High impedance Used to drive internal or external busses Two inputs: Data In and Enable Various signal assertions Two types: C2MOS CMOS with Control Logic
C2MOS
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VDD
En
En
PADOut
In
Control logic could be modified to obtain Inversion/non-inversion Active low/high Enable
For large load, pre-driversare required
Tri-state Driver
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Latch-up: Trigger
Factors which trigger latch-up
transmission line reflections or ringing
voltage drop on the VDD bus “hot plug in” of unpowered circuit
board electrostatic discharge sudden transient on power and
ground busses leakage current across the junction radiation: x-ray, cosmic
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Input PAD
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Protection Circuitry Principles
Punch Through Avalanche
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Protection Circuitry
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Protection Circuitry
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Input protection
Electrostatic discharge can take place through transfer of charges from the human body to the device.
Human body can carry up to 8000V. Discharge can happen within hundreds of nanoseconds. Critical field for SiO2 is about 7X106 V/cm. For 0.5u CMOS process the gate oxide can withstand around 8V
Some protection technique is required with minimum impact on performance
DUT100pF
1.5K1M
Vesd
Human Body model
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ESD Structures
Basic technique is to include series resistance and two clamping diodes.The resistance R is to limit the current and to slow down the high voltage transitions.R could be polysilicon or diffusion resistanceDiffusion resistance could be part of the diode structureTypical values of R: 500 to 1k
PAD
VDD
R
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Layout of ESD Structure
p+
p+
n+
n+n+
p+
Guard RingGuard Ring
PADThis structureuses transistors asclamping diodes
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p+
p+
n+
n+n+
p+
Guard RingGuard Ring
PAD
VDD
GND
Layout of ESD Structure
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Another ESD Structure
PAD
VDD
R2
Thick FOXMOS Transistor
R1
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Bi-direct PAD
PAD
VDD
ESD ProtectionInput Buffer
Control Logic
EN
IN
Pre-drivers
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Thank you !