optimus fabric interface specification...write/read control write/read control uart_fifo_ctl txd...

UART

User Guide

04/2014

Capital Microelectronics, Inc.

China

User Guide of UART

http://www.capital-micro.com 2

Contents

Contents ..................................................................................................................................................2

1 Introduction ......................................................................................................................................4

2 UART Overview .................................................................................................................................5

2.1 Pins and Parameters ............................................................................................................................. 5

2.1.1 EMIF interface ................................................................................................................................... 5

2.1.2 AHB interface .................................................................................................................................... 6

2.2 UART Block Diagram ............................................................................................................................. 7

2.2.1 EMIF interface ................................................................................................................................... 7

2.2.2 AHB interface .................................................................................................................................... 7

2.2.3 Block diagram description ................................................................................................................ 7

2.3 UART Internal Registers ........................................................................................................................ 8

2.3.1 Overview ........................................................................................................................................... 8

2.3.2 Serial Port Mode Register – SMOD ................................................................................................... 9

2.3.3 Serial Port Control register – SCON................................................................................................... 9

2.3.4 Serial Port Data Buffer – SBUF ........................................................................................................ 10

2.3.5 Serial Port Reload Register - SRELH, SRELL ..................................................................................... 11

2.3.6 Serial Port Data Buffer - SBUFH ...................................................................................................... 11

2.3.7 Transmit/Receive FIFO State Register – STATE ................................................................................ 11

2.3.8 Serial Port Command Register – SCOMM ....................................................................................... 12

2.3.9 Transmit/Receive FIFO Data Amount Register(High) – TRCNTH ..................................................... 12

2.3.10 Transmit FIFO Data Amount Register(Low) – TRANSCNTL ............................................................ 12

2.3.11 Receive FIFO Data Amount Register(Low) – RCVCNTL .................................................................. 13

2.3.12 Receive Overtime Counter Threshold Register – RCVOVERT0…3 ................................................. 13

2.3.13 Receive Overtime Counter Register – RCVOVERC0…3 .................................................................. 13

2.3.14 Receive FIFO Threshold Register – RCVTHREL, RCVTHREH ........................................................... 14

2.3.15 Transmit FIFO Data Amount Register – TRANSCNT ...................................................................... 14

2.3.16 Receive FIFO Data Amount Register – RCVCNT ............................................................................ 15

2.3.17 Receive Overtime Counter Threshold Register – RCVOVERT ........................................................ 15

2.3.18 Receive FIFO Threshold Register – RCVTHRE ................................................................................ 15

3 UART IP Usage ................................................................................................................................. 16

3.1 Baud Rate Generation ........................................................................................................................ 16

3.2 Serial Port Operation Mode – mode 0 ............................................................................................... 16


3.3.1 Non-fifo ........................................................................................................................................... 17

3.3.2 With fifo .......................................................................................................................................... 18

3.3.3 5, 6, 7-bit support ........................................................................................................................... 20


3.4.1 Non-fifo ........................................................................................................................................... 20

3.4.2 With fifo .......................................................................................................................................... 21

User Guide of UART



3.5.1 Non-fifo ........................................................................................................................................... 22

3.5.2 With fifo .......................................................................................................................................... 23

3.6 Serial Port Multiprocessor Communication ....................................................................................... 24

3.7 External Memory Interface (EMIF) Operation .................................................................................... 24

3.8 AHB Interface Operation .................................................................................................................... 27

3.9 Interrupt Operation ............................................................................................................................ 28

3.10 Resource Usage and Performance Analysis ........................................................................................ 30

4 Generate File Directory Structure ..................................................................................................... 31

Revision History ..................................................................................................................................... 34

User Guide of UART


1 Introduction

This document mainly describes the usage of the UART IP. Based on the behavior of 8051’s internal UART, this

IP is upgraded to support new features. The IP provides two kinds of simplified interface connected to EMIF

bus and AHB bus for communication with 8051 core and ARM core for different device of CME. The two kinds

of interface are full-duplex serial communication interface.

The UART IP supports the following features:

Support programmable baud rate

Synchronous mode, fixed baud rate

5-bit, 6-bit, 7-bit, 8-bit data width, variable baud rate in mode 1

9-bit UART mode, fixed baud rate

9-bit UART mode, variable baud rate

512-byte fifo for transmit & receive data path respectively, which can be configured by users

Support batch data read and receive overtime control(only for interrupt function) in mode 1

Support baud rate up to 115200bps

Support AHB interface and EMIF interface

Programmable BASE_ADDR for internal registers, EMIF interface address must be 0x20 aligned, AHB

interface address must be 0x80 aligned

Device family support:

CME-M5,CME_M7,CME_HR3,CME_HR2

User Guide of UART


2 UART Overview

2.1 Pins and Parameters

2.1.1 EMIF interface

Table 2-1 UART IP pin description with EMIF interface

Interface Name Direction Width Description

System

interface

clk Input 1 Clock input

rst_n Input 1 Reset input, low active

User

interface

rxdi Input 1 Receive data input

rxdo Output 1 mode 0 receive data output

txd Output 1 transmit data output

irq Output 1 UART interrupt request

Memory

interface

with MCU

memaddr Input 23 8051 ext-memory address

memdatai Input 8 8051 ext-memory data input

memdatao Output 8 8051 ext-memory data output

memwr Input 1 8051 ext-memory write enable

memrd Input 1 8051 ext-memory read enable

memack Output 1 8051 ext-memory acknowledge

Table 2-2 UART IP Parameters

Parameters Type Description

BASE_ADDR Integer EMIF /AHB bus base address of the UART IP

DATA_WIDTH Integer Bits a byte have. 5, 6, 7, 8 are available choices in mode 1;

in mode 0, 2 and 3, the value has to be set as 8

FIFO_EN Integer 1: Transmit and receive fifo are used

0: Transmit and receive fifo are not used

BATCHRDEN Integer 1: Batch data read and receive overtime control enable. For

receive fifo, users can set a data threshold, if data amount

of receive fifo reaches the threshold set, IP core triggers an

interrupt, so mcu could continuously read the specific

amount(set threshold) of data with no need to check

receive fifo status. Furthermore, receive overtime control is

enable. Users set a counter threshold(counting time unit:

the time a bit transmission occupies). If there is some data,

the amount of which does not reach the data threshold but

internal counter reaches the counter threshold, an interrupt

User Guide of UART


is asserted and mcu could read out these data. The internal

counter is reset to zero every time a new data is received.

0: Both batch data read and receive overtime control are

disable. If the receive fifo is not empty, IP asserts an

interrupt.

2.1.2 AHB interface

Table 2-3 UART IP pin description with AHB interface

Interface Name Direction Width Description

User

interface

rxdi Input 1 Receive data input

rxdo Output 1 mode 0 receive data output

txd Output 1 transmit data output

irq Output 1 UART interrupt request

Memory

interface

with MCU

hclk Input 1 AHB interface clock

hresetn Input 1 AHB reset signal, low active

haddr Input 32 AHB address bus

hsel Input 1 AHB slave select signal

htrans Input 2 AHB transfer type

hwrite Input 1 AHB transfer direction: 1-write,

0-read

hsize Input 3 AHB transfer size signal

hburst Input 3 AHB transfer type signal

hwdata Input 32 AHB write data bus

hrdata Output 32 AHB read data bus

hready_out Output 1 Transfer done output

hresp Output 1 Transfer response signal

UART IP Parameters of AHB interface is the same as Table2-2.

User Guide of UART


2.2 UART Block Diagram

2.2.1 EMIF interface

Transmit FIFO

Receive FIFO

Serial Core

wrdatawrenrden

memdataimemdataomemwrmemrdmemaddrmemack

Ad

dre

ss M

app

ing

rddata

wrdatawrenrden

rddata

ConfigureControl

Logic

Write/Readcontrol

Write/Readcontrol

Uart_fifo_ctl

txdrxdo

rxdi

irq

clkrst_n

control & data sent

status & data received

Figure 2-1 UART IP block diagram of EMIF interface

2.2.2 AHB interface

Transmit FIFO

Receive FIFO

Serial Core

wrdatawrenrden

hwdatahrdatahaddrhselhwritehtranshsizehbursthresphready_out

Ad

dre

ss M

app

ing

rddata

wrdatawrenrden

rddata

ConfigureControl

Logic

Write/Readcontrol

Write/Readcontrol

Uart_fifo_ctl

txdrxdo

rxdi

irq

hclkhresetn

control & data sent

status & data received

Figure 2-2 UART IP block diagram of AHB interface

2.2.3 Block diagram description

User Guide of UART


The UART IP includes 4 sub modules: uart_fifo_ctl, serial_core, transmit fifo and receive fifo.

uart_fifo_ctl:

The functions of this module are as below:

Map 8051’s EMIF or ARM AHB bus address to UART IP internal register address. The base address of

UART IP can be set by user. But each internal register’s offset address can’t change.

Control tx_fifo data writing(from the EMIF bus or AHB bus) and data reading(from the request of

serial_core), clear the interrupt indicating data transmitting over and show the status of tx_fifo(empty

& full).

Control rx_fifo data writing(from the serial_core) and data reading(from the EMIF bus or AHB bus),

clear the interrupt indicating received data available and show the status of rx_fifo(empty & full).

Receive overtime control. In batch data read mode, there is an 32-bit counter. Every time a new data is

received, the counter is reset to 0. Then it increases by 1 every baud rate clock cycle. When the data

amount of receive fifo does not reach the threshold user set, but the counter reaches the threshold, an

interrupt is asserted, then mcu could read out left data. Also, through reading out the real time value of

the counter, users could know how long has passed after the last data is received.

serial_core:

This module the core control module of UART, which includes: baud rate generator, internal registers, control

logic, transmit shift register, receive shift register, output logic and input logic.

Transmit/Receive FIFO:

512-depth, 9-bit width fifo, used to store data which is received or to be transmitted.

2.3 UART Internal Registers

2.3.1 Overview

All registers are shown below as Table 2-4 (EMIF interface) and Table 2-5(AHB interface)

Table 2-4 All Internal Registers of EMIF interface

memaddr[22:0] Register Comment Access Type

Base+1 SMOD Register Serial control register

R/W

Base+2 SCON Register R/W

Base+3 SBUF Register Serial data buffer register(low) R/W

Base+4 SRELH Register Serial Baud reload register

R/W

Base+5 SRELL Register R/W

Base+6 SBUFH Register Serial data buffer register(high) R/W

Base+7 STATE Register FIFO status register R

Base+8 SCOMM Register Command register W

Base+9 TRCNTH Register Bit 9 of data amount of transmit &

receive fifo R

Base+10 TRANSCNTL Register Data amount(low 8 bits) of transmit

fifo

R

Base+11 RCVCNTL Register Data amount(low 8 bits) of receive

fifo

R

User Guide of UART


Base+12 RCVOVERT0 Register

Receive Overtime Counter Threshold

register

R/W([7:0])

Base+13 RCVOVERT1 Register R/W([15:8])



Base+16 RCVOVERC0 Register

Receive Overtime Counter register

R/W([7:0])

Base+17 RCVOVERC1 Register R/W([15:8])



Base+20 RCVTHREL Register Receive fifo Threshold(low 8 bits) R/W([7:0])

Base+21 RCVTHREH Register Receive fifo Threshold(high 1 bits) R/W([15:8])

Table 2-5 All Internal Registers of AHB interface

haddr[31:0] Register Comment Access Type

Base+4 SMOD Register Serial control register

R/W

Base+8 SCON Register R/W

Base+C SBUF Register Serial data buffer register(low) R/W

Base+10 SRELL Register Serial Baud reload register

R/W

Base+14 SRELH Register R/W

Base+18 SBUFH Register Serial data buffer register(high) R/W

Base+1C STATE Register FIFO status register R

Base+20 SCOMM Register Command register W

Base+24 TRANSCNT Register Data amount of transmit fifo R

Base+28 RCVCNT Register Data amount of receive fifo R

Base+2C RCVOVERT Register Receive Overtime Counter Threshold

register

R/W

Base+30 RCVOVERC Register Receive Overtime Counter register R/W

Base+34 RCVTH Register Receive fifo Threshold R/W

2.3.2 Serial Port Mode Register – SMOD

Table 2-6 SMOD Register

Reset value: 00h

Bit Symbol Description Access Type

7 smod Serial Port baud rate select

SMOD = 1, baud rate double

SMOD = 0, baud rate not double

R/W

6:0 -- Not used, read as 0 R

Note: The register bit[7:0] are same in EMIF interface and AHB interface

2.3.3 Serial Port Control register – SCON

User Guide of UART


Table 2-7 SCON Register

Reset value: 00h


7 sm0 Serial Port mode select

(see table 2-8)

R/W

6 sm1 R/W

5 sm2 Multiprocessor communication enable R/W

4 ren Serial reception enable

If set HIGH serial reception at Serial Port is enabled.

Otherwise serial reception at Serial Port is disabled.

R/W


1 ti Transmit interrupt flag

It indicates completion of a serial transmission at Serial Port

when transmit fifo is not used.

It is set by hardware at the end of bit 8 in mode 0 or at the

beginning of a stop bit in other modes. It must be cleared

by software(refer to SCOMM).

R

0 ri Receive interrupt flag

It is set by hardware after completion of a serial reception

at Serial Port when receive fifo is not used.

It is set by hardware at the end of bit 8 in mode 0 or in the

middle of a stop bit in other modes.

It must be cleared by software(refer to SCOMM).

R


Table 2-8 Serial Port work modes and baud rates

sm0 sm1 Mode Description Baud Rate

0 0 Mode 0 Shift register Fclk/12

0 1 Mode 1 5,6,7,8-bit UART Variable (details below the table)

1 0 Mode 2 9-bit UART Depends on SMOD

SMOD = 0, Fclk/64

SMOD = 1, Fclk/32

1 1 Mode 3 9-bit UART Variable (details below the table)


The baud rate for serial port working in mode 1 or mode 3

Baud rate = 2SMOD*Fclk/(64*(210-SREL))

SMOD: Serial port baud rate select flag (Table 2.3)

SREL: the contents of SREL register (SRELH, SRELL)

2.3.4 Serial Port Data Buffer – SBUF

Reset value: 00h

If fifo is used, Writing data to this register puts data into the transmit fifo. Data can be written into fifo until it

User Guide of UART


is full. And data in fifo is transmitted successively without any control. Reading from the SBUF reads data from

receive fifo. Only when receive fifo is not empty, software can read this buffer.

In application fifo is not used, writing data to this register sets data in serial output buffer and starts the

transmission through Serial Port. Reading from the SBUF reads data from the serial receive buffer.

Note: The register is same in EMIF interface and AHB interface

2.3.5 Serial Port Reload Register - SRELH, SRELL

SRELH: Reset value: 03h

SRELL: Reset value: D9h

Serial Port Reload Register is used for Serial Port baud rate generation.

Only 10 bits are used. 8 bits from the SRELL as lower bits and 2 bits from the SRELH (srelh.1, srelh.0) as higher

bits.

Note: The two registers are same in EMIF interface and AHB interface

2.3.6 Serial Port Data Buffer - SBUFH

Reset value: 00h

Only bit 0 of this register is used. When the core works in mode 2/3, the most significant bit(bit8) to be

transmitted should be written to bit0 of this register. When reading, the bit is the most significant bit(bit8) of

the 9-bit data received.


2.3.7 Transmit/Receive FIFO State Register – STATE

Table 2-9 STATE Register

Reset value: 11h


7 -- Not used, read as 0 R

6 trans_busy Transmit busy flag(valid when fifo is used)

1: data in transmit fifo is being transmitted

0: all data transmission in transmit fifo is over

R

5 tfifo_full Transmit fifo full flag

1: transmit fifo is full, mcu cannot write new data to

transmit fifo

0: transmit fifo is not full, mcu can write new data to

transmit fifo

R

4 tfifo_empty Transmit fifo empty flag

1: transmit fifo is empty

0: transmit fifo is not empty, some data still waiting for

be transmitted

R

3 rcv_overtime Receive overtime valid flag

1: from last data received, the counter exceeds the

threshold users set(RCVOVER0, RCVOVER1,

RCVOVER2, RCVOVER3).

R

User Guide of UART


0: do not exceed

2 rfifo_thre Receive fifo threshold flag

1: data amount of receive fifo is equal to or larger than

the threshold users set

0: data amount of receive fifo is smaller than the

threshold users set

R

1 rfifo_full Receive fifo full flag

1: receive fifo is full, if another new data is received, it

is lost

0: receive fifo is not full

R

0 rfifo_empty Receive fifo empty flag

1: receive fifo is empty, mcu cannot read data from fifo

0: receive fifo is not empty, mcu can read data from

fifo

R


2.3.8 Serial Port Command Register – SCOMM

This register is write-only. To write different value to the register indicates different operation to hardware.

Details are as below.

Table 2-10 SCOMM command description

Bit Condition Description

0x61 valid when fifo and overtime

control are used;

Clear receive overtime valid flag

0x81 valid when fifo is unused; Clear transmit interrupt flag(refer to SCON.1)

0x41 valid when fifo is unused; Clear receive interrupt flag(refer to SCON.0)


2.3.9 Transmit/Receive FIFO Data Amount Register(High) – TRCNTH

Table 2-11 TRCNTH Register

Reset value: 00h



4 Tfifo_cnt9 Bit 9 of the data amount of transmit fifo R


0 Rfifo_cnt9 Bit 9 of the data amount of receive fifo R

Note: This register is only used in EMIF interface

2.3.10 Transmit FIFO Data Amount Register(Low) – TRANSCNTL

User Guide of UART


Table 2-12 TRANSCNTL Register

Reset value: 00h


7:0 transcntl Data amount(low 8 bits) of transmit fifo R


2.3.11 Receive FIFO Data Amount Register(Low) – RCVCNTL

Table 2-13 RCVCNTL Register

Reset value: 00h


7:0 rcvcntl Data amount(low 8 bits) of receive fifo R


2.3.12 Receive Overtime Counter Threshold Register – RCVOVERT0…3

Table 2-14 RCVOVERT0 Register

Reset value: FFh


7:0 rcvovert Bit[7:0] of Receive Overtime Counter Threshold register R/W



Reset value: FFh





Reset value: FFh





Reset value: FFh




2.3.13 Receive Overtime Counter Register – RCVOVERC0…3

User Guide of UART


Table 2-18 RCVOVERC0 Register

Reset value: 00h


7:0 Rcvoverc Bit[7:0] of Receive Overtime Counter register R/W



Reset value: 00h





Reset value: 00h





Reset value: 00h


7:0 rcvoverc Bit[31:24] of Receive Overtime Counter register R/W


2.3.14 Receive FIFO Threshold Register – RCVTHREL, RCVTHREH

Table 2-22 RCVTHREL Register

Reset value: FFh


7:0 rcvtherl Bit[7:0] of receive fifo Threshold register R/W


Table 2-23 RCVTHREH Register

Reset value: 01h



0 rcvtherh Bit[8] of receive fifo Threshold register R/W


2.3.15 Transmit FIFO Data Amount Register – TRANSCNT

User Guide of UART


Table 2-24 TRANSCNT Register

Reset value: 000h


8:0 transcnt Data amount of transmit fifo R/W

Note: This register is only used in AHB interface

2.3.16 Receive FIFO Data Amount Register – RCVCNT

Table 2-25 RCVCNT Register

Reset value: 000h


8:0 rcvcntl Data amount of receive fifo R


2.3.17 Receive Overtime Counter Threshold Register – RCVOVERT

Table 2-26 RCVOVERT Register

Reset value: FFFFh


31:0 rcvovert Receive Overtime Counter Threshold register R/W


2.3.18 Receive FIFO Threshold Register – RCVTHRE

Table 2-27 RCVTHRE Register

Reset value: 1FFh


8:0 rcvther Receive FIFO Threshold register R/W


User Guide of UART


3 UART IP Usage

3.1 Baud Rate Generation

10-Bit Timer

SRELH SRELL

div(1/2)

div(1/2)

div(1/16)

clk clk/2 Baud rate

clk

clk/2

0

SCON(7-6)

Baud

x16

Baud

SMOD

Figure 3-1 Baud rate generation

As is shown in table 2.5, under different work mode, the baud rate settings are different. For work mode 0, 2,

the baud rate is fixed, depends on input clk frequency. For mode 2, the SMOD can control whether the baud

rate need to double. For work mode 1, 3, the baud rate is variable, which depends on the setting of SRELH,

SRELL.

3.2 Serial Port Operation Mode – mode 0

In mode 0 the Serial Port operates as synchronous transmitter/receiver. The "txd" outputs the shift clock. The

“rxdo” outputs data and the “rxdi” inputs data. 8 bits are transmitted with LSB first. The baud rate

(t_baud_clk) is fixed at 1/12 of the main clock frequency. Reception is started by setting the “ren” = 1 flag of

“SCON” register and clearing the “ri” flag. Transmission is started by writing data to “SBUF” register. In mode 0,

the hardware does not support fifo.

Figure 3-2 serial port transmission without fifo in mode 0

User Guide of UART


Figure 3-3 serial port reception without fifo in mode 0


3.3.1 Non-fifo

In mode 1 the Serial Port operates as asynchronous transmitter/receiver with 8(5,6,7 can be selected by user)

data bits and programmable baud rate. “SRELH”, “SRELL” baud rate generator is used. Additionally the baud

rate can be doubled with the use of the “smod” bit of the “SMOD” register.

Transmission is started by writing to the “SBUF” register. The “txd” pin outputs data. The first bit transmitted

is a start bit (always 0), then 8(5,6,7 can be selected by user) bits of data proceed, after which a stop bit

(always 1) is transmitted.

The “rxdi” pin inputs data. When reception starts, the Serial Port synchronizes with the falling edge detected

at pin “rxdi”. Input data are available after completion of the reception in the “SBUF” register. During the

reception, the “SBUF” remains unchanged until the completion.


User Guide of UART



3.3.2 With fifo

3.3.2.1 Data Transmission

With transmit fifo, software can write a large amount of data into fifo only when the fifo is not full. Controller

of the IP samples the empty state of transmit fifo. If the fifo is not empty, then read out a byte and send out.

When the sending is over, controller samples the empty state of transmit fifo again and goes into another

sending process. During this “sample-send-sample” process, there is no need for software control. As for the

flow chart, refer to figure 3-6.

Ready to transmit

new data

Tx fifo full?

Write to Tx fifo

N

Y

Send byte bit by bit

Figure 3-6 serial port transmission with fifo in mode 1

3.3.2.2 General Data Read

With receive fifo, the UART IP receives data and writes into fifo. If the fifo is full and another data is received,

then data-loss occurs. System designer should modify the serial communication setting to avoid data-loss. For

software, when the receive fifo is not empty, it can read data from the fifo. Software read can be carried out

only if the receive fifo is not empty.

User Guide of UART


Ready to read

received data

Rx fifo empty?

Read Rx fifo

N

Y

Figure 3-7 serial port reception with fifo in mode 1(general data read)

3.3.2.3 Batch Data Read(for interrupt function)

For data reception, the data access speed in batch data read is greater than that in general data read because

there is no need to check the status of receive fifo.

For batch data read, during initialization, receive fifo threshold T(refer to 2.3.14) and receive overtime

threshold C(refer to 2.3.12) must be set. The receive overtime counter is driven by baud rate clock. After

initialization, mcu or other type of controller waits for the assertion of irq(interrupt).

With interrupt sampled, users must read fifo status register STATE(refer to 2.3.7) to check interrupt source,

data amount or receive overtime. If it is data amount(STATE.bit2 = 1), it means there are at least T bytes in

receive fifo so users can read receive fifo T times continuously with no need to check whether the receive fifo

is empty. When the data in receive fifo is less than set threshold, the interrupt is cleared by hardware.

If the interrupt source is receive overtime(STATE.bit3 = 1), users should first read STATE.bit0 to check whether

the receive fifo is empty. If empty, it means during the set time interval, no data is received and write 0x61 to

SCOMM to clear the interrupt. If not empty, read out one byte and check the empty status of receive fifo

again. Like this, uses should read out all data in receive fifo. Then, 0x61 should be written to SCOMM to clear

the interrupt.

User Guide of UART


Interrupt?

Read data one time

N

Y

Receive Fifo Threshold Setting

Receive Overtime Threshold Setting

Read Interrupt Status

ThresholdOvertime

Read Data Continuouslydata amount = threshold

Recefive fifoEmpty?

Y

Initialization

Write 0x61 to SCOMMClear interrupt

Figure 3-8 serial port reception with fifo in mode 1(batch data read)

3.3.3 5, 6, 7-bit support

In mode 1, the UART IP supports 5, 6, 7-bit width. When 5-bit is selected, during the transmitting process, the

core truncates the low 5 bits and sends out. So, no matter what the high 3 bits are, they cannot be sent out.

When 6-bit or 7-bit is selected, the core works the same as 5-bit.


3.4.1 Non-fifo

In mode 2 the Serial Port operates as asynchronous transmitter/receiver with 9 data bits and baud rate fixed

to Fclk/32 or Fclk/64, depending on the setting of “smod” bit of “SMOD” register.


is a start bit (always 0), then 9 bits of data proceed where the 9th is taken from bit0 of the “SBUFH” register,

after which a stop bit (always 1) is transmitted. Writing to “SBUFH” has to be ahead of writing to “SBUF”.

User Guide of UART



at pin “rxdi”. Input data are available after completion of the reception in the “SBUF” register, and the 9th bit

is available as bit0 in the “SBUFH” register. During the reception, the “SBUF” and “SBUFH” bit0 remain

unchanged until the completion.



3.4.2 With fifo

With transmit fifo, software can write a large amount of data into fifo only when the fifo is not full. Because

the EMIF bus is 8-bit wide and the data is 9-bit wide, software first has to write the 9 bit to SBUFH, then write

the low 8 bits to SBUF. As a result, the 9-bit data is stored into fifo. Controller of the IP samples the empty

state of transmit fifo. If the fifo is not empty, then read out a byte and send out. When the sending is over,

controller samples the empty state of transmit fifo again and goes into another sending process. During this

“sample-send-sample” process, there is no need for software control.



software, when the receive fifo is not empty, it can read data from the fifo. The 9th bit is available in bit0 of

“SBUFH” and the low 8 bits are in “SBUF”. Software read can be carried out only if the receive fifo is not

empty. Reading “SBUFH” has to be ahead of reading “SBUF”.

User Guide of UART


Ready to transmitnew data

Tx fifo full?

Write 9th bit to SBUFH

N

Y

Write lower 8 bits to SBUF(to Tx fifo)


Ready to readreceived data

Rx fifo empty?

Read 9th bit from SBUFH.bit0

N

Y

Read lower 8 bits (from SBUF)

Figure 3-11 serial port transmission/reception with fifo in mode 2


3.5.1 Non-fifo

The only difference between Mode 2 and Mode 3 is that in Mode 3 internal baud rate generator can be used

to specify the baud rate.

In mode 3 the Serial Port operates as asynchronous transmitter/receiver with 9 data bits and programmable

baud rate. “SRELH”, “SRELL” baud rate generator is used. Additionally the baud rate can be doubled with the

use of the “smod” bit of the “SMOD” register.


is a start bit (always 0), then 9 bits of data proceed where the 9th is taken from bit0 of the “SBUFH” register,

after which a stop bit (always 1) is transmitted. Writing to “SBUFH” has to be ahead of writing to “SBUF”.


at pin “rxdi”. Input data are available after completion of the reception in the “SBUF” register, and the 9th bit

is available as bit0 in the “SBUFH” register. During the reception, the “SBUF” and “SBUFH” bit0 remain

unchanged until the completion.

User Guide of UART




3.5.2 With fifo

With transmit fifo, software can write a large amount of data into fifo only when the fifo is not full. Because

the EMIF bus is 8-bit wide and the data is 9-bit wide, software first has to write the 9 bit to SBUFH, then write

the low 8 bits to SBUF. As a result, the 9-bit data is stored into fifo. Controller of the IP samples the empty

state of transmit fifo. If the fifo is not empty, then read out a byte and send out. When the sending is over,

controller samples the empty state of transmit fifo again and goes into another sending process. During this

“sample-send-sample” process, there is no need for software control.



software, when the receive fifo is not empty, it can read data from the fifo. The 9th bit is available in bit0 of

“SBUFH” and the low 8 bits are in “SBUF”. Software read can be carried out only if the receive fifo is not

empty. Reading “SBUFH” has to be ahead of reading “SBUF”.

User Guide of UART


Ready to transmitnew data

Tx fifo full?

Write 9th bit to SBUFH

N

Y

Write lower 8 bits to SBUF(to Tx fifo)


Ready to readreceived data

Rx fifo empty?

Read 9th bit from SBUFH.bit0

N

Y

Read lower 8 bits (from SBUF)

Figure 3-14 serial port transmission/reception with fifo in mode 3

3.6 Serial Port Multiprocessor Communication

The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface can be used for multiprocessor

communication.

When the “sm2” bit of the “SCON” register is set, the receive interrupt is generated only when the 9th

received bit (“rb8” of “SCON”) is 1. Otherwise, no interrupt is generated upon reception.

To utilize this feature to multiprocessor communication, the slave processors have their “sm2” bit set to 1.

The master processor transmits the slave’s address, with the 9th bit set to 1, causing reception interrupt in all

of the slaves. The slave processors’ software compares the received byte with their network address. If there

is a match, the addressed slave clears its “sm2” flag and the rest of the message is transmitted from the

master with the 9th bit set to 0. The other slaves keep their “sm2” set to 1 so that they ignore the rest of the

message sent by the master.

3.7 External Memory Interface (EMIF) Operation

EMIF Interface timing

EMIF is used to extend the MSS (MCU sub-system) memory, address 20000~7FFFFF, can be implemented with

Fabric.

The CME-M5 family provides synchronous and asynchronous EMIF for Fabric extended memory which has the

same data/address and control ports but have different timing waveforms. The synchronous or asynchronous

EMIF mode is selected by the parameter sync_mode_en.

User Guide of UART


Figure 3-15 EMIF read waveform

When reading, Fabric places the read data to memdatai bus and not outputs a valid “memack” after one or

several cycles until the fabric data is ready after the memrd is asserted.

Figure 3-16 EMIF write waveform

In write cycle, Fabric writes the memdatao to extended memory when the memwr is asserted and send a

valid “memack” to MSS on the next cycle

EMIF data bank operation

User Guide of UART


Figure 3-17 CME 8051 memory map

Figure 3-18 CME 8051 bank arrangement

As is shown in figure up, the common area starts at 0x0000H address and ends at 0x7FFFH. Bank 0 is not

available, it is physically the same memory spaces at the common area.

While code/xdata memory banking feature is enabled, the code/xdata memory address is composed of two

parts:

User Guide of UART


15 bit address

8bits from a bank switching register SW_REGISTER:

PAGESEL for code memory

D_PAGESEL for xdata memory

Figure 3-19 code/xdata memory address with banking

For more information of EMIF interface, please refer to:

http://www.agatelogic.com.cn/PDF/CME-M5_Family_FPGA_Simplified_Data_Sheet_EN.pdf

3.8 AHB Interface Operation

AHB Interface timing

1 2 3 4 5 6 7 8

addr1

addr1

2

data1

data1

TimeGen

hclk

hsel

haddr

htrans

hwrite

hready_out

hwdata

wen

wdata

Figure 3-20 Basic write transfer

http://www.agatelogic.com.cn/PDF/CME-M5_Family_FPGA_Simplified_Data_Sheet_EN.pdf

User Guide of UART


1 2 3 4 5 6 7 8

addr1

addr1

2

data1

data1

TimeGen

hclk

hsel

haddr

htrans

hwrite

hready_out

hrdata

ren

rdata

Figure 3-21 Basic read transfer

AHB interface UART address mapping

FP0

bfff_ffff

a000_0000

FP1

dfff_ffff

c000_0000

Figure 3-22 Address mapping

The ARM Core provides two groups of AHB Bus signals,AHB0 and AHB1, so there are two memory space for

user logic which are called as FP0 and FP1.It means that if you instantiate an ARM Core and choose the AHB0 ,

you must access your slaves on the address from a000_0000 to bfff_ffff, but if you connect the AHB interface

UART to AHB1, the slaves can be accessed on the address from c000_0000 to dfff_ffff.

3.9 Interrupt Operation

For this UART IP, in different application and configuration, interrupt request is different.

(1) With no fifo, the UART IP generate interrupt request(irq) after each transmission and reception complete.

User Guide of UART


(2) With fifo in transmit/receive data path, the UART IP generate interrupt request(irq) only when receive fifo

is not empty. Data written into transmit fifo will be sent out automatically without software’s control, so

there is no need for interrupt.

Table 2.24 and Table 2.25 are separately illustrates 8051and ARM external interrupt sources. For UART IP, the

interrupt will keep asserted when receive fifo is not empty. Obviously users should exploit level-sensitive

interrupt.

So, in 8051, external interrupt 0 and 1 can be used, but in ARM, there is a 16-bit external

interrupt :fp_interrupt[15:0]. Users can connect interrupt request with corresponding interrupt source and

8051 or ARM will follow the normal interrupt handle procedure to handle UART’s interrupt request.

Table 3-1 8051 external interrupt sources

Vector Type Polarity Alternate Port Description

0 I Low/Fall Port3i[2] External interrupt 0

2 I Low/Fall Port3i[3] External interrupt 1

9 I Fall/Rise Port1i[4] External interrupt 2

10 I Fall/Rise Port1i[0] External interrupt 3

11 I Rise Port1i[1] External interrupt 4




Table 3-2 ARM external interrupt sources

Interrupt Serve Function Type Alternate Port Description

Void FP0_IRQHandler(void) I fp_interrupt[0] External interrupt 0
















User Guide of UART


3.10 Resource Usage and Performance Analysis

Resource usage and performance of the UART IP on Primace

Table 3-3 UART IP resource usage and performance with EMIF interface

Resource LUTs Regs EMBs Performance

Value

(with no FIFO) 337 155 0 165M

Value

(with FIFO,

general data

read)

437 251 2 130M

Value

(with FIFO,

batch data read)

644 382 2 100M

Table 3-4 UART IP resource usage and performance with AHB interface

Resource LUTs Regs EMBs Performance

Value

(with no FIFO) 292 166 0 155M

Value

(with FIFO,

general data

read)

436 253 2 120M

Value

(with FIFO,

batch data read)

657 407 2 90M

User Guide of UART


4 Generate File Directory Structure

The UART IP wizard generated file includes: source files (src), simulation files(sim) and example design files.

The detailed design directory structure is as below

Project

src outputs ip_core

system_top.v(define by user)

serial_core.v

uart_fifo.v

syn_fifo.v

simsrc doc example

*.vp (Protected RTL)

CME_uart_user_guide_EN03

.pdf

CME_uart_example_user_guide_EN03.pdf

= directory

= source RTL code

= simulation related files

= documentation

uart_v3

ahb_uart_top.v

emif_uart_top.v

ahb_uart_fifo_ctl.v

emif_uart_fifo_ctl.v

emb_uart_m5.v

emb_uart_m7.v

emb_uart_hr3.v

src_vp

tb_m7

m7s_sim.v

uart_top_m7_tb.v

uart_top_m7_tb.do

uart_top_m7_tb_modelsim.f

sim_src

tb_m5

js_sim.v

uart_top_m5_tb.v

uart_top_m5_tb.do

uart_top_m5_tb_modelsim.f

*.v(arm simulation RTL)

tb_hr3

hr3_sim.v

uart_top_r3_tb.v

uart_top_r3_tb.do

uart_top_r3_tb_modelsim.f

ahb_example

uart_demo_batchrd

emif_example

uart_demo_single

uart_demo_multi-channel

Figure 4-1 IP wizard generated file directory structure

User Guide of UART


Table 4-1 Generated File Directory structure

Directory Description

src\ Directory for project source code, including IP wizard

generate code, for example: system_top.v, which

instantiate the UART IP and define related

parameters

ip_core\ The directory specially for all IPs

\uart_v3 Directory for UART IP

\doc\CME_uart_user_guide

_EN03.doc

User guide for UART IP

\src IP Design RTL

ahb_uart_top.v Uart top module with AHB interface

emif_uart_top.v Uart top module with EMIF interface

ahb_uart_fifo_ctl.v UART/memory control module of UART IP with AHB

interface

emif_uart_fifo_ctl.v UART/memory control module of UART IP with EMIF

interface

emb_uart_m5.v EMB module of UART IP for M5 device

emb_uart_m7.v EMB module of UART IP for M7 device

emb_uart_hr3.v EMB module of UART IP for HR3 device

serial_core.v Core control module of UART IP

uart_fifo.v Memory top module of UART IP

syn_fifo.v FIFO module of UART IP

\sim Design functional verification

\src_vp Encrypted source code for modelsim simulation

\tb_m7 Simulation files directory for M7 device

uart_top_m7_tb.v Test bench

uart_top_m7_tb_modelsim.f File list of simulation related file

uart_top_m7_tb.do For modelsim simulation

m7s_sim.v M7 simulation library

\sim_src Files for ARM core simulation

\tb_m5 Simulation files directory for M5 device

uart_top_m5_tb.v Test bench

uart_top_m5_tb_modelsim.f File list of simulation related file

uart_top_m5_tb.do For modelsim simulation

JS_sim.v JS simulation library

\tb_hr3 Simulation files directory for HR3 device

uart_top_r3_tb.v Test bench

User Guide of UART


uart_top_r3_tb_modelsim.f File list of simulation related file

uart_top_r3_tb.do For modelsim simulation

hr3_sim.v HR3 simulation library

\example

\emif_example

uart_demo_single example design for single channel application

uart_demo_multi-channel example design for multichannel application

\ahb_example

uart_demo_batchrd example design for batchread model application

CME_uart_example

_user_guide_EN03.pdf

User guide of example design

User Guide of UART


Revision History

Revision Date Comments

1.0 2012-12-12 Initial release

2.0 2013-03-22 Upgrade for 5,6,7,8-bit width & fifo support

2.1 2013-07-27 Batch data read and reception overtime control support

3.0 2014-04-22 Add AHB interface

optimus fabric interface specification...write/read control write/read control uart_fifo_ctl txd...

Documents