RESEARCH POSTER PRESENTATION DESIGN © 2012

www.PosterPresentations.com

Set-Top-Box(STB) SoC designs are extremely

complex with multi-million gates, higher core

utilization of around 75-80 %, and multiple clock

domains. Die-Area optimization of such SoCs becomes

a key challenge.

Our experience on these SoCs consistently

demonstrates that:

• The PDN (Power Delivery Network) lie well within

the IVD budget of 15% of supply voltage.

• We continue to see routing congestions which is

shared by both signal/clock due to PG grid

overdesign

• Using an early Power Grid Prototyping based

approach, we got results that predicted strong

potential for optimizing area of the die without

compromising on cost and performance.

In this work, we first leveraged an existing version of

the STB SoC and optimized the PDN to (a) quantify the

increased signal and routing resources created and (b)

its affect on IR drop. In the second phase, we

implemented these PDN optimization changes on a

shrinked version of the SoC and took it through the

PnR and timing closure flow to validate the area

recovery of these SoCs in production.

a) Phase 1- Optimizations using an existing version of

SoC

• Optimize M3 PDN for routing and tracks

availability for 7ML and 8ML stack configurations

of existing SoC. (M2-M7 stack via for PDN OR

M3-M7 stack via)

• Quantify the effect on IR when M7 pitch is made

2x to reduce PG stack-vias.

b) Phase 2- Reduced version of SoC (Die area reduced by

12%)

• Took the reduced version of the SoC through PnR,

Timing and IR for standard grid (M7 pitch 7.2u)

and optimized grid (M7 pitch 14.4u) to validate the

Area Recovery.

Motivation

The IVD analysis with M7 pitch 7.4u and 14.4u were done

using RedHawk-Grid Prototyping System tool, and the

worst IR drops were within budgets.

Atul Bhargava1, Abhishek Nigam1, Fabrizio Viglione2 ,Shiv Om Sharma1, Anant Narain3

Optimizing Existing PDN to Recover Area of SoC in Production

1STMicroelectronics, Noida, India 2STMicroelectronics, Grenoble, France3Ansys, Inc., Noida , India

Results and Findings

Methodology

Phase 1a: M3 PDN Routability Analysis:

Power Grid-A allows denser routing for all configurations

Phase 1b: Optimizing M7 PDN:

Grid AAvailable tracks per layer

M2(H): 10/16 (standard cell rails)

M3(V): 152/170 (M3 stripes, pitch 17u)

M4(H): 44/48 (stacked via)

M5(V): 152/170 (stacked via)

M6(H): 38/48 (stacked via)

Grid BAvailable tracks per layer

M2(H): 10/16 (standard cell rails)

M3(V): 82/90 (stacked via, pitch 9u)

M4(H): 12/16 (stacked via every 2 rows)

M5(V): 82/90 (stacked via)M6(H): 6/16 (stacked via every 2 rows)

Grid A

Total Available tracks:

112/144 = 77.8% (H)

304/340 = 89.4% (V)

Grid BTotal Available tracks:

28/48 = 58.3% (H)

164/180= 91.1% (V))

Routability Analysis for 8ML and 8T Libraries.

Phase 2: Reduced SoC – Routing Analysis

The SoC die-area was reduced while the area of the IP

remained the same. This increased routing demands near

the Hard IP regions and caused congestions at high-cell

density areas

Routing resources

demand at SoC level

Congestion at High

Cell Density area

Phase 2: Reduced SoC – routing analysis/congestions/timing and IR drop comparisons between standard M7 PG pitch (7.2u) SoC and 2x M7 PG pitch (14.4u) SoC.

Results and Findings

M7 pitch

7.2u

M7 pitch

14.4u

Congestion reductions in channels and notches with

2x M7 pitch due to reductions in M3-M7 PG stack

vias by 50%

M7 pitch

7.2u

M7 pitch

14.4u

Congestion reductions with 2x M7 pitch for same region

in two cases with the signal nets remaining the same in

two cases.

M7 pitch 7.2u

M7 pitch 14.4u

No timing impact with

2x M7 pitch !

M7 pitch 7.2u M7 pitch 14.4u

The IR drop with 2x M7 pitch

only increased by 5mV

(within budget)

• Die-Area optimization of STB SoCs has become a key challenge.

• A two-phase methodology and results for recovering die area of such SoCs in production has been presented.

• In first phase, we leveraged an existing version of the STB SoC and optimized the PDN for 8ML and 8T libraries.

• Our results demonstrate 77% available horizontal tracks with M3 PDN routing versus just 58% without it.

• Also the increase in IR drop is well within the 15% voltage drop budget when the M7 pitch is doubled to reduce the M3-M7 stack via density by 50%.

• In second phase, both the M3 PDN routing and 2x M7 PDN pitch are implemented on a reduced-area version of the same chip and taken through PnR, timing and IR flow to demonstrate the feasibility of recovering the area of the SoC without compromising on performance.

Summary