operating systems comp 4850/cisg 5550 page tables tlbs inverted page tables dr. james money

Operating SystemsOperating SystemsCOMP 4850/CISG 5550COMP 4850/CISG 5550

Page TablesPage TablesTLBsTLBs

Inverted Page TablesInverted Page Tables

Dr. James MoneyDr. James Money

PagingPaging

Page TablesPage Tables

• In the simplest cases, mapping of virtual In the simplest cases, mapping of virtual addresses happens as we have addresses happens as we have describeddescribed

• The virtual address is split into lower The virtual address is split into lower and higher order bitsand higher order bits

• The higher order bits are grouped into a The higher order bits are grouped into a page numberpage number

• Splits might be of 3 or 5 bits instead of 4Splits might be of 3 or 5 bits instead of 4


• The virtual page number is used as The virtual page number is used as an index into the page tablean index into the page table

• From the entry in the page table, the From the entry in the page table, the page frame number is foundpage frame number is found

• The page frame number is attached The page frame number is attached to the high order bits to determine to the high order bits to determine the physical addressthe physical address


• The main purpose of the page table The main purpose of the page table is to map virtual addresses to is to map virtual addresses to physical addressesphysical addresses

• Mathematically the page table is a Mathematically the page table is a function that takes a virtual page function that takes a virtual page number and returns a physical frame number and returns a physical frame numbernumber


• There are two major issues to There are two major issues to addressaddress– The page table can grow to be The page table can grow to be

extremely largeextremely large– The mapping of addresses must be fastThe mapping of addresses must be fast


• The reason for large page tables is b/c The reason for large page tables is b/c most computers have at least 32 bits and most computers have at least 32 bits and many now have 64many now have 64

• With a 4KB page size, a 32 bit address With a 4KB page size, a 32 bit address space has 1 million pagesspace has 1 million pages

• With a 64 bit address space, there are With a 64 bit address space, there are more than one can imaginemore than one can imagine

• Typically each process has its own page Typically each process has its own page table with it’s own virtual address spacetable with it’s own virtual address space


• The second point is needed b/c we do The second point is needed b/c we do the virtual-to-physical mapping must the virtual-to-physical mapping must be done with every memory be done with every memory referencereference

• Many times there are 1,2, or memory Many times there are 1,2, or memory references per instructionreferences per instruction

• If an instruction takes 4 nsec, the If an instruction takes 4 nsec, the lookup must not exceed 1 nseclookup must not exceed 1 nsec


• The simplest design is to have the The simplest design is to have the table as an array of fast hardware table as an array of fast hardware registers with an entry for each registers with an entry for each virtual pagevirtual page

• This requires no memory references This requires no memory references during mappingduring mapping

• This problem is this can be This problem is this can be expensive($$!!) and slow with a expensive($$!!) and slow with a context switchcontext switch


• The other end is to have the entire The other end is to have the entire page table in memorypage table in memory

• There is a single register that points There is a single register that points to start of the tableto start of the table

• Easy for a context switchEasy for a context switch

• Needs memory references to read Needs memory references to read page tablepage table

Multilevel Page TablesMultilevel Page Tables

• Many computers use a multilevel Many computers use a multilevel page system to alleviate the problempage system to alleviate the problem

• The basic idea is a two level tree with The basic idea is a two level tree with the top level being reference to leaf the top level being reference to leaf nodes with an array of page entriesnodes with an array of page entries

• We partition the 32 bit virtual We partition the 32 bit virtual address into a PT1 field, a PT2 field, address into a PT1 field, a PT2 field, and the Offset fieldand the Offset field


• The idea is to not keep all the leaf page The idea is to not keep all the leaf page tables in memory when they are not tables in memory when they are not neededneeded

• A page fault occurs when the top level A page fault occurs when the top level entry has the Present bit is clearentry has the Present bit is clear

• Either this is an illegal address or we need Either this is an illegal address or we need to allocate more pages to the processto allocate more pages to the process

• We can extend this scheme to three or We can extend this scheme to three or four levelsfour levels


• For example, consider referencing For example, consider referencing the virtual address 0x00403004the virtual address 0x00403004

• This corresponds to PT1=1, PT2=2, This corresponds to PT1=1, PT2=2, and Offset=4and Offset=4

• The MMU uses PT1 as an index into The MMU uses PT1 as an index into the top level table and PT2 as the the top level table and PT2 as the index into the appropriate second index into the appropriate second level tablelevel table

Page Table EntriesPage Table Entries

• We consider now the structure of a We consider now the structure of a single entry for a page tablesingle entry for a page table

• This is highly machine dependent, This is highly machine dependent, but roughly the same from machine but roughly the same from machine to machineto machine

• A common size for an entry is 32 bitsA common size for an entry is 32 bits


• The field containsThe field contains– Page frame numberPage frame number– Present/absent bitPresent/absent bit– Protection – what kind of access is Protection – what kind of access is

permittedpermitted– Modified/Referenced – keeps track of Modified/Referenced – keeps track of

writes and read to a page framewrites and read to a page frame– Caching disabledCaching disabled


• Note the disk address to hold the page is Note the disk address to hold the page is not in memory or part of the page tablenot in memory or part of the page table

• This is b/c the OS handles this This is b/c the OS handles this information internally in its software information internally in its software tablestables

• The page table only has to hold The page table only has to hold information on virtual -> physical information on virtual -> physical mappings for processesmappings for processes

TLBsTLBs

• Most paging systems keep page tables Most paging systems keep page tables in memory due to their large sizein memory due to their large size

• In register to register instructions, there In register to register instructions, there is no paging hitis no paging hit

• Since the rate of the memory access is Since the rate of the memory access is the limiting factor, making two the limiting factor, making two references reduces performance by 2/3references reduces performance by 2/3

TLBsTLBs

• The solution is based on the fact The solution is based on the fact there are a large number of close by there are a large number of close by memory referencesmemory references

• This results in a little number of page This results in a little number of page referencesreferences

• The rest are used rarelyThe rest are used rarely

TLBsTLBs

• The solution is to equip a device to The solution is to equip a device to handle the mapping without going handle the mapping without going through the page tablethrough the page table

• This device is called the This device is called the Translation Translation Lookaside Buffer (TLB)Lookaside Buffer (TLB) or associate or associate memorymemory

• This is kept inside the MMU and has a This is kept inside the MMU and has a small number of entries(8-64)small number of entries(8-64)

TLBsTLBs

TLBsTLBs

• How does this work?How does this work?• The MMU first looks in the TLB by The MMU first looks in the TLB by

comparing all entries simultaneouslycomparing all entries simultaneously• If an entry is found and the protection If an entry is found and the protection

is appropriate, then the entry is used is appropriate, then the entry is used without going to the page tablewithout going to the page table

• If there is a protection problem, then a If there is a protection problem, then a protection fault is issuedprotection fault is issued

TLBsTLBs

• If the entry is not in the TLB, the If the entry is not in the TLB, the MMU does a normal page lookupMMU does a normal page lookup

• It replaces an entry in the TLB with It replaces an entry in the TLB with the page lookup just issuedthe page lookup just issued

• If that page is used again, then it will If that page is used again, then it will read the page frame from the TLBread the page frame from the TLB

Software TLB ManagementSoftware TLB Management

• So far the management of the TLB So far the management of the TLB has been done by the MMU itselfhas been done by the MMU itself

• This was true in the pastThis was true in the past

• Many modern RISC CPUs do this Many modern RISC CPUs do this management in softwaremanagement in software

• On these systems, a TLB fault is On these systems, a TLB fault is issued for handling the TLB mississued for handling the TLB miss

Software TLB ManagementSoftware TLB Management

• The OS needs to find the page table The OS needs to find the page table entry, evict the least used one, and entry, evict the least used one, and load the new TLB entryload the new TLB entry

• This has to be done fast since there This has to be done fast since there are many TLB misses to a page faultare many TLB misses to a page fault

• If the TLB size is large(64), then If the TLB size is large(64), then there is no problem b/c the misses there is no problem b/c the misses are far in betweenare far in between


• With 32 bit computers, with 4KB page With 32 bit computers, with 4KB page size, a full table might require 4MBsize, a full table might require 4MB

• This can be a problem on 64 bit This can be a problem on 64 bit address systemsaddress systems

• We now need 2We now need 25252 entries entries

• If each entry is 8 bytes, we need to If each entry is 8 bytes, we need to use 30 million gigabytesuse 30 million gigabytes


• We need a different solutionWe need a different solution• One solution is called an One solution is called an inverted inverted

page tablepage table• In this design, there is one entry per In this design, there is one entry per

page frame in real memory rather page frame in real memory rather than one entry per virtual pagethan one entry per virtual page

• In the same scenario with 256MB of In the same scenario with 256MB of RAM, we need only 65536 entriesRAM, we need only 65536 entries


• Each entry keeps track of which Each entry keeps track of which (process,virtual page) belongs to the (process,virtual page) belongs to the frameframe

• Now the virtual to physical mapping Now the virtual to physical mapping is hard to performis hard to perform

• When a process references virtual When a process references virtual page page pp, it must search the inverted , it must search the inverted page table for an entry of the form page table for an entry of the form ((nn,,pp))


• The way around this again it to use The way around this again it to use the TLBthe TLB

• When the TLB holds the heavily used When the TLB holds the heavily used pages, then this work happens as pages, then this work happens as fast as regular page tablesfast as regular page tables

• However, on a miss, the search must However, on a miss, the search must be done in softwarebe done in software


• One way to do this search is to use a One way to do this search is to use a hash table with chaininghash table with chaining

• If the hash table has as many entries If the hash table has as many entries as frames, then the chains will only as frames, then the chains will only have one entry eachhave one entry each

• Once the entry is found, the entry is Once the entry is found, the entry is put in the TLBput in the TLB

operating systems comp 4850/cisg 5550 page tables tlbs inverted page tables dr. james money

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