www.opal-rt.com

Luc-André Grégoire, Wei Li March 13th, 2014

Modular Multilevel Converter (MMC)

HIL and RCP Solutions

2

Your Hosts

Presenter

Luc-André Grégoire

Simulation Specialist

OPAL-RT TECHNOLOGIES

Lead Demo

Wei Li

Lead Specialist, Power System

Simulation

OPAL-RT TECHNOLOGIES

Special Guest

Sébastien Dennetière

Power system engineer

RTE FRANCE

Jean Belanger

CEO & CTO

OPAL-RT TECHNOLOGIES

3

Darcy Laronde

Business development

OPAL-RT TECHNOLOGIES

3

Presentation Outline

• Introduction to Modular Multilevel Converter (MMC)

• Challenges of MMC in HIL

• Live demo: Real-Time / Fast Simulation of MMC

• Benefits and features of MMC solutions

• Modeling of MMC for the France-Spain link by RTE

• Vision MMC - Accuracy and Flexibility

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MMC business at OPAL-RT TECHNOLOGIES

• Founded in 1997, leading developer of open Real-Time Digital Simulators

and Hardware-in-the-loop testing equipment for:

o Electrical, electro-mechanical and power electronic systems.

o Headquarters: Montreal and regional subsidiaries in OPAL-RT Europe,

India and USA.

• OPALRT’s MMC Hardware-in-the-loop Simulation can emulate

MMC systems

• Our platforms can be interconnected to simulate several MMCs in real time

• MMC is becoming a more and more significant portion of our Global

Business

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MMC Customers

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customer site deliveryMMC model /

Hardwarecell number /Terminals

IO/protocol projects

ABB Switzerland 2012MMC FPGA model, MMC

controller/OP70008*6

2 terminals48 AO, 96 DI

Hardware-in-the-loop test controller

Alstom UK 2012 MMC cpu model /OP5600100*6

2 terminalsno Fast simulation

China South Grid (CSG) China2013

MMC FPGA model/OP7020

200*63 terminals

AuroraSimulation a real 3-terminal

MMC HVDC project and validation its controller

China Electric Power Research Institute

(CEPRI)China 2013

MMC FPGA model/OP7000

500*62 terminals

noSimulation of a 3-terminal MMC

HVDC project

Nari-Relays (NR)phase 1

China 2011MMC CPU and fpga

model/OP5600+ML60550*6

2 terminals

48*6 AO, 96*6 D3200 IO in total

25 microsIHardware-in-the-loop test

Nari-Relays (NR)phase 2

China 2013MMC fpga model/

10 VIRTEX7 OP7020250*6

5 terminalsAurora/Gigabit

HIL Simulation of a 5-terminal MMC HVDC project

XJ Group phase 1 China 2013 MMC controller/OP70205 terminals

IO Rapid Control Prototyping (RCP)

State Power Economic Research Institute

(SPERI) China 2013

MMC controller/OP702010 VIRTEX7 OP7020 5 terminals

AuroraHIL Simulation of a 5-terminal

MMC HVDC project

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Introduction to MMC

67

Cells output can either be the capacitor voltage or zero. The sum of all the cells from 1

arm equals two times the HVDC bus, at any given time there is only half of the cell with

there capacitor voltage at there output.

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Introduction to Modular Multilevel Converter (MMC)

78

Two Basic Cell Topologies for High-Power Converters

Half-Bridge

- Most popular

- Difficulties to eliminate DC-bus fault

Full-Bridge

- More losses

- Bus capable to eliminate DC-buss faultVcap

+

-

Vab

+

-

A

B

ISM

T1

T2

T3

T4

8

Introduction to Modular Multilevel Converter (MMC)

89

Advantages and Disadvantages vs Traditional Thyristor-based converters

Advantages

- Reduced stress on converter and grid component

- Redundancy of the model increases its reliability

- VSC allows easier power flow control

- Very fast recovery on fault to stabilize power grids

- Can feed loads without any generators (no limit on short-

circuit ratio)

- Easy and start-up

- Smaller foot print

- No filters

Disadvantages

- Requires more components

- Control more complex

- Limited power capability

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Challenges of MMC in HIL- Model computation

910

Equations for each

- Reactive component (state-space solver).

- Node (Nodal approach)

Equations need to be recomputed at each switching instant

1 cell == 1 state or 2 nodes

1 arm == 100 cells == 102 states or 201 nodes

3 arms == 300 cells == 306 states or 603 nodes

10

Challenges of MMC in HIL- IO management

1011

For a small converter

IO requirements

1 cell :

- 2 digital inputs

- 1 Analog output

300 cells

- 600 digital inputs

- 300 analog outputs

Can be replaced by high

speed optical IO

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Challenges of MMC in HIL- IO management

1112

For a small converter

25µs 50µs 0 µs

t

Inputs

ModelCalc.

Outputs

RCP: Converter measurement

HIL: Gating signalRCP: Control law

HIL: Real-time simulation

RCP: Gating signal

HIL: Converter measurement

500ns 1µs 0 ns

t

12

Demo System

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Description of Parameters Value

Grid frequency and voltage 50 Hz, 230 kV

Transformer power rating 280 MVA

Transformer voltage ratio 230 kV / 100 kV

Transformer impedance 10%

Arm Impedance 24 mH

MMC power rating 200 MVA

Number of SM per valve in MMC 250

SM capacitance 24 mF

DC link Voltage ± 100 kV

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MMC FPGA model

MMC valve controlVoltage balancing control + gating signal generation

MMC255*6 SM

Se

lecto

r k1

Gating

Signals

to MMC

FPGA

Protocol drive (or IO drive)

Selector k2

Gating

Signals

from CPU

Gating signals by

valve control

SPF or IO

Reference

from CPU

Gating signals

to protocol

Target

Gating signals

from protocol

Se

lecto

r k3 Capacitor voltage

Capacitor Voltage

from Protocol

MMC & system

Measurements

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14

Fiber optic

Gating signals

by valve

control

Gating

Signals

to MMCMMC valve

controlMMC

Sele

cto

r k1

FPGA 1

Protocol drive

Selector k2

Gating

Signals

from CPU

SPF

Reference

from CPU

Gating signals

to protocolGating signals

from protocol

Sele

cto

r k3

Capacitor voltage

Capacitor Voltage

from Protocol

MMC

Sys.

Meas.

Gating

Signals

to MMCMMC valve

control MMC

Sele

cto

r k1

FPGA 2

Protocol drive

Selector k2

Gating

Signals

from CPU

Gating signals

by valve

control

SPF

Reference

from CPU

Gating signals

to protocolGating

signals

from protocol

Sele

cto

r k3

Capacitor voltage

Capacitor Voltage

from Protocol

MMC

Sys.

Meas.

GridPole ctrlTarget 1 Target 2I/O I/OCopper wiring

Simulating MMC in FPGA (External Control)

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Simulating MMC in FPGA (External Control)

Fiber optic

Gating signals

by valve

control

Gating

Signals

to MMCMMC valve control

MMC

Sele

cto

r k1

FPGA 1

Protocol drive

Selector k2

Gating

Signals

from CPU

SPF

Reference

from CPU

Gating signals

to protocolGating signals

from protocol

Sele

cto

r k3

Capacitor voltage

Capacitor Voltage

from Protocol

MMC

Sys.

Meas.

Gating

Signals

to MMCMMC valve

control MMC

Sele

cto

r k1

FPGA 2

Protocol drive

Selector k2

Gating

Signals

from CPU

Gating signals

by valve

control

SPF

Reference

from CPU

Gating signals

to protocolGating

signals

from protocol

Sele

cto

r k3

Capacitor voltage

Capacitor Voltage

from Protocol

MMC

Sys.

Meas.

GridPole ctrlTarget 1 Target 2I/O I/OCopper wiring

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16

Test bench setup

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MMC HIL and RCP and its applications

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Real-Time or faster than real-time MMC simulation for:

• Concept validation – Grid and Converters

• Control/protection system design and optimisation

• Stress analysis on power grid and converter components (arrestor sizing etc.)

• Monte carlo analysis

• Research work

• Academic application

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MMC HIL and RCP and its applications

1819

• Rapidly build a demonstration prototype

• Validate control algorithms

• MMC model validation

• De-risk control design

• Detect design faults

Rapid control prototyping with physical plant

RCP MMC real-time simulation to:

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MMC HIL and RCP and its applications

1920

• Controller validation

• Validate destructive test sequence without damaging physical material

• Control research and development in laboratory environment

• Controller production verification

Hardware-in-the-loop

HIL MMC real-time simulation connected to control system replica for:

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MMC Typical HIL Configuration

• Capable of simulating up to 1500 MMC

sub-modules

• Supports 16 SFP and SFP+

transceivers multi-mode fiber modules

• 20-Gbits/s PCI Express x4 links to

interface with any OPAL-RT real-time

simulator

OP7020Virtex 7 FPGA Processor Expansion Unit

0

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MMC Typical HIL Configuration

• Capable of simulating up to 1500 MMC

sub-modules

• Supports 16 SFP and SFP+

transceivers multi-mode fiber modules.

• 20-Gbits/s PCI Express x4 links to

interface with any OPAL-RT real-time

simulator

• Up to 8 signal conditioning & A/D

converter modules with 16 or 32

channels each

OP5607Virtex 7 FPGA Processor & I/O Expansion Unit

0

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Key Benefits and Features

• MMC FPGA models include up to 511 submodules per valve, 6

valves per FPGA, and run at 500ns

• MMC FPGA modules include features such as: cells short-circuit

fault, AC fault and DC fault

• FPGA model can also be coupled directly with SFP optical fiber

(Small Form-factor Pluggable)

• Total bandwidth selectable between 1 and 5 Gbits/s

• Minimum latency of 250 ns

• Total update time with actual controller smaller than 4 micros

with more than 511 sub modules per optical fiber pairs

• HIL system architecture allow easy I/O expansion

• OPAL-RT MMC open protocol using Aurora or Gbit Ethernet

• Possibility to implement custom protocol

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Modeling of Modular Multilevel Converters for the France-Spain link

Sébastien Dennetière (RTE)

INELFE project: France-Spain ELectrical INterconnection

Santa

Llogaia

Baixas

A 2000 MW - 65 km underground cable – DC link connecting Baixas (near Perpignan, France) and Santa Llogaia (near Figueras, Spain)

Santa Llogaia

Baixas

Tunnel

Modeling of Modular Multilevel Converters for the France-Spain link24

Scope of the project

Rated power: 2*1000 MW

DC voltage: ±320 kV for each 1000MW link

Reactive Power Control: +/- 300 MVAR for each 1000MW Converter

Converter Contractor : Siemens

DC cable length: 64 km

Cable Contractor: Prysmian8 km dedicated Tunnel

Commissioning date: 2015

Cost of the Project : 700M€

with 225M€ financing from EU

GAUDIERE

BAIXAS

VIC

RIUDARENES

BESCANO

SANTA LLOGAIA

RAMIS

FRANCESPAIN

HV

DC

LIN

K1

HV

DC

LIN

K2

+

-

+

-

BAIXASSANTA

LLOGAIA

Modeling of Modular Multilevel Converters for the France-Spain link25

Modeling of MMC for Rte

INELFE is the first VSC installation operated and maintained by RTE

Many HVDC projects in the future on the French grid…

Competences in modeling and simulation of VSC based equipment were required in RTE

Manufacturers models are black box and are provided at the end of the project

Collaborations with Ecole Polytechnique de Montréal (CA)

and Ecole Centrale de Lille (FR) to develop generic MMC models for EMT studies

Modeling of Modular Multilevel Converters for the France-Spain link26

VSC MMC topology for INELFE

SM 1

SM 2

SM n

SM 1

SM 2

SM n

SM 1

SM 2

SM n

SM 1

SM 2

SM n

SM 1

SM 2

SM n

SM 1

SM 2

SM n

3

2

6

+320kV

-320 kV

4

56

2

3

4

5

Insertion resistors

Star point reactor

Arm reactor

Multi-valve arm

Converter transformer

1

1 SubmoduleS1

S2C ~400 SM

Detailed modeling of such converters is very challenging :

improve numerical techniques develop simplified models

Modeling of Modular Multilevel Converters for the France-Spain link27

Modeling of Modular Multilevel Converters for the France-Spain link

Type of Converter models

Description from converter topologies to semi conductors

Full detailed models – model1

28

Id

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

Vd

Ls

LsLsLs

Ls Ls

Sub-

Module

Multi-

valve

Arm

iua

ibic

vc

iub iuc

ila ilb ilc

vsua

vb

iava

vsla

p

n

gS1

S2

C

K2K1

0 1000 2000 3000 4000 5000 60000

0.2

0.4

0.6

0.8

1

Current (A)

Voltage (

V)

+

n

p

g

Simulation time for a 1s simulation in EMTP-RV ~ 3.5h (t=10µs)

Detailed equivalent models

Id

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

SM-1

SM-2

SM-400

:

Vd

Ls

LsLsLs

Ls Ls

Sub-

Module

Multi-

valve

Arm

iua

ibic

vc

iub iuc

ila ilb ilc

vsua

vb

iava

vsla

SMv t

MVi t

_SM eqr t

_SM eqv t T

++

_1

_1

SM

eq

v t

r t

_ 2

_ 2

SM

eq

v t

r t

_ 3

_ 3

SM

eq

v t

r t

_ 4

_ 4

SM

eq

v t

r t

_ 5

_ 5

SM

eq

v t

r t

_ 6

_ 6

SM

eq

v t

r t _ 6eqr t

_ 5eqr t

_ 4eqr t

_3eqr t

_ 2eqr t

_1eqr t

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+ + +

DC_PLUS

DC_MINUS

a

b

cAC

A solution to limit number of internal nodes – model2

Simulation time for a 1s simulation in EMTP-RV ~7.5min (t=10µs)

Modeling of Modular Multilevel Converters for the France-Spain link29

Models validation – comparison against full detailed model

3-phase AC fault

Saad, H.; Dennetière, S.; Mahseredjian, J.; Delarue, P.; Guillaud, X.; Peralta, J.; Nguefeu, S., "Modular Multilevel Converter Models for Electromagnetic Transients," IEEE Transactions on Power Delivery, Nov 2013

Modeling of Modular Multilevel Converters for the France-Spain link30

0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4-1.5

-1

-0.5

0

0.5curr

ent

(pu)

time (s)

0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.40.95

1

1.05

1.1

1.15

voltage (

pu)

time (s)

Model 4

Model 1, 2 and 3

Model 4

Model 1 and 2 Model 3

0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4-1.5

-1

-0.5

0

0.5

curr

ent

(pu)

time (s)

0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.40.95

1

1.05

1.1

1.15

voltage (

pu)

time (s)

Model 4

Model 1, 2 and 3

Model 4

Model 3Model 1 and 2

1.85 1.9 1.95 2-5

0

5

curr

ent

(pu)

time (s)

1.85 1.9 1.95 20

5

10

curr

ent

(pu)

time (s)

Model 4

Model 1, 2 and 3

Model 1, 2 and 3

Model 4

Zoomed

1.898 1.9 1.902 1.904 1.9060

2

4

6

8

curr

ent

(pu)

time (s)

1.898 1.9 1.902 1.904 1.9060

2

4

6

8

curr

ent

(pu)

time (s)

Model 1, 2 and 3

Model 4

DC pole-to-pole fault

DC voltage and current

DC current

Conclusions

Generic models to have a better understanding of MMC

MMC models for EMT studies during and after the project

Models presently available in EMTP-RV – based on generic control systems and validated against results given by manufacturers

Next steps

Models suitable for Real-time simulation and connected to control system replica collaboration with OPAL-RT and Hydro-Québec to

develop very accurate MMC models for real-time simulation

Studies with control system replica connected to Hypersim real-time simulator to test dynamic performances

to validate and maintain offline modelsto perform HVDC studies

Modeling of Modular Multilevel Converters for the France-Spain link31

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VISION MMC : Accuracy and Flexibility

Better Model Accuracy and Flexibility (2014Q2)• All arm inductors and transformer leakage inductors simulated

with a time step of 500 nanos or lower on FPGA chips• Better accuracy during special pulse blocking conditions

• Better accuracy during natural rectification mode

• Better accuracy of fault transients on the converter side

• Better arrestor simulation (MMC side and DC bus arrestors)

• Easier to simulate complex back-to-back converters

Better Model Accuracy (2014Q4)• Transformer saturation effect simulated at 500 ns

• Frequency dependent line and cable models simulated at 1 µs

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VISION MMC : Lower Cost

To provide smaller but powerful MMC simulators for R&D, initial design and teaching

Fast/real-time simulation:

• HYPERSIM – 50 3-phase busses on 2 INTEL core

(20 to 50 us)

• High-Level MMC SIMULINK Controller on 1 Intel core

• Low-Level Cell controller on FPGA

• Up to 1500 MMC cells on one KINTEX 7 FPGA

(500 ns)

• Controller and MMC cell signal are interfaced inside the

FPGA chip (no external IO)

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VISION MMC : Lower Cost

To provide smaller but powerful MMC simulators for R&D, initial design and teaching

Real-time simulation of the grid and MMC converters

• HYPERSIM – 50 3-phase buses on 2 INTEL core

• MMC SIMULINK Controller on 1 Intel core

• Up to 1500 MMC cells on one KINTEX 7 FPGA

MMC Control Prototyping System

• High-Level MMC SIMULINK Controller on 1 to 3 Intel cores

• Low-level MMC controller on one KINTEX 7 FPGA

• Can include all control and protection functions used in

industrial MMC controllers

• Some MMC manufacturers already use the same architecture

(INTEL + KINTEX7 FPGA)

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VISION MMC : Lower Cost

To provide smaller but powerful MMC simulators for R&D, initial design and teaching

OP4500

optical fibers

(up to 4 SFP)

MMC Control Prototyping System

• High-Level MMC SIMULINK Controller on 1 to 3 Intel cores

• Low-level MMC controller on one KINTEX 7 FPGA

• Can include all control and protection functions used in industrial MMC

controllers

• Some MMC manufacturers already use the same architecture (INTEL +

KINTEX7 FPGA)

PHYSICAL

SET UP AND PHIL (Grid and

MMC)

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ACTUAL: Integrated Power Electronic LAB

EXT CNTR

Bench 1

Bench 2

Bench 3

Bench 4

5-Gbits optical fiber pair

Standard PCs (12, 24 cores or 32 cores)

PCI Express 4x

University Sheffield UK

(delivery April 2014)

Bench 5

OP5607Virtex 7 FPGA Processor & I/O Expansion Unit

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CONCLUSION

• OPAL-RT TECHNOLOGIES established a global leadership on MMC HIL and RCP solutions over the last three years.

• OPAL-RT TECHNOLOGIES is in active discussion for future MMC projects over 5 continents.

• OPAL-RT TECHNOLOGIES provides specific MMC hardware and software expertise as well as service from experienced engineers.

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OPAL-RT’S UPCOMING EVENTS

Montreal | June 9 – 12, 2014• Call for Paper deadline extended - See topics

http://www.opal-rt.com/realtime2014/registration/call-for-papers/

• Conference Registration: http://www.opal-rt.com/realtime2014/registration/

IEEE PES T&D in Chicago | April 14-17, 2014• Visit OPAL-RT at Booth 9123

More info at http://www.opal-rt.com/Events

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Thank you for your attention

This presentation will be available shortly on www.opal-rt.com

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