opal-rt real time simulation using rt-lab

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Real-Time Simulation of Renewable Energy Systems Using RT-LAB Presented by Andy Yen [email protected] Montréal, Canada ©2013 OPAL-RT - June 24 th , 2013 From Imagination to Real-Time IEEE COMPEL 2013 The 14th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL)

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Real-Time Simulation of Renewable Energy Systems Using RT-LAB, by OPAL-RT

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Page 1: OPAL-RT Real time simulation using RT-LAB

Real-Time Simulation of Renewable Energy Systems

Using RT-LAB

Presented by Andy Yen

[email protected]

Montréal, Canada

©2013 OPAL-RT - June 24th, 2013

From Imagination to Real-Time

IEEE COMPEL 2013

The 14th IEEE Workshop on Control and

Modeling for Power Electronics (COMPEL)

Page 2: OPAL-RT Real time simulation using RT-LAB

2

When we think about environment and energy, we think:

– Electric Vehicle

– Hydro Power

– Wind Power

– Photovoltaic Power

– Renewable Energies

Power Engineers think about:

– How to control

– How to bring this technology quickly to market

– How to distribute power

– How to interconnect

Introduction

Page 3: OPAL-RT Real time simulation using RT-LAB

3

Context

Modelling Challenges for Renewable Energy Systems

Solution

Specialized models

Summary

Outline

Page 4: OPAL-RT Real time simulation using RT-LAB

Context : Real-Time Simulation Helps in Development Process

4

Rapid Control Prototyping Hardware in-the-loop Testing

Desktop Simulation

Coding

Validation

Page 5: OPAL-RT Real time simulation using RT-LAB

Context : Controlled System, and Real-Time Simulation

5

Plant Controller

Rapid Control Prototyping Hardware-in-the-loop Simulation

Page 6: OPAL-RT Real time simulation using RT-LAB

6

Electric Drive for Hybrid Electric Vehicle and Electric Vehicle

Modular Multilevel Converter (MMC) for HVDC Connection

Wind farms, Photovoltaic Systems to Grid Connection

Renewable Energy Systems

Page 7: OPAL-RT Real time simulation using RT-LAB

7

Example figure : PMSM motor for electric vehicle model

Reduce latency

– Protection – Fast response needed

– High speed – Fast rotating machine

– Precision – Position of the rotor

Challenges for Electric Drive

Page 8: OPAL-RT Real time simulation using RT-LAB

Typical MMC HVDC circuit

MMC response to a short circuit

fault at transformer primary side

8

Challenges for Modular Multilevel Converter

Large number of

Inputs/Outputs managements

Wikipedia

Page 9: OPAL-RT Real time simulation using RT-LAB

9

Numerous converters

Fast switching

Short Transmission Lines

Challenges for Micro-Grid

Vgrid

A

B

C

a

b

c

Three-Phase Breaker

A

B

C

A

B

C

Resistance: RiInductance: Li

A

B

C

A

B

C

Three-PhaseSeries RL

Resistance: RiInductance: Li

A

B

C

A

B

C

Three-PhaseResistance

Resistance: Rgrid

A

B

C

A

B

C

Three-PhaseParallel RL

Inductance : LgridResistance : Rdamp_Lgrid

A

B

C

A

B

C

Three-PhaseInductance

Inductance: La

Capacitance:DClink_CResistance:DClink_R

+

-

PV Subsystem

DeltaCapacitance : Cf

g

A

B

C

+

-

g

A

B

C

+

-

2-level IGBT/Diode

Page 10: OPAL-RT Real time simulation using RT-LAB

10

Low Latency

High resolution – Small Time Steps

Non-averaged model

Fault capabilities

Transient analysis

Higher Harmonics effect

Solution : FPGA-based simulation

FPGA

Page 11: OPAL-RT Real time simulation using RT-LAB

11

FPGA are more difficult to program

Modeling via Block Diagram

Generating bitstream is long

(typical: 120 min + )

Flashing FPGA firmware is long

~15 mins

FPGA-based Simulation with eHS

Easier to program

Flexibility

Save bitstream generation time

Save reprogramming time

Difficulties Want

Page 12: OPAL-RT Real time simulation using RT-LAB

Fast and versatile architecture

12

Workstation Multicore

CPU

FPGA

firmware System Under

Control

Ethernet PCIExpress

Analog I/O

Digital I/O

Real-Time Computer

Page 13: OPAL-RT Real time simulation using RT-LAB

≈ 2 μs

CPU and FPGA-based Simulation Platform

Re

al-T

ime

Sim

ula

tor

CPU-Based Simulation

Controller Firing Pulses Measurements

Analog Outputs Digital Inputs

FPGA

(IO management)

CPU

25 μs model step

≈ 50-100 μs

Analog Outputs Digital Inputs

FPGA

CPU

FPGA-Based Simulation

Controller Firing Pulses Measurements

Re

al-T

ime

Sim

ula

tor

0.25 μs model step

Page 14: OPAL-RT Real time simulation using RT-LAB

FPGA

14

eHS (electrical Hardware Simulation) solver

– Generic Power Converter solver on FPGA

– SPS model editor interface (Soon with PLECS, PSIM and EMTP-RV)

– Reconfigurable from Host PC without reprogramming the FPGA

– Simulation in off-line mode with eHS nodal solver within Simulink

eHS Key Features

Automatic Model Generation

eHS

Automatic generation of

electric circuit model:

No Mathematical Modeling

No FPGA expertise

No VHDL programming

Circuit Editor (SPS, PLECS, …)

Page 15: OPAL-RT Real time simulation using RT-LAB

eHS uses the modified nodal analysis approach

– It solves a admittance matrix to find the voltage at each node and the current from each sources.

– The admittance matrix does not need to be re-computed for each switch status

– Simulated model topology and parameters can be modified without recompiling the bitstream

The maximum size of the circuit is determined by the number of inputs,

switches and reactive components

Currently, the maximum number of components is :

– 16 inputs (voltage/current sources)

– 16 outputs (voltage/current measurements)

– 24 switches (IGBTs, breakers, etc)

– 60 non-switching devices (ie. L and C) – unlimited resistors

eHS Nodal Solver

eHS core Y[0:15]

24x switches control

16x Inputs U[0:15]

S[0:23] 16 Measurements

Page 16: OPAL-RT Real time simulation using RT-LAB

eHS method replaces switches by:

– either a very small inductance when conducting

– or a very small capacitor when not conducting

This method is called the fix-Y because the admittance matrix does not change

when a switch changes state.

Switch Model in eHS

h is the time step

Page 17: OPAL-RT Real time simulation using RT-LAB

For the matrix to remain the same upon switching event, the following equation

must remains true

Gs=hL =C

h where h is the time step

When building the nodal matrix a value between 10 and 0.001 has to be set to

represent a switch. This determines the value of the inductor and the capacitor

representing the switch.

L=hGs C=h × Gs

For example, a time step 100ns and a Gs=1, the switch will be represented by the

following inductance when conducting or the following capacitance when non-

conducting.

L=hGs = 100ns

1 = 100nH C=h × Gs=100ns × 1=100nF

Ideally, we need a very small inductor and a very small capacitor to represent a ideal

switch. Depending of the circuit topology, the best result is obtained by optimizing

the value of Gs and compare results with conventional off-line software.

Switch Model in eHS

Page 18: OPAL-RT Real time simulation using RT-LAB

18

FPGA are more difficult to program

Modeling via Block Diagram

Generating bitstream is long

(typical: 120 min + )

Flashing FPGA firmware is long

~15 mins

FPGA-based Simulation with eHS

Easier to program

Flexibility, freedom to change circuit topology

Save bitstream generation time

Save reflashing time

On-line modification of circuit parameters

On-line modification of circuit topology

Difficulties Want

Page 19: OPAL-RT Real time simulation using RT-LAB

eHS model : PV connected to grid.

Time Step = 500ns

4 sources inputs (1 DC from PV, 3 phases AC from Grid)

16 voltage and current measurements,

15 switches (2x 2level inverters & 3phase breaker)

CPU (20 μs) FPGA (500 ns) CPU

Vgrid

A

B

C

a

b

c

Three-Phase Breaker

A

B

C

A

B

C

Resistance: RiInductance: Li

A

B

C

A

B

C

Three-PhaseSeries RL

Resistance: RiInductance: Li

A

B

C

A

B

C

Three-PhaseResistance

Resistance: Rgrid

A

B

C

A

B

C

Three-PhaseParallel RL

Inductance : LgridResistance : Rdamp_Lgrid

A

B

C

A

B

C

Three-PhaseInductance

Inductance: La

Capacitance:DClink_CResistance:DClink_R

+

-

PV Subsystem

DeltaCapacitance : Cf

g

A

B

C

+

-

g

A

B

C

+

-

2-level IGBT/Diode

19

Real-Time eHS Simulation Examples

CONTROLLERS (On CPU, FPGA or using external hardware)

Page 20: OPAL-RT Real time simulation using RT-LAB

20

Results for PV model

Real-Time eHS Simulation

Page 21: OPAL-RT Real time simulation using RT-LAB

21

Standard architecture of OPAL-RT RT-LAB simulator and RCP system

Mixed CPU-FPGA-based Multi-Rate Simulation Platform

≈ 2 μs

Analog Outputs Digital Inputs

FPGA

CPU

Actual Controller

Firing Pulses Measurements

Re

al-T

ime

Sim

ula

tor

0.25 μs model step

10 μs to 100 μs model step

≈ 20-30 μs

Complex grid and mechanical models and controllers

communication systems

≈ 2 μs

Analog Outputs Digital Inputs

FPGA

CPU

RT-LAB Prototype Controller

Firing Pulses Measurements

0.25 μs model step

10 μs to 100 μs model step

≈ 20-30 μs

Complex grid and mechanical models and controllers

communication systems

Low Latency

Small

time step

For fast Power

Electronic

Larger

time step

For grid and

mechanical

subsystems

Page 22: OPAL-RT Real time simulation using RT-LAB

22

MMC Solver

Specialized Models

≈ 2 μs

Analog Outputs Digital Inputs

FPGA

CPU

FPGA-Based Simulation

Controller Firing Pulses Measurements

Re

al-T

ime

Sim

ula

tor

0.25 μs model step

Page 23: OPAL-RT Real time simulation using RT-LAB

23

Motor model on FPGA

– Using Finite Element Analysis (FEA) modeling approach:

• Such as JMAG-RT and MotorSolve

Specialized Models

Flux, impedance values according to

the mechanical angles of the motors

Page 24: OPAL-RT Real time simulation using RT-LAB

24

Comparative results :

Specialized models

Torque control results at high currents (saturation)

-50

0

50

Cur

rent

s (A

)

0 0.005 0.01 0.0150

5

10

15

Time (s)

Torq

ue (N

.m.)

DQ (fixed Ld-Lq)

VDQ

SH

(Ld=1.43 mH Lq=2.34 mH)(Ld=1.53 mH Lq=2.5 mH) (Ld=1.45 mH Lq=2.45 mH)

motor file: '10k_D_C_I-.rtt'motor speed: 4000 RPM

VDQ torque= 12.7 N.m.

DQ torque=13.7 N.m.

SH average torque= 12.5 N.m.

Iref=20A (beta=0) Iref=40A (beta=40 deg)Iref=30A (beta=0)

Page 25: OPAL-RT Real time simulation using RT-LAB

CPU

25

eHS Real-Time (eFPGAsim, Virtex 6)

– Ac side & Converter: 400 ns

– Inverter & Filter: 690 ns

– FPGA PMSM motor: 100ns

Real-Time FPGA-based Simulation Example

− Inverter switching frequency = 8 kHz

− Converter switching frequency = 4 kHz

eHS FPGA eHS FPGA FPGA

M

INVP

N

TB L3_U0

L3_V0

L3_W0

C_UV

C_VW

C_WU

Sine-Wave Filter

MotorL3_U0

L3_V0

L3_W0

C_UV

C_VW

C_WU

L3_U0

L3_V0

L3_W0

PowerSource

INPUT FILTER

CNV

3-level Invertor

OUTPUT FILTER

M

INVP

N

TB L3_U0

L3_V0

L3_W0

C_UV

C_VW

C_WU

Sine-Wave Filter

MotorL3_U0

L3_V0

L3_W0

C_UV

C_VW

C_WU

L3_U0

L3_V0

L3_W0

PowerSource

INPUT FILTER

CNV

Trans former

L1

L1

L1

L2

L2

L2

C

C

C

L

L

L

C

C

C

Load

Page 26: OPAL-RT Real time simulation using RT-LAB

Real-Time FPGA-based Simulation Example

26

eHS and SPS superimposed

eHS and SPS superimposed

zoomed

Motor voltage (Phase-to-phase)

Motor current

zoomed

8-kHz components due to the 8-kHz PWM carrier

Page 27: OPAL-RT Real time simulation using RT-LAB

27

Non-Flashing technology:

– 1 firmware by application which handle

a large number of configuration

Multiple configurations:

– Generic Power Systems solver

– Modification in a model editor

– Reconfigurable from the host PC

OPAL-RT FPGA-based Simulation

Page 28: OPAL-RT Real time simulation using RT-LAB

28

Flexible I/O routing and configuration

OPAL-RT Real-Time Simulation

Page 29: OPAL-RT Real time simulation using RT-LAB

29

Flexible I/O routing and configuration

OPAL-RT Real-Time Simulation

Page 30: OPAL-RT Real time simulation using RT-LAB

30

Flexible I/O routing and configuration

OPAL-RT Real-Time Simulation

Page 31: OPAL-RT Real time simulation using RT-LAB

31

FPGA-based Simulation has many advantages over regular CPU-based

simulation

High Resolution Simulation

Low Latency

With OPAL-RT’s eFPGAsim, modelling is :

Easy

Reliable

Flexible

Customizable

Summary

FPGA ≈ 2 us

Analog Outputs Digital Inputs

FPGA

CPU

Controller Firing Pulses Measurements

Re

al-T

ime

Sim

ula

tor

0.25 us model step

Page 32: OPAL-RT Real time simulation using RT-LAB

32

Cover the complete spectrum of power system analysis & studies

ePOWERgrid Product Family

ePHASORsim Real-Time Transient

Stability Simulator 10 ms time step

NEW

HYPERsim Large Scale Power System

Simulation for Utilities & Manufacturers 10 µs to 100 µs time step

NEW

eFPGAsim Power Electronics Simulation on FPGA 1 µs to 100 ns time step

NEW

1 s (1 Hz)

10,000

5000

2500

1000

100

10

0

10 ms (100 Hz)

50 µs (20 KHz)

10 µs (100 KHz)

1µs (1 MHz)

100 ns (10 MHz)

10 ns (100 MHz)

20,000

Period (frequency) of transient phenomena simulated

Number of

Nodes

eMEGAsim Power System & Power Electronics Simulation

Based on Matlab/Simulink and SimPowerSystem 7 µs to 100 µs time step

Page 33: OPAL-RT Real time simulation using RT-LAB

OPAL-RT Democratize Real-Time Simulation

33

Page 34: OPAL-RT Real time simulation using RT-LAB

Real-Time Simulation of Renewable Energy Systems

Using RT-LAB

Presented by Andy Yen

[email protected]

Montréal, Canada

From Imagination to Real-Time

Thank you !

©2013 OPAL-RT - June 24th, 2013

IEEE COMPEL 2013

The 14th IEEE Workshop on Control and

Modeling for Power Electronics (COMPEL)