on the design of a photonic network-on-chip

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On the Design of a Photonic Network-on-Chip Assaf Shacham, Keren Bergman, Luca P. Carloni Presented for HPCAN Session by: Millad Ghane NOCS’0 7

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Presented for HPCAN Session by : Millad Ghane. Assaf Shacham , Keren Bergman, Luca P. Carloni. On the Design of a Photonic Network-on-Chip. NOCS’07. Why NoC ?. Scaling Transistor Speed and Integrity Tighter Logic Power Dissipation Increasing Number of Cores per Chip - PowerPoint PPT Presentation

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Page 1: On the Design of a Photonic Network-on-Chip

On the Design of a Photonic Network-on-Chip

Assaf Shacham, Keren Bergman, Luca P. Carloni

Presented for HPCAN Session by: Millad Ghane

NOCS’07

Page 2: On the Design of a Photonic Network-on-Chip

Why NoC ?

Scaling Transistor Speed and Integrity Tighter Logic Power Dissipation

Increasing Number of Cores per Chip Bottleneck: Global Intrachip Communications▪ Bandwidth▪ Power

Performance-per-watt

Page 3: On the Design of a Photonic Network-on-Chip

Why Optic ?

Low Power Dissipation Ultra-high Throughput Minimal Latency End-to-end Transmission

No Repeating No Regeneration No Buffering

A silicon ring

resonator

Page 4: On the Design of a Photonic Network-on-Chip

Hybrid Architecture

Photonic Interconnection High Bandwidth Messages

Electronic Interconnection Low Bandwidth Messages Short Control Messages

Page 5: On the Design of a Photonic Network-on-Chip

Photonic Properties

Advantages Bit-rate Transparency▪ Not Switching by Every Bit of Data▪ Switching Once per Message

Low Loss in Optical Waveguide▪ Independence of Transmission Distance

Disadvantages No Storage Element E/O and O/E Conversions▪ Off-chip Lasers

Page 6: On the Design of a Photonic Network-on-Chip

Packet Life

D

D

SSending path-setup packet

Electronic Network

Optic Network

S

Page 7: On the Design of a Photonic Network-on-Chip

Packet Life

D

S D

SSending optical packet

Page 8: On the Design of a Photonic Network-on-Chip

Packet Life

D

S D

SSending path-teardown packet

Page 9: On the Design of a Photonic Network-on-Chip

Packet Life

D

S D

SSending path-blocked packet

path-teardown packet

Page 10: On the Design of a Photonic Network-on-Chip

Building Blocks

70 µm

70 µm

Photonic Switching ElementElectrical Router

Page 11: On the Design of a Photonic Network-on-Chip

Building Blocks Problems No Injection/Ejection Port Not Deadlock-Free

Wide Turns

Page 12: On the Design of a Photonic Network-on-Chip

Approach

Injection

Torus Address

Ejection

Gateway Switch

Injection Switch

Ejection Switch

Torus Network Nodes

Access Points Address

Format

Page 13: On the Design of a Photonic Network-on-Chip

Deadlock Solution

Injection-Ejection Blocking [previous slide]

Intra-dimentional Blocking (Torus Network) Virtual Channel Flow Control▪ Circuit Switching

terminate-on-timeout packet

Page 14: On the Design of a Photonic Network-on-Chip

Simulation Parameters

POINTS Simulator Based on OMNET++

36-core CMP 6x6 planar

Chip size: 20 x 20 mm Uniform Traffic 3 Cases

Deadlock Message Size Optimization Increasing Path Diversity

2

Page 15: On the Design of a Photonic Network-on-Chip

Message Size Optimization Long path-setup latency

Nonoseconds Super fast transmission

Overhead Ratio:

Page 16: On the Design of a Photonic Network-on-Chip

Message Size Optimization (cont.) Message Duration: 50ns Message Size: 2KB Suitable for

DMA Trans

Page 17: On the Design of a Photonic Network-on-Chip

Increasing Path Diversity PD=2

Less Hardware Less Overhead

Difference

Page 18: On the Design of a Photonic Network-on-Chip

Q & A ?

Thanks !