On Reliable Modular Testing with Vulnerable Test Access Mechanisms

On Reliable Modular Testing with Vulnerable Test Access Mechanisms

Lin Huang, Feng Yuan and Qiang Xu

PurposePurpose

Is on-chip data transmission reliable?

What is the solution? Correction Retransmission Hybrid schemes

They are helpful in normal functional modenormal functional mode

However, how about modular testing modular testing?

Cross talk

IR drop

and even alpha particle hits …

Yield loss

Yield loss

AgendaAgenda

Introduction to Modular Testing

Test Data Transmission “Error-Free” Assumption

Impact of Fault-Tolerant Schemes

The Proposed Solution “Jitter-Aware” Test Wrapper Design “Jitter-Transparent” ATE Interface Design

Experimental Results

Conclusion

Introduction to Modular TestingIntroduction to Modular Testing

“Divide and conquer” manner test wrapper test access mechanisms (TAMs) ATE Interface basic

TAM designs classification dedicated bus-based access scheme functional access schemefunctional access scheme

Reuse On-Chip Network as TAMReuse On-Chip Network as TAM

ATE

Legend

Core

ATE Interface

NI

MUX

Router

System Input

System Output

“Error-Free” Assumption is Questionable“Error-Free” Assumption is Questionable

Existing work assumes test data transmission to be error-free

It is questionable when at-speed functional interconnects are reused as TAMs

Fault Tolerance SchemesFault Tolerance Schemes

Retransmission and hybrid schemes are mainstream techniques to achieve fault-tolerant communication

Retransmission brings problems Test traffic jitter Test bandwidth mismatch

The Impact of Retransmission SchemeThe Impact of Retransmission Scheme

CUT & Wrapper

CHIP UNDER TEST

ATE

In Path ATE IF

In Path ATE NI

In Path Router 1

In Path Router j

In Path Router j+1

In Path Router m

CUT Router

CUT NI

Out Path Router 1

Out Path Router n

Out Path ATE NI

Out Path ATE IF

Flit Error

NACKSequential Flits are Blocked here

Retransmission

TestTrafficJitter

TestBandwidthMismatch

The Significance of These ProblemsThe Significance of These Problems

Given the number of flits in the entire test data volume , the flit error rate , the potential yield loss can be expressed as

When and flit size is 32 bits, the test yield loss for the chip containing 21.5M gates [1] is

1 1N

YieldLoss

N

910

[1] C. Barnhart et al, Extending OPMISR Beyond 10x Scan Test Efficiency.IEEE Design & Test of Computers, 19(5):65-73, Sep.-Oct. 2002

11.47% !

Buffer-Only SolutionBuffer-Only Solution

Given the flit injection rate is 0.1 flits per cycleand the extra delay caused by one retransmission is 40 cycles

The 1st

retransmissionThe 2nd

retransmission

5 reserved flits 1 reserved flits

Shortage ofreserved flits

5 40 0.1 1

“Jitter-Aware” Test Wrapper Design“Jitter-Aware” Test Wrapper Design

Two extra states: HALTIN

HALTOUT

CAPTRUE SHIFT

HALTOUT

HALTIN

OutputBlocked

InputBlocked

IEEE 1500Finite State Machine

Wrapper ArchitectureWrapper Architecture

NETWORK INTERFACE

TEST WRAPPER

Gated_Clk Scan_En

Control Logic

Bd

. Mat

chin

g U

nit

Bd

. Mat

chin

g U

nit

CUT

Input Channel Output Channel

Dat

a

Dat

a

Co

ntr

ol

Co

ntr

ol

Control Logic of Test WrapperControl Logic of Test Wrapper

Block_Ctrl

IPath_Blocked

OPath_Blocked

IBMU_Ctrl

SCmdAccept_In

MCmd_Out

SCmdAccept_Out

MCmd_In

Scan_En

Input Control

Output Control

Control Logic

WrapperKernel Control

ClockDivision

OCP_Clk

Gated_Clk

Scan_Clk

OBMU_Ctrl

“Jitter-Transparent” ATE Interface“Jitter-Transparent” ATE Interface

If the ATE operate in a stream mode …

Minimum buffer size: that is able to tolerate the extra delay caused by one retransmission

Given the flit error rate and the number of flits , the test yield loss can be computed as follows:

11 1 1

N N

BYieldLoss N

N

1 1N

YieldLoss Without Buffer:

On-Chip Network

ATE Interface

Test Vector(w. don’t care bits)

Test Vector(w.o. don’t care bits)

Test Response(w. jitter)

Test Response(w. don’t care bits)

ATE

“don’t care” bitsmeaningful information in the input data data

meaningful information in the output data data

Expected Response

“Jitter-Transparent” ATE Interface“Jitter-Transparent” ATE Interface

We propose to divide the entire input test data flow into segments and insert a small section of “don’t-care” bits

r

Data transmission direction

Test Yield ImprovementTest Yield Improvement

r

1

& 1 1 1rN N

r rB S

NYieldLoss

r

NGiven the flit error rate , the number of flits , and the number of segments , the test yield loss can be computed as follows:

1 1N

YieldLoss Without Buffer:

With Minimum Buffer Size: 1

1 1 1N N

BYieldLoss N

Experimental SetupExperimental Setup Commercial 90nm CMOS technology

Area overhead 838 two-input NAND equivalent gates

An industrial circuit [2]

Number of gates: 2.6M Number of scan cells: 274K Compressed scan test data volume: 106M

System parameters Flit injection rate: 0.25 flit per cycle Flit size: 32 bits Retransmission delay: 40 cycles

[2] C. Barnhart et al, OPMISR: The Foundation for Compressed ATPG Vectors.In Proc. IEEE International Test Conference, pp. 748-757, Nov. 2001

Test Yield Loss for a Core with 2.6M GatesTest Yield Loss for a Core with 2.6M Gates

Yield Loss: 4.41%

Yield Loss: 0.05%

Cost: Testing Time Penalty: 0.15%

Yield Loss: 28.20%

Flit Error Rate: 10-7

Proposed Technique vs. Buffer-Only SolutionProposed Technique vs. Buffer-Only Solution

λYield Loss ≤ 1% Yield Loss ≤ 0.5%

nb (flits) np (flits) ΔTp nb (flits) np (flits) ΔTp

1x10-8 20 20 0.0003% 20 20 0.0003%

5x10-8 40 20 0.0006% 40 20 0.0009%

1x10-7 40 20 0.0018% 40 20 0.0033%

5x10-7 100 20 0.0411% 120 20 0.0824%

1x10-6 160 20 0.1642% 180 20 0.3297%

λ: Flit error rate nb: Buffer size for buffer-only solution

np: Buffer size for the proposed design

ΔTp: Testing time extension ratio of the proposed design

ConclusionConclusion

The “error-free” assumption of existing work is questionable

Fault-tolerant schemes may lead to traffic jitter and variable test bandwidth

We propose a “jitter-aware” test wrapper“jitter-aware” test wrapper and an on-chip “jitter-transparent” ATE interface“jitter-transparent” ATE interface to achieve reliable modular testing

Experimental results demonstrate the effectiveness

Thank you !Thank you !

Timing Diagram of Test WrapperTiming Diagram of Test Wrapper

11 12

Scan_En

OCP_Clk

Scan_Clk

Gated_Clk

MCmd_In

SCmdAccept_In

Block_Ctrl

IPath_Blocked

Mdata_In

A B C D EShift Capture Halt