of motherboards and processors

8/14/2019 Of Motherboards and Processors

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Of Motherboards and ProcessorsA Presentation by Ashish Chalke

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I/O Ports / Back Panel Connectors

Connectors for various types of devices,

e.g. Printers, Monitors etc.

Header Connectors

Electrical posts used generally for Front

Panel connections.AT form factor Motherboards used

Header connectors for every I/O port

except the keyboard.

Power Connectors

Used for giving power to themotherboard. Generally White in colour,

however some Motherboard

manufacturers use Red, Black and Blue as

well.4


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MOTHERBOARD

Main Printed Circuit Board that connects every device.

Called MoBo in short.

CHIPSET

ICs [Integrated Chips] that allow PC components to communicate

with each other.

Called the Northbridge and the Southbridge.

I/O PORTS Connectors at the back of the Motherboard to connect devices.

Color coded to be idiot proof.

BUSES

Connectors or Slots for add-on cards to enhance functionality.

Examples: PCI, AGP, ISA.

SOCKET / SLOT TYPE

House the processor.

Goes hand in hand with Processor selection.5


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BIOS

Basic Input/Output System chip controls the most basic functions of the

computer and performs a self-test every time you turn it on. Some systems feature dual BIOS, which provides a backup in case one fails or

in case of error during updating.

Uses the Real Time Clock or CMOS Chip to store User settings.

REAL TIME CLOCK

Battery operated chip that maintains Basic settings and system time.

CRYSTALS

Check system frequency.

Run at 13.14818 MHz.

JUMPERS

Sit on top of two electrical posts or headers to complete anelectrical circuit.

Used especially in Hard Drives to configure Master/Slave settings.

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CPUL1 Cache

Northbridge

L2 CacheRAM

AGP Video

Controller

PCI Bus PCI Slots

Southbridge

IEEE 1394

USB

Serial Port

Parallel Port

KeyboardMouse

EIDE #1

EIDE #2

Floppy Drive

ISA Slots

Back Side Bus

Front Side Bus

Memory Bus

ISA Bus

Defunct

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CPUL1 Cache

L2 Cache

Graphics Memory

Controller Hub

[GMCH]

PCI Express /

AGP Video

RAM

I/O Controller Hub

[ICH]

LAN

EIDE

SATA

USB

Super I/O

Serial Ports

Parallel Ports

Keyboard

MouseGame Port

Floppy Drive

PCI BusPCI Slots

Front Side Bus / CPU Bus

Memory Bus

Hub Interface

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XT

Obsolete.

Called the IBM Personal Computer XT.Used Memory banks and had sockets

for the processor and support chips.

Full AT

12 x 11

Only a 5 Pin DIN Keyboard connector.

Memory & Buses run parallel.

Expansion cards cover processor.

Baby AT

8.5 x 10

2/3 the size of full AT. Socket 7 ZIF for classic Pentium processor.

Plug and Play BIOS.

Memory & Buses run parallel.

Mix of ISA/EISA and PCI buses,9


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LPX / NLX

Allows for a smaller form factor by placing

bus architectures on a riser card. LPX was never standardised. NLX was

standardised in1997 by Intel.

8-9 x 10-13.6

BTX

12.8 x 10.5 Introduced by Intel as successor to ATX.

Better Cooling & low power consumption.

Needs a BTX case.

Hasnt really been adopted because of Intels

recommitment to the ATX standard.

mBTX

10.4 x 10.5

Smaller than BTX for use in Portable devices.

Might include the Communications Network

Riser.10


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ATX

12 x 9.6

Created by Intel in 1995. Buses are at a right angle with Memory Slots.

Processor between Memory and I/O Ports,

right in front of the fan for better cooling.

20 Pin Power connector + 4 pins added for PCI-E

Soft Power: OS sends signal to the Motherboard

to turn the power off.

mATX

9.6 x 9.6

Smaller than ATX for small form factor PCs. Fits into ATX case.

Everything else ATX style.

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Stranger as they come..

Mini/Nano/Pico ITX

Developed by VIA for

use in Thin Clients andSet Top Boxes.

WTX

Developed by Intel. Large

design for serversfeaturing multiple CPUs.

PC/104 [Plus / Express]

Used in Embedded Systems.

Adapted the AT Bus, PCI Bus and

PCI Express architectures to

vibration tolerant header

connectors.12


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PCI (Peripheral Component Interconnect)

Introduced to replace ISA.

Has two implementations: 32 bit & 64 bit.

Plug & Play.

White slot.

PCI-X (Peripheral Component InterconnecteXtended)

Upgrade of PCI. Backwards compatible. One implementation: 64 bit.

Never implemented outside North America because of engineering difficulties.

AGP (Accelerated Graphics Port) 32 bit architecture.

Used for advanced Video.

First appeared in 1997 along

with the Pentium II.13


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PCI-Express

Uses lanes to transfer data. Each implementation has different no. of lanes

identified by a multiplier. Eg.: x4

Uses Serial communication over PCI/PCI-Xs parallel communication. Modern replacement for PCI, PCI-X, AGP as it is a lot faster.

SLI & CrossFire:

Graphics standards from Nvidia and ATi that allow multiple PCI Express x16

slots to be used for multiple graphics cards increasing graphics performance.

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The pensioners

ISA / EISA (Industry Standard Architecture / Enhanced ISA)

ISA: 8 bits or 16 bits ; EISA: 16 bits or 32 bits.

Run at a sloooooooow 8Mhz. EISA is backwards compatible with ISA.

MCA (Micro Channel Architecture)

32 bit architecture, runs at 10 Mhz.

Developed by IBM but never caught on as it wasnt compatible with ISA cards.

Introduced Bus Mastering which allows device to device communication without

processor intervention greatly reducing Processor workload.

VESA (Video Electronics Standards Association)

32 bit architecture, by means of a 16 bit extension behind a 16 bit EISA slot.

Runs/Ran at processor speed. [25-33 Mhz back then.]

Used for video and is a tan slot behind a black ISA/EISA slot.

Audio Modem Riser / Communications Network Riser

Used to provided advanced audio & modem / Dolby Digital audio and LAN

capabilities.

Defunct due to the rise of PCI Express and integrated chipsets.15


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C

AC

H

E

ALU

R

CONTROL

ALU

R Register

ArithmeticLogic Unit

Internal Data Bus

Back Side Bus

Fig: Internal components of a Hyperthreaded Processor

Front Side Bus

INPUT OUTPUT

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ARITHMETIC LOGIC UNIT

Performs mathematical calculations and comparisons.

REGISTER Provides a temporary holding area for calculating data as it has the fastest

access from the ALU.

FRONT SIDE BUS

Interface between the Motherboard and the Processor.

Data Path: 64 bits for a 32 bit Processor, 128 bits for a 64 bit Processor. Higher Speed will result in full efficient utilisation of CPU.

Current speeds are: 1333 MHz, 1600 MHz.

CONTROL UNIT

Controls various operations like generating control signals for reading and

writing data to memory or I/O devices.

In a Hyperthreaded / Multi-Core environment, decides which ALU will perform

operations.

BACK SIDE BUS

Interface between the Register & ALU; the ALU & Cache.18


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INTERNAL DATA BUS

In a HT environment, interface between the second ALU, Register and Control.

CACHE Memory on the processor used for storing frequently accessed information.

Used for load balancing between the CPU (fast) and RAM (slow) as it is faster

RAM due to close proximity to the processor.

Named L1, L2, L3 in terms of access speed.

In modern CPUs, L1 and L2 cache reside in the processor itself while L3 resides

on the socket. That is changing as well with Intels Core i7 processors which haveall three on the processor.

Connected to the ALU by the Backside Bus.

CORE SPEED

Calculations performed per second.

Depends on a lot of things like the FSB, rated clock speed etc.

ADVANCED TRANSPORT CONTROLLER BUS

256 bits wide, runs as fast as the processor.

Built to replace: Backside Bus, Internal Data Bus, Control Unit and Front Side Bus.

Hasnt really seen the light of the day.19


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HYPERTRANSPORT

HyperTransport Technology was invented at AMD with contributions from

industry partners and is managed and licensed by the HyperTransport

Technology Consortium, a Texas non-profit corporation. HyperTransport Technology is a high-speed, low latency, point-to-point link

designed to increase the communication speed between integrated circuits in

computers, up to 48 times faster than some existing technologies. (3.2 Ghz)

Reduces the number of buses in a system, which can reduce system bottlenecks

and enable today's faster microprocessors to use system memory more

efficiently in high-end multiprocessor systems.

QUICKPATH INTERCONNECT

Designed by Intel to compete with AMDs HyperTransport Technology,

Dynamically scalable interconnect bandwidth designed to set loose the full

performance of Nehalem, Tukwila, and future generations of Intel multi-core

processors

Outstanding memory performance and flexibility to support leading memorytechnologies

Tightly integrated interconnect reliability, availability, and serviceability (RAS)

with design-scalable configurations for optimal balance of price, performance,

and energy efficiency. Clocks at 3.2 Ghz.20


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REDUCED INSTRUCTION SET COMPUTING

RISC chips use simple instruction sets to achieve higher clock speeds

and process more instructions per clock cycle.

RISC chips are technically faster than CISC per instruction but use

more instructions. [Software side]

Cheaper and faster but more burden on Software developers.

SUN, pre-OS X Apple use RISC architecture. The UNIX OS runs on

RISC.

COMPLEX INSTRUCTION SET COMPUTING Have a large amount of different and complex instructions.

Are technically slower than RISC per instruction but use less

instructions. [Software side]

The philosophy is that the hardware is always faster than software. A

powerful instruction set will in turn reduce the workload of

programmers by allowing them to use assembly instructions forshorter programs.

Conventional CISC chips are becoming FASTER and CHEAPER.

Intel and AMD make CISC processors.

The line between CISC and RISC chips is blurring however.21


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OVERCLOCKING

Change the clock speed of the processor for performance gains via the FSB

multiplier in the BIOS, jumpers or DIP switches. Needs better CPU cooling solutions as overclocked CPUs generate more heat.

MULTIMEDIA EXTENSION (Micro Code)

Introduced by Intel with the Pentium MMX.

Added the MMX Instruction set to the normal Instruction set for better

processing of graphics, video and audio data.

Helped the processor perform certain key tasks in a streamlined fashion,sufficing in just one instruction instead of many required earlier.

Provided a 10-20% increase in normal software and more for MMX specific.

Apps and Games that took advantage of MMX performed better.

THROTTLING

Reduce speed (calculations per second) to run cooler and consume less power. CLAMPING

Controls how much CPU time is allowed for an application.

Generally seen on Laptops and low power devices.22


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VOLTAGE REGULATOR MODULE

Regulates voltage between processors in multi-processor environments. Sends Standard Voltage level to the processor.

Processor communicates voltage needed with the VRM especially when

Throttling features are enabled.

32/64 BIT

Type of instructions the CPU can process.

While 64 bit CPUs mean a performance gain, they require special 64 bit

software and drivers that provide 64 bits wide instructions to be fully

utilised.

HYPER-THREADING

Ability to perform two sets of data executions in parallel to each other at

the same time. Summarised as: Act logically as two processors.

Not to be confused with: Multi-core processors which are two or more

CPUs on a single die or chip that share the Cache.23


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THE TERM

A processing system composed of two or more independent cores on thesame chip or die, which facilitates simultaneous managing of activities.

High performance without driving up power consumption

CPU 1

L1 Cache

CPU 2

L1 Cache

L2 Cache

Control Unit

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CPU1 CPU2

CPU

Single-core

Large tasks runningsimultaneously slow down

Dual-core

Large tasks can beprocessed in separate CPUs

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Two CPUs perform two tasks

simultaneously.

Now think what a Hyperthreaded

Dual Core CPU can do.. 4processes at a time!

And there are Quad Core

Hyperthreaded processors in the

currently available!

Significant improvement on cache (bus)

snooping Signals between different CPUs travel

shorter distance, which allows:

More data to be transmitted.

Less signal degradation.

No need to transmit data

repeatedly.

Two cores on the same die mean less

power consumption, of course at the

price of performance of TWO

processors.

CPU 1

L1 Cache

CPU 2

L1 Cache

L2 Cache

Control Unit

Because the cores have to

share the L2 Cache.

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Dual Inline Package Pin Grid Array

Staggered Pin Grid Array Ball Grid Array

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Land Grid Array Single Ended Contact Cartridge

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PASSIVE

Standard heatsinks without fan.

Not used for CPUs as they run quite hot.

ACTIVE

Standard heatsinks with a fan to dissipate heat

quickly Stock cooling systems are of this type.

Water based / Liquid based cooling systems

used generally by overclockers.

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Jointly developed by IBM, Toshiba and Sony

for the Playstation 3 gaming console.

Specs 8 Cores clocked at 3.2 GHz

Each core has 256 KB of local memory.

64 bit Architecture.

Can be overclocked to 4 GHz.

NASA Scientists are using the Cell

Processor for research.

Termed as a Super Computer for Desktops.

Programmers still have not been able to

utilise the full 8 cores due to its complex

instruction sets.

In 2008 IBM announced a revised variant of

the Cell termed as the PowerXCell 8i.

The IBM Roadrunner super computer, theworlds second fastest utilises 12240

PowerXCell 8i processors, along with 6562

AMD Opteron processors.32


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Developed by Intel in 2008.

Ultra Low Voltage CPUs for netbooks, nettops,Mobile devices. Has given birth to a whole new slew

of low voltage consuming yet powerful computers.

Specs:

Available in Single Core and Dual Core models.

Some models, namely the Z, 200, 300, support

hyperthreading.

The N270 is the most popular with 1.6 Ghz

Single Core and a 533 Mhz FSB.

The Dual Core Atom 300 Series is the current

performance king.

Developments:

Graphics Processor maker Nvidia announced

the ION Platform with the Atom 300 with aspecial graphics chipset sporting the GeForce

9400M on the Mini-ITX form factor.

Allows Atom PCs support for HD graphics.33


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Thanks to my Instructors, Mr. Gulabchand and Mr. Surendra.

Thanks to James Conrad, JiaYiao and Anil C. for their help.

References:

Wikipedia

Intel, AMD and IBM official websites.

Formfactors.org

CPUShack.com HowStuffWorks.com

PCMech.com

Scribd.com

FrozenCPU.com

How Multi Core Processors Work by JiaYiao

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