November 7 - 11, 2004DoubleTree Hotel

San Jose, CA

Proceedings of the 2004 International Conference

on Computer-Aided Design

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Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted tophotocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry acode a the bottom of the first page, provided the per-copy fee indicated in the code is paid through CopyrightClearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission,write to IEEE Copyrights Manager, IEEE Operations Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. All rights reserved. Copyright © 2004 by the institute of Electrical and Electronic Engineers, Inc.

The papers in this book comprise the proceedings of the meeting mentioned on the cover and title page. They reflectthe authors’ opinions and, in the interests of timely dissemination, are published as presented and without change.Their inclusion in this publication does not necessarily constitute endorsement by the editors, the IEEE ComputerSociety, or the Institute of Electrical and Electronics Engineers, Inc.

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IEEE Catalog Number: 04CH37606ISBN Number: 0-7803-8702-3 Softbound EditionISSN Number: 1092-3152

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PROGRAM CHAIRMajid SarrafzadehUniv. of California, Los AngelesComputer ScienceBoelter Hall, Room 3532CLos Angeles, CA 90095-1596(310) 794-4303majid@cs.ucla.edu

PROGRAM VICE CHAIRSoha HassounDept. of Computer ScienceTufts Univ.Medford, MA 02155(617) 627-3217soha@cs.tufts.edu

PAST CHAIRAndreas KuehlmannCadence Berkeley Labs.1995 University Avenue, Suite 460Berkeley, CA 94704(510) 647-2840kuehl@cadence.com

TUTORIAL CHAIRGeorges GielenESAT-MICASKatholieke University LeuvenKasteelpark Arenberg 10Leuven, B-3001 Belgium(32) 16-321047georges.gielen@esat.kuleuven.ac.be

EUROPEAN REPRESENTATIVEWolfgang RosenstielUniv. of TuebingenSand 14Tuebingen, BW72074, Germany(49) 7071-29-75482rosen@informatik.uni-tuebingen.de

ASIAN REPRESENTATIVEAllen C. H. WuComputer Science Dept.National Tsing Hua Univ.Hsin-Chu, Taiwan 30043(88) 63-571-5131 ext 3517chunghaw@cs.nthu.edu.tw

ACM/SIGDA REPRESENTATIVENikil DuttUniv. of CaliforniaDepartment of Computer Science444 CSIrvine, CA 92697-3425(949) 824-7219dutt@uci.edu

IEEE CS/DATCREPRESENTATIVEJohn DarringerIBM Corp., TJ Watson Research Ctr.P.O. Box 218Yorktown Heights, NY 10598(914) 945-2742jad@us.ibm.com

IEEE/CAS REPRESENTATIVEHiroto YasuuraKyushu Univ.6-1 Kasuga Koen Kasuga, 816-8580, Fukuoka, Japan(81) 92-583-7620yasuura@c.csce.kyushu-u.ac.jp

PUBLICITY CHAIRCarole ThurmanMentor Graphics Corp.8005 S.W. Boeckman Road,Wilsonville, OR 97070-7777(503) 685-4716(503) 685-1214carole_thurman@mentor.com

CONFERENCE MANAGERKathy MacLennanMP Associates, Inc.5405 Spine Rd., Ste. 102Boulder, CO 80301(303) 530-4562kathy@mpassociates.com

CONFERENCE COMMITTEE

GENERAL CHAIRHidetoshi OnoderaKyoto Univ.Dept. of CCEGraduate School of InformaticsSakyo-ku, Kyoto 606-8501 Japan(81) 75-753-5314onodera@i.kyoto-u.ac.jp

FOREWORD

On behalf of the ICCAD 2004 Executive and Technical Program Committee, we would like to welcome you to theInternational Conference on Computer Aided Design. We hope you enjoy the conference and learn about all the latestadvances in electric design technology and automation.The core of the conference is the technical program. This year, ICCAD received 520 submissions, the highest number inour history. Based on the result of a rigorous and thorough review followed by a full day face-to-face discussion, 127papers were selected and compiled into an exciting final program which will be further enriched by multiple specialsessions and events. Besides technical sessions, we will have social hours every evening beginning Sunday and runningthrough Wednesday. This is an opportunity to meet your colleagues and develop your network for information exchangeor for you to further discussion in a relaxed atmosphere.As in the previous two years, some of the conference activities begin on Sunday, November 7th. There will be a workshopentitled "IC Design in 65 nm and beyond: Evolution or Revolution?". This is a forum where leading experts from industryand academia will present their visionary view on the challenges and solutions for 65 nm design and beyond. There aretwo parallel tracks of three presentations each, focusing on system-oriented and physical-implementation-oriented topics.Following the workshop, participants will be invited to a concluding panel and the ICCAD Opening Reception. Allconference registrants are welcome to attend the workshop, panel, and reception. For the students on Sunday,ACM/SIGDA is sponsoring a CADathlon, a programming contest that challenges students in their CAD knowledge andtheir skills in problem solving, programming, and teamwork.The main part of the ICCAD 2004 conference begins on Monday morning with the opening keynote speaker, Peter Rickert,Director of Platform Technology Development, Texas Instruments, entitled: "Problems or Opportunities? Beyond the90nm Frontier". The technical program follows with 38 regular paper sessions and five embedded tutorials on "StatisticalSTA", "Variability Impact on Design", "Formal Verification", "Design-Manufacturing Interface", and "Transaction LevelModeling". The Monday night panel, entitled "Divine for Dollars," will focus on the next EDA innovations that can changethe way chips are developed.Multiple side events complement the technical program and enhance the overall ICCAD schedule. The Technology Fairon Tuesday will provide a forum where conference attendees can meet industrial R&D colleagues to discuss technicalchallenges and solutions, or to simply meet new contacts for future relationships. The Technology Fair Reception willfollow in the evening and will be a perfect opportunity to network with the vendors and your colleagues.The conference concludes on Thursday, November 11th, with the 2004 Tutorial Program. This year, we are introducing anew format for the tutorials. We will offer six half-day tutorials. Attendees will receive the full set of notes and they canfreely choose any morning and afternoon sessions. Special care has been taken in the selection of topics and speakers sothat there will be a good balance of theoretical aspects and real industrial practices. The Tutorial Program covers the topics:"Power Reduction Techniques", "Industrial Power Reduction Experiences", "Physical Design at 90nm", "Signal Integrityand Reliability", "Clock Distribution", and "New Algorithm for CAD".On behalf of the organizers of ICCAD, we would like to thank all people involved in the 2004 event. In particular, wewould like to thank the members of the Executive and Technical Program Committees, everyone at MP Associates, andthe many volunteers from our sponsoring societies. Also, we would like to express our sincere thanks to all the authorswho submitted papers with valuable results, since their contributions form the basis of our technical excellence.As we are going into the era of nano scale integrated circuits, many issues will confront us such as complexity,manufacturability, and power dissipation. These issues can be overcome by tighter collaboration than ever among EDAresearchers, designers, manufacturers, and application engineers. ICCAD 2004 offers an ideal place for all these peopleto meet and exchange ideas about the challenges and solutions for the future. We hope ICCAD 2004 will be a valuable andenjoyable professional experience.

Hidetoshi OnoderaGeneral Chair

Majid SarrafzadehTechnical Program Chair

IEEE/ACM William J. McCalla ICCAD Best Paper AwardThe "Best Paper Awards", selected by the ICCAD Program Committee, were selected through arigorous and multi-stage reveiw process. The Awards are given in memory of William J. McCalla,for his contributions to ICCAD and his CAD technical work through his career.

Asymptotic Probability Extraction for Non-Normal Distributions of Circuit PerformancePaper 1A.1Authors: Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. PileggiAffiliation: Carnegie Mellon Univ., Pittsburgh, PA

SPRIM: Structure-Preserving Reduced-Order Interconnect MacromodelingPaper 1D.2Author: Ronald W. FreundAffiliation: Univ. of California, Davis, CA

SIGDA 2004 Outstanding New Faculty AwardKaustav Banerjee - Univ. of California, Santa Barbara, CAIgor Markov - Univ. of Michigan, Ann Arbor, MI

For a junior faculty member early in her or his academic career who demonstrates outstanding potentialas an educator and/or researcher in the field of electronic design automation.

ICCAD-2004 AWARDS

Ram AcharCarleton Univ.Ottawa, Ontario, Canada

Narayan R. AluruUniv. of Illinois, Urbana-ChampaignUrbana, IL

Kia BazarganUniv. of MinnesotaMinneapolis, MN

Michel BerkelaarMagma Design Automation, Inc.Eindhoven, The Netherlands

David BlaauwUniv. of MichiganAnn Arbor, MI

Duane S. BoningMassachusetts Institute of Tech.Cambridge, MA

Elaheh BozorgzadehUniv. of California, IrvineIrvine, CA

Forrest D. BrewerUniv. of California, Santa BarbaraSanta Barbara, CA

Thomas BurdConsultantBerkeley, CA

Gianpiero CabodiPolitecnico di TorinoTorino, Italy

Yao-Wen ChangNational Taiwan Univ.Taipei, Taiwan

Charlie Chung-Ping ChenNational Taiwan Univ.Taipei, Taiwan

Chung-Kuan ChengUniv. of California, San DiegoLa Jolla, CA

Charles ChiangSynopsys, Inc.Mountain View, CA

Jordi CortadellaUniversitat Politecnica de CatalunyaBarcelona, Spain

Bernard CourtoisTIMA Labs.Grenoble, Cedex, France

Alper DemirKoch Univ.Sariyer-Istanbul, Turkey

Elena V. DubrovaRoyal Institute of Tech.Stockholm, Sweden

Tony GivargisUniv. of California, IrvineIrvine, CA

Seth GoldsteinCarnegie Mellon Univ.Pittsburgh, PA

Helmut E. GraebTechnical Univ. of MunichMunich, Germany

Nagib Z. HakimIntel Corp.Santa Clara, CA

Joerg HenkelUniv. of KarlsruheKarlsruhe, Germany

Dwight D. HillSynopsys, Inc.Mountain View, CA

James C. HoeCarnegie Mellon Univ.Pittsburgh, PA

Jiang HuTexas A&M Univ.College Station, TX

Tomoo InoueHiroshima City Univ.Hiroshima, Japan

Yehea IsmailNorthwestern Univ.Evanston, IL

Andre IvanovUniv. of British ColumbiaVancouver, BC, Canada

Sharad KapurIntegrand Software, Inc.Hoboken, NJ

Tanay KarnikIntel Corp.Hillsboro, OR

Chandramouli R. KashyabFlexlogics, Inc.Sunnyvale, CA

Ryan KastnerUniv. of California, Santa BarbaraSanta Barbara, CA

Michael KishinevskyIntel Corp.Hillsboro, OR

James KukulaSynopsys, Inc.Hillsboro, OR

Kimmo KuusilinnaTampere Univ. of Tech.Tampere, Finland

Tadahiro KurodaKeio Univ.Yokohama, Japan

Paolo IenneSwiss Federal Institute of Tech.Laussanne, Switzerland

Hardy K. LeungMagma Design Automation, Inc.Santa Clara, CA

Rainer LeupersRWTH AachenAachen, Germany

Jun LieTOP Design Technology, Inc.Sunnyvale, CA

Yanbing LiSynopsys, Inc.Mountain View, CA

Shen LinApache Design Solutions, Inc.Mountain View, CA

Amitava MajumdarSun MicrosystemsSunnyvale, CA

Igor L. MarkovUniv. of MichiganAnn Arbor, MI

Yusuke MatsunagaKyushu Univ.Kasuga, Japan

Ken McMillanCadence Berkeley Labs.Berkeley, CA

Seda Ogrenci MemikNorthwestern Univ.Evanston, IL

Noel MenezesIntel Corp.Hillsboro, OR

Tamal MukherjeeCarnegie Mellon Univ.Pittsburgh, PA

Sani R. NassifIBM Corp., Austin Research LabAustin, TX

ICCAD-2004 TECHNICAL PROGRAM COMMITTEE

Wolfgang NebelOldenburg Univ., OFFISOldenburg, Germany

Borivoje NickolicUniv. of California, BerkeleyBerkeley, CA

Alex OrailogluUniv. of California, San DiegoSan Diego, CA

David OverhauserCadence Design Systems, Inc.San Jose, CA

Sule OzevDuke Univ.Durham, NC

Yunheung PaekSeoul National Univ.Seoul, Korea

David PanUniv. of TexasAustin, TX

Preeti R. PandaIIT DelhiNew Delhi, India

Rajendran PandaMotorola Inc.Austin, TX

Joel R. PhillipsCadence Berkeley Labs.Berkeley, CA

Jaijeet RoychowdhuryUniv. of MinnesotaMinneapolis, MN

Louis SchefferCadence Design Systems, Inc.San Jose, CA

Narendra V. ShenoySynopsys, Inc.Mountain View, CA

Youngsoo ShinIBM Corp., T.J. Watson Research CenterYorktown Heights, NY

Luis Miquel SilveiraINESC I & D LisboaLisboa, Portugal

Deshanad SinghAltera Corp.Toronto, Ontario, Canada

Vigyan SinghalJasper Design AutomationMountain View, CA

Tom SpyrouCiraNova Inc.Campbell, CA

Ankur SrivastavaUniv. of MarylandCollege Park, MD

Georgios StamoulisUniv. of ThessalyVolos, Greece

Stuart SwanCadence Design Systems, Inc.Redwood City, CA

Atsushi TakahashiTokyo Institute of Tech.Tokyo, Japan

Hiroyuki TomiyamaNagoya Univ.Nagoya, Japan

Boris TroyanovskyTiburon Design AutomationSanta Rosa, CA

Nick van der MeijsDelft Univ. of Tech.Delft, Netherlands

Ashok VittalFlexlogics, Inc.Santa Clara, CA

Duncan (Hank) WalkerTexas A&M Univ.College Station, TX

Martin D. F. WongUniv. of Illinois, Urbana-ChampaignUrbana, IL

Allen C. H. WuTsing Hua Univ.Hsin-Chu, Taiwan

Nobuyuki YoshikawaYokohama National Univ.Hodogaya-ku, Yokohama Japan

Hai ZhouNorthwestern Univ.Evanston, IL

Hanna ZiyadIntel Corp.Hillsboro, OR

ICCAD-2004 TECHNICAL PROGRAM COMMITTEE

Patrick H. MaddenUniv. of Kitakyushu and SUNY BinghamtonKitakyushu, Japan

Juan-antonio CarballoIBM Corp.Austin, TX

Joerg HenkelUniv. of Karlsruhe, GermanyKarlsruhe, Germany

Jim KukulaSynopsys, Inc.Hillsboro, OR

Richard ShiOrora Design Technologies, Inc.Redmond, WA

Yehea IsmailNorthwestern Univ.Evanston, IL

Stephen SunterLogicVision, Inc.Ottawa, Canada

IEEE/ACM WILLIAM J. MCCALLA ICCAD BEST PAPER AWARDSELECTION COMMITTEE

Cristinel AbabeiAmir Aborna Saurabh Adya Kanak Agarwal Charles Alpert Baris Arslan Adnan Aziz Damogoj Babic Iris Bahar David Bañeres Shabbir Batterywala Ali Bayazit Murat Becer Sarvesh Bhardwaj Armin Biere Christian Blum Stephen Bullock Steve Butler Ke Cao Olivier Caty Sourav Chakravarty Hayward Chan Kai-Yuan ChaoArindam Chatterjee Cary Chin Eli Chiprout Wonjoon Choi Florin Ciontu Claudionor Coelho Kivilcim Coskun Florentin Dartu Shidhartha Das Scott Davidson Azadeh Davoodi Li Ding Rolf Drechsler Basant Kumar Dwivedi Nuria Pazos Escudero Andrea Fedeli Yuhong Fu

Zhaohui Fu Youxin Gao Giuseppe Garcea Arjan van GenderenSoheil Ghiasi Wenrui Gong Eric Grimme Satrajit Gupta Mattew Guthaus Daniel Even Haiem Ramesh Harjani Ian Harris Masaki Hashizume Yoshinobu Higami Greg Hoover Anup Hosangadi Toshinori Hosokawa Li-Da Huang William N. Hung Hideyuki Ichihara Michiko Inoue Tsuyoshi Isshiki Sitaraman Iyer Abhijit Jas Dan Jiao Hiroto Kagotani Daher Kaiss Seiji Kajihara Timothy Kam Kai Kapp Chandramouli Kashyap Nitin Kataria Jacob Katz Himanshu Kaul Jamil Kawa Vishal Khandelwal Zurab Khasidashvili Joonyoung Kim Sam Kim Desmond Kirkpartrick

Alex Kondratyev Oleksandr Korshak Victor Kravets Yukiko Kubo Andreas Kuehlmann Haydar Kutuk Luciano Lavagno Dongwoo Lee Seokjin Lee Alexander S. Levin Zhuo Li Frank Liu George Logothetis Tao Luo Ryan Magargle Yogesh Mahajan Pongstorn Maidee Cliff Maier Rob Mains Freddy Mang Diana Marculescu Tobias Massier Mohiuddin Mazumder Peter Meijer Yan Meng Hideyuki Michinishi Prabhat Mishra Yukiya Miura Nilesh Modi Hushrav Mogal Daniel Mueller Hiroshi Murata Ashok Murugavel Shigetoshi Nakatake Mini Nanua Jagannathan Narasimhan Naren Narasimhan Sridhar Narayanan Sreekumar Natarajan Sudipto Neogi

ICCAD-2004 REVIEWERS

Jose Neves Kelvin Ng Sergio Nocco Chanhee Oh Brendan O'Higgins Satoshi Ohtake Kenichi Okada Charles Ouyang Sanjay Pant David Papa Claudio Passerone Enric Pastor Jordi Petit Laura Pozzi Wang Qiang Stefano Quer Umberto Quer Arathi Ramani Rhyam Ramji Abhishek Ranjan Rajeev Rao Kavita Ravi Haoxing Ren Steffen Rochel Umberto Rossi Jarrod Roy Viktor Sabelfeld Khurram Sajid

Sachin Sapatnekar Prashant Saxena Peter Schmidt Eelco Schrik Navaratnasothie Selvakkumaran Muzhou Shao Weiping Shi Shy Shyman Ozgur Sinanoglu Subarna Sinha Christos Sotiriou Guido Stehr Ken Stevens George Su Haihua Su Qing Su Yamini Bala Sukumaran Savithri Sundareswaran Michael Syrjakow Chin-Ngai Sze Hiroshi Takahashi Yasuhiro Takashima Daijue Tang Xiaoping Tang Michael Theobald Bhavana Thudi Jing Tong Rasit Topaloglu

Franco Toto Kees-Jan van der Kolk Lieven Vandenberghe Prab Varma Giri Venkata Miljan Vuletic Shin' ichi Wakabayshi Steven Walstra Gang Wang Xin Wang Xinning Wang Yi Wang Xiaoping Wen Yujie Wen Jacob White Di Wu Xiang Wu Gang Xu Koji Yamazaki Mehmet Yildiz Hiroshi Yokoyama Tomokazu Yoneda Hiroyuki Yotsuyanagi Yinlei Yu Xin Yuan Bo Zhai Min Zhao Jun Zou

ICCAD-2004 REVIEWERS

Peter Rickert, P.E.TI Fellow, Director of Platform Technology Development,

Application Specific Products, Texas Instruments

PROBLEMS OR OPPORTUNITIES? BEYOND THE 90NM FRONTIERDescription: TContinued technology advances in the next ten years are based on 1) continuedperformance improvement and cost reduction through Moore's Law scaling of feature size and 2)SOC integration of analog and RF functions. Radically more sophisticated EDA capabilities arerequired in order for the industry to achieve this technology entitlement. This talk projectstechnology trends and identifies some of the key challenges for the EDA industry.Several key new trends in the product space are driving the need for additional innovation in theEDA tool space. Several specific examples will be reviewed, notably, System-on-ChipIntegration, Power Management (both leakage and active power reduction) integration, andmultiple CPU cores on a single chip along with multi million gates per chip driving the need fora higher level of abstraction to improve designer efficiency. Intermingled with these is the needfor multivariable optimization, to close all the design gaps simultaneously, for improvedefficiencies. Each of these will be discussed in detail.This is coupled with the 65nm and beyond process technology specific challenges which are alsodriving the need for additional EDA innovation. Notably design rule complexity explosion, sublithographic feature implementation tools (Reticle Enhancement Technology RET and OpticalProximity Correction OPC), and increased process variation and worst case corner explosion,requiring need for statistical simulation tools up and down the design flow.Only through quick interaction between engineers from the product and process domains, alongwith the tool developers as well as academia and research labs will these new required capabilitieshave a chance of intersecting the timelines required to be leveraged on the 65nm and 45nm productplatforms. This talk will also include areas which should be driven towards open, non-proprietarystandards to improve the overall efficiency of design organizations across the industry, leveraginglessons learned from recent history.Let's all address these gaps with innovative solutions and end the arguments over what thetimeline is for the end of Moore's Law!Biography: Peter Rickert, P.E., is a TI Fellow and currently responsible for Platform TechnologyDevelopment for the Application Specific Products (ASP) organization at TI. He manages thecross-functional team which encompasses the definition, development, and deployment of TI'sdeep submicron System on a Chip process technologies, including the the 90nm , 65nm, and the45nm platforms. In 2000, Rickert was elected a TI Fellow in recognition of his leadership of newtechnology introductions and ramp to productions. He has held multiple management rolesacross TI during his 24 year career, including assignments in Houston, France, and now Dallas.He is widely recognized for his broad technical leadership and knowledge in process technology,ASIC design, testing, and program management. Rickert received his Bachelor of Science degreein Electrical and Computer Engineering at Clarkson University in 1980. He became a RegisteredProfessional Engineer in the state of Texas in 1992 and is a Senior member of the IEEE.

ICCAD-2004 KEYNOTE

TUTORIAL 1

BEST PRACTICES IN LOW POWER DESIGN: PART 1 : POWERREDUCTION TECHNIQUES

Speakers:Enrico Macii – Politecnico di Torino, Torino, ItalyMassoud Pedram - Univ. of Southern California, Los Angeles, CA

Targeted Audience: Industrial design engineers and EDA professionals who want to learn aboutbasic low-power design techniques that can be used in industrial practice.

Description: In the last decade, huge effort has been invested to come up with a wide range ofdesign solutions that help in solving the power consumption problem for different types ofelectronic devices, components and systems. Some of those solutions turned out to be verypractical and effective, thus finding a path into commercial products of a different nature. Otherapproaches, which sounded promising on paper, showed too many limitations for attracting theattention of real designers. The objective of this tutorial is to offer the attendees some well-established, yet innovative recipes for addressing the power problem in real life. The presentationwill be structured into two half-day tutorials. The morning tutorial will describe basic techniques,applicable at different levels of abstraction, that have proven to hold great potential for poweroptimization in practical design environments. They range from RTL power management andclock-tree architecture design to memory and bus interface design. Also some of the latestsolutions regarding frequency and voltage dynamic control, as well as solutions for leakage powermanagement will be discussed.

TUTORIAL 2

PHYSICAL DESIGN AT 90NM AND BEYOND

Speakers:Andrew B. Kahng – Univ. of California, San Diego, La Jolla, CAPete J. Osler - IBM Corp., Essex Junction, VA

Targeted Audience: Industrial design and layout engineers and EDA professionals who want tolearn about physical design challenges and solutions in advanced nanometer CMOS processtechnologies.

Description: Process variations, leakage, and scalability of runtime and QOR present criticalchallenges to IC physical design at the 90nm node and beyond. Many established paradigms,such as sequenced synthesis, place, and route flows, will have to be replaced by new physicaldesign methodologies and tool paradigms. This tutorial will cover five key shifts at 90nm andbeyond. We will discuss necessary algorithmic and flow changes that underlie manufacturing-aware cell-based place-and-route methodologies. Next, we will discuss methods andinfrastructure for statistical and parameterized static timing analysis. Then we will discuss thebenefits and challenges of integrated routing/placement/synthesis. Next, we will discuss next-generation thermal and leakage power-centric analysis and optimization flows that respond to thepower and leakage issues. Finally, a view is provided on the long-term methodological trends thatwill govern the evolution of physical design.

TUTORIAL 3

SIGNAL INTEGRITY AND RELIABILITY OFINTEGRATED CIRCUITS: PRACTICAL

CONSIDERATIONS AT 130NM AND BELOW

Speakers:Kenneth Tseng – Cadence Design Systems, Inc., San Jose, CASyed M. Alam - Massachusetts Institute of Tech., Cambridge, MA

Targeted Audience: Industrial design and layout engineers and EDA professionals who want tolearn about signal integrity and reliability challenges and solutions in real practical designs.

Description: At 130nm and below, ignoring signal integrity (SI) is a luxury no designer canafford. SI-related issues are showing up in silicon from high-performance custom designs toASICs and even FPGA-based designs, resulting in costly respins and missed market window.Hence every designer needs an awareness of signal integrity prevention, analysis and repair. TheSI problem promises to become even more challenging at 90nm and 65nm. The fundamentalscaling barrier of supply and threshold voltages have given rise to a multitude of designtechniques trading off timing versus power, yet making noise much worse than before. IncreasingSI problems call for better analysis techniques and tools. The first part of the tutorial will explorenew techniques in coupling aggressor alignment and statistical analysis of crosstalk. New delaymodels and tools are needed to handle the multitude of supply voltages and operatingtemperatures in a design. The second part of the tutorial focuses on reliability problems inintegrated circuits, with a focus on electromigration, which is the primary interconnect reliabilityconcern in integrated circuits. Cu interconnects are still susceptible to electromigration-inducedfailure over time. First the physical mechanisms and failure modes due to the electromigrationphenomenon in both Al and dual-damascene Cu technologies will be reviewed. The bulk of thetutorial will focus on design procedures and CAD methodologies for circuit-level reliabilityassessment. A hierarchical reliability analysis flow will be discussed that accounts for the distinctreliability characteristics in Cu technology. Finally, future reliability issues with Cu/low-ktechnology and non-blocking vias will be explored.

TUTORIAL 4

BEST PRACTICES IN LOW-POWER DESIGN: PART 2: INDUSTRIAL POWER REDUCTION EXPERIENCES

Speakers:Vivek De – Intel Corp., Hillsboro, ORRoberto Zafalon - STMicroelectronics, Agrate, Italy

Targeted Audience: Industrial design engineers and EDA professionals who want to learn aboutbasic low-power design techniques that can be used in industrial practice.

Description: Huge effort has been invested in the last decade to come up with a wide range ofdesign solutions that help in solving the power consumption problem for different types ofelectronic devices, components and systems. Some of those solutions turned out to be verypractical and effective, thus finding a path into commercial products of a different nature. Otherapproaches, that sounded promising on paper, showed too many limitations for attracting theattention of real designers. The objective of this tutorial is to offer the attendees some well-established, yet innovative recipes for addressing the power problem in the real life. Thepresentation will be structured into two half-day tutorials. The afternoon tutorial will focus onreal-practice industrial experiences in low-power design for state-of-the-art systems. Speakersfrom Intel and STMicroelectronics will report on the results obtained by the application of low-power techniques to proprietary designs covering different application domains (e.g. high-performance microprocessors, and hardware platforms for embedded multi-media processing). Agood mix of theory, application examples and real-life results will make the presentation valuableto designers interested in increasing their skills in low-power design and looking for solutionsusable in their next-day product development.

TUTORIAL 5

CHALLENGES AND SOLUTIONS IN THE DESIGN OF HIGH-FREQUENCY GLOBAL CLOCK DISTRIBUTIONS

Speakers:Phillip Restle – IBM Research, Yorktown Heights, NYKen Shepard - Columbia Univ., New York, NY

Targeted Audience: Industrial design engineers and EDA professionals who want to learn aboutglobal clock distribution techniques in industrial practice.

Description: This tutorial will begin with an overview of techniques that have been used for thesuccessful design and analysis of global clock distributions. Popular methods of clockdistributions will be compared, including the strategy of a clock-grid driven by tunable trees usedby many of IBM’s recent microprocessors. Both the modeling and design of the wires in thesesystems is critical; interconnect analysis techniques based on PEEC modeling will be illustratedwith current-voltage animations. Despite past successes, current techniques for global clockdistribution (including trees, grids, and tree-driven grids) are facing increasing challenges indistributing low-skew and low-jitter clocks. Furthermore, the power dissipated by the clocknetwork is becoming a very significant fraction of the total power demands of the chip.Resonant clocking techniques, which resonate the clock capacitance with on-chip inductance,promise to ease these constraints, making possible low-skew and low-jitter clock distributions atreduced power. The inductance can come from on-chip wires (in the form of traveling wave andstanding wave clocks) or spiral inductor topologies embedded into the clock wiring network.Both oscillator and resonant load topologies can be employed. In the latter part of this tutorial,we will review resonant clock techniques and predict the future impact of the technology.

TUTORIAL 6

WHAT'S NEW IN ALGORITHMS FOR CAD SINCE YOU LEFT SCHOOL?

Speakers:Stephen Boyd – Stanford Univ., Stanford, CASachin Sapatnekar - Univ. of Minnesota, Minneapolis, MN

Target Audience: EDA and circuit design engineers and researchers.

Description: This tutorial covers two recent topics that are applicable in many IC design andEDA tasks: convex optimization, focusing on geometric programming (GP), and random walktechniques for solving systems of equations.After an overview of convex optimization and new efficient solution methods, the first focus ison GP, and a powerful extension called generalized geometric programming (GGP). Aftercovering the basics of GP and GGP modeling, their use in digital and analog device sizingproblems will be illustrated, including topics such as design over corners, joint electrical andphysical design, and fitting functions or empirical data in a form compatible with GP.The second topic is a new class of methods that solve systems of positive definite equations, notby the conventional direct or iterative methods, but by running a set of random walks on a circuitgraph. These methods have been successfully used in applications including capacitanceextraction, analyzing on-chip power grids, and checking electrostatic discharge (ESD) networks,and have large potential for many other EDA problems, and can give good tradeoffs betweenaccuracy and runtime.

SUNDAY PANEL:

IC DESIGN IN 65 NM AND BEYOND: EVOLUTION OR REVOLUTION?PANEL: CAD ROADMAPS - USEFUL, REDUNDANT OR EVEN OBSTRUCTIVE?

Moderator: John Cohn - IBM Corp., Essex Junction, VT

In this concluding panel discussion, our industrial and academic experts will gather to contrasttheir different opinions about 65nm design, and we hear comments and questions from theaudience. What are the showstoppers in designing integrated circuits in 65nm and beyond? Arethere any emerging solutions? olume markets like microprocessors? Come, listen, and learnabout the answers to these questions.

Panelists:

Uwe Fassnacht - IBM Corp., Sunnyvale, CAJamil Kawa - Synopsys, Inc., Mountain View, CASani R. Nassif - IBM Corp., Austin, TXRalph Otten - TU Eindhoven, Eindhoven, The NetherlandsWayne Wolf - Princeton Univ., Princeton, NJYervent Zorian - Virage Logic, Fremont, CA

MONDAY PANEL:DIVINE FOR DOLLARS

Moderator: Steve Kang - Univ. of California, Santa Cruz, CAAlthough EDA spending is a small portion of the semiconductor chip budget, EDA can enablesignificant advances in chip productivity and capability. Technologies such as physicalverification, place and route, and synthesis have made fundamental changes in how chips aredesigned. The time periods between significant innovations are generally filled with incrementalimprovements in EDA tools that generally involve performance, capacity, flow or featureimprovements. As an industry, EDA needs to seek innovative ways to deliver greater value to ourcustomers. If EDA is unable to provide the semiconductor industry with increased value from itsproducts, it will not share in the growth of the semiconductor business.

The EDA industry needs to look to a variety of sources to provide inspiration for innovations thatcan deliver new value to semiconductor design and manufacturing. Academia and semiconductorroadmaps are common sources of inspiration. This panel seeks to obtain insights from ourcustomers, namely designers. We invited five specialists with a variety of design backgrounds todiscuss the next EDA innovations they think can change the way chips are developed. Thepanelists will first present proposals for these innovations. Then the table is turned. Afterdiscussion with the audience, the panelists will decide and justify which proposal they wouldactually back if they were an investor. Select members of the audience will vote on the proposalthat, in its opinion, will change the way chips are designed. Business plan development will bethe responsibility of the audience members after the conference.

Panelists:

Seth Copen Goldstein - Carnegie Melon Univ., Pittsburgh, PAMark McDermott - AMCC, Austin, TXBorivoje Nikolic - Univ. of California, Berkeley, CAKris Pister - Dust Networks, Berkeley, CASteve Teig - Tabula, Mountain View, CA

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Table of Contents

Conference Committee ............................................................................................................... iii Foreward ...................................................................................................................................... iv Awards ........................................................................................................................................... v Technical Program Committee .................................................................................................. vi Reviewers .................................................................................................................................. viii Keynote .......................................................................................................................................... x Tutorial 1: Best Practices in Low Power Design:

Part 1: Power Reduction Techniques ........................................................... xi Tutorial 2: Physical Design at 90NM and Beyond ......................................................... xii Tutorial 3: Signal Integrity and Reliability of Integrated Circuits:

Practical Considerations at 130 NM and Below ........................................ xiii Tutorial 4: Best Practices in Low-Power Design:

Part 2: Industrial Power Reduction Experiences ...................................... xiv Tutorial 5: Challenges and Solutions in the Design of High-Frequency

Global Clock Distributions ............................................................................ xv Tutorial 6: What’s New in Algorithms for CAD Since You Left School? ................... xvi Sunday Panel: IC Design in 65NM and Beyond: Evolution or Revolution? .................. xvii Monday Panel: Divine for Dollars ....................................................................................... xviii

Session 1A Statistical Modeling and Optimization Methodologies Moderators: Duane S. Boning - Massachusetts Institute of Tech., Cambridge, MA

Sani R. Nassif - IBM Corp., Austin, TX

1A.1 Asymptotic Probability Extraction for Non-Normal Distributions of Circuit Performance ......................................................................................... 2

Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi

1A.2 Statistical Design and Optimization of SRAM Cell for Yield Enhancement ........................ 10 Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy

1A.3 Gate Sizing for Crosstalk Reduction under Timing Constraints by Lagrangian Relaxation ............................................................................................................... 14

Debjit Sinha, Hai Zhou

Session 1B System-Level Energy Management Moderators: Elaheh Bozorgzadeh - Univ. of California, Irvine, CA

Paolo Ienne - Swiss Federal Institute of Tech., Lausanne, Switzerland

1B.1 Optimizing Mode Transition Sequences in Idle Intervals for Component-Level and System-Level Energy Minimization ................................................... 21

Jinfeng Liu, Pai H. Chou

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1B.2 Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Considering Variable and Fixed Components of the System Power Dissipation ................. 29

Kihwan Choi, Wonbok Lee, Ramakrishna Soma, Massoud Pedram

1B.3 The Effects of Energy Management on Reliability in Real-Time Embedded Systems ........ 35 Dakai Zhu, Rami Melhem, Daniel Mossé

Session 1C Equivalence Verification Moderators: Hanna Ziyad - Intel Corp., Hafia, Israel

Carl Pixley - Synopsys, Inc., Hillsboro, OR

1C.1 DAG-Aware Circuit Compression for Formal Verification ................................................... 42 Per Bjesse, Arne Borälv

1C.2 Dynamic Transition Relation Simplification for Bounded Property Checking .................... 50 Andreas Kuehlmann

1C.3 Theoretical Framework for Compositional Sequential Hardware Equivalence Verification in Presence of Design Constraints ....................................................................... 58

Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna

1C.4 Checking Consistency of C and Verilog using Predicate Abstraction and Induction .......... 66 Daniel Kroening, Edmund Clarke

Session 1D Advances in Interconnect Analysis Moderators: Sharad Kapur - Integrand Software, Hoboken, NJ

Joel R. Phillips - Cadence Berkeley Labs, San Jose, CA

1D.1 SAPOR: Second-Order Arnoldi Method for Passive Order Reduction of RCS Circuits ........................................................................................................ 74

Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles Chiang, Dian Zhou

1D.2 SPRIM: Structure-Preserving Reduced-Order Interconnect Macromodeling .................... 80 Roland W. Freund

1D.3 Sparse and Efficient Reduced Order Modeling of Linear Subcircuits with Large Number of Terminals ............................................................................................. 88

Peter Feldmann, Frank Liu

1D.4 Fast Simulation of VLSI Interconnects .................................................................................... 93 Jitesh Jain, Cheng-Kok Koh, Venkataramanan R. Balakrishnan

Session 2A Soft Error Rate Analysis Moderators: Duncan M. Walker - Texas A&M, College Station, TX

Louis Scheffer - Cadence Design Systems, Inc., San Jose, CA

2A.1 Cost-Effective Radiation Hardening Technique for Combinational Logic ......................... 100 Quming Zhou, Kartik Mohanram

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2A.2 Improving Soft-Error Tolerance of FPGA Configuration Bits ............................................ 107 Suresh Srinivasan, Aman Gayasen, N. Vijaykrishnan,

M. Kandemir, Y. Xie, M. J. Irwin

2A.3 A Soft Error Rate Analysis (SERA) Methodology ................................................................ 111 Ming Zhang, Naresh R. Shanbhag

Session 2B Application Specific Memory and Processor Architecture Design Techniques Moderators: Nikil Dutt - Univ. of California, Irvine, CA

Hiroyuki Tomiyama - Nagoya Univ., Nagoya, Japan

2B.1 Banked Scratch-Pad Memory Management for Reducing Leakage Energy Consumption ............................................................................... 120

M. Kandemir, M. J. Irwin, G. Chen, I. Kolcu

2B.2 Reducing Cache Misses by Application-Specific Re-Configurable Indexing ..................... 125 K. Patel, L. Benini, E. Macii, M. Poncino

2B.3 DynamoSim: A Trace-Based Dynamic Compiled Instruction Set Simulator ..................... 131 Wai Sum Mong, Jianwen Zhu

Session 2C Embedded Tutorial: The Care and Feeding of your Statistical Static Timer Moderator: Sachin Sapatnekar - Univ. of Minnesota, Minneapolis, MN

2C.1 The Care and Feeding of your Statistical Static Timer ........................................................ 138 Sani R. Nassif, Duane Boning, Nagib Hakim

Session 3A Crosstalk-Aware Timing and Noise Analysis Moderators: Charlie Chung-Ping Chen - National Taiwan Univ., Taipei, Taiwan

Noel Menezes - Intel Corp., Hillsboro, OR

3A.1 Analytical Modeling of Crosstalk Noise Waveform using Weibull Function ..................... 141 Alireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda

3A.2 A Robust Cell-Level Crosstalk Delay Change Analysis ........................................................ 147 Igor Keller, Ken Tseng, Nishath Verghese

3A.3 Timing Macro-Modeling of IP Blocks with Crosstalk .......................................................... 155 Ruiming Chen, Hai Zhou

3A.4 Delay Noise Pessimism Reduction by Logic Correlations .................................................... 160 A. Glebov, S. Gavrilov, R. Soloviev, V. Zolotov, M. R. Becer, C. Oh, R. Panda

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Session 3B System Software Optimizations Moderators: Wolfgang Nebel - Univ. of Oldenburg, Oldenburg, Germany

Joerg Henkel - Univ. of Karlsruhe, Karlsruhe, Germany

3B.1 Factoring and Eliminating Common Subexpressions in Polynomial Expressions ............. 169 Anup Hosangadi, Farzan Fallah, Ryan Kastner

3B.2 Custom-Optimized Multiplierless Implementations of DSP Algorithms ............................ 175 Markus Püschel, Adam C. Zelinski, James C. Hoe

3B.3 A Quantitative Study and Estimation Models for Extensible Instructions in Embedded Processors .................................................................................... 183

Newton Cheung, Sri Parameswaran, Jörg Henkel

3B.4 Code Partitioning for Synthesis of Embedded Applications with Phantom ....................... 190 André C. Nácul, Tony Givargis

Session 3C New Directions in Verification Moderators: Stuart Swan - Cadence Design Systems, Inc., Redwood City, CA

Adnan Aziz - Univ. of Texas, Austin, TX

3C.1 Formal Verification Coverage: Computing the Coverage Gap between Temporal Specifications ............................................................................................ 198

Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni

3C.2 Debugging Sequential Circuits Using Boolean Satisfiability ................................................ 204 Moayad Fahim Ali, Andreas Veneris, Sean Safarpour, Rolf Drechsler,

Alexander Smith, Magdy Abadir

3C.3 Towards Formal Verification of Analog Designs .................................................................. 210 Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar

3C.4 Automatic Translation of Behavioral Testbench for Fully Accelerated Simulation .......... 218 Young-Il Kim, Chong-Min Kyung

Session 3D Algorithms and Modeling Techniques for Bio and Nano Technologies Moderators: Andrew B. Kahng - Univ. of California, San Diego, La Jolla, CA

Sitaraman Iyer – Intel Corp., Santa Clara, CA

3D.1 Architectural-Level Synthesis of Digital Microfluidics-Based Biochips .............................. 223 Fei Su, Krishnendu Chakrabarty

3D.2 Simultaneous Design and Placement of Multiplexed Chemical Processing Systems on Microchips .......................................................................................... 229

Anton J. Pfeiffer, Tamal Mukherjee, Steinar Hauan

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3D.3 A Circuit Model for Carbon Nanotube Interconnects: Comparative Study with Cu Interconnects for Scaled Technologies ............................................................................. 237

Arijit Raychowdhury, Kaushik Roy

3D.4 Hybrid Techniques for Electrostatic Analysis of Nanowires ................................................ 241 Gang Li, N. R. Aluru

Session 4A Developments in Timing Analysis and Optimization Moderators: David Overhauser - Cadence Design Systems, Inc., San Jose, CA

Tom Spyrou - Consultant, Sunnyvale, CA

4A.1 Computation of Signal Threshold Crossing Times Directly from Higher Order Moments ........................................................................................................... 246

Yehea I. Ismail, Chirayu S. Amin

4A.2 Modeling Unbuffered Latches for Timing Analysis .............................................................. 254 Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail

4A.3 A Flexibility Aware Budgeting for Hierarchical Flow Timing Closure .............................. 261 Olivier Omedes, Michel Robert, Mohamed Ramdani

Session 4B Energy Efficiency and Interconnect Design Moderators: Engling Yeo - Univ. of California, Berkeley, CA

Thomas Burd - Consultant, Sunnyvale, CA

4B.1 Energy Optimization for a Two-Device Data Flow Chain .................................................... 268 Ravishankar Rao, Sarma Vrudhula

4B.2 A Power Aware System Level Interconnect Design Methodology for Latency-Insensitive Systems .................................................................................................... 275

Vikas Chandra, Herman Schmit, Anthony Xu, Larry Pileggi

4B.3 Exploiting Level Sensitive Latches in Wire Pipelining ......................................................... 283 Vikram Seth, Min Zhao, Jiang Hu

Session 4C Floorplanning for Advanced Technologies Moderators: Igor L. Markov - Univ. of Michigan, Ann Arbor, MI

Deshanad Singh - Altera, Toronto, ON, Canada

4C.1 Floorplan Design for Multi-Million Gate FPGAs .................................................................. 292 Lei Cheng, Martin D. F. Wong

4C.2 Temporal Floorplanning using the T-Tree Formulation ...................................................... 300 Ping-Hung Yuh, Chia Lin Yang, Yao-Wen Chang

4C.3 A Thermal-Driven Floorplanning Algorithm for 3D ICs ..................................................... 306 Jason Cong, Jie Wei, Yan Zhang

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Session 4D Robust Design Tools Moderators: Nagib Z. Hakim - Intel Corp., Santa Clara, CA

Haihua Su - IBM Corp., Austin, TX

4D.1 A Chip-Level Electrostatic Discharge Simulation Strategy ................................................. 315 Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar

4D.2 Efficient Full-Chip Thermal Modeling and Analysis ............................................................ 319 Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra

4D.3 Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design ......................................................................................................... 327

Zhijian Lu, Wei Huang, John Lach, Mircea Stan, Kevin Skadron

Session 5A Embedded Tutorial: Variability Impact on Design Moderator: Soha Hassoun - Tufts Univ., Medford, MA

5A.1 Process and Environmental Variation Impacts on ASIC Timing ........................................ 336 Paul S. Zuchowski, Peter A. Habitz, Jerry D. Hayes, Jeffery H. Oppold

5A.2 The Impact of Device Parameter Variations on the Frequency and Performance of VLSI Chips .................................................................................................... 343

Samie B. Samaan

5A.3 Variability in Sub-100nm SRAM Designs .............................................................................. 347 Raymond Heald, Ping Wang

Session 5B Architectural Issues in System Synthesis Moderators: Tony Givargis - Univ. of California, Irvine, CA

Ryan Kastner - Univ. of California, Santa Barbara, CA

5B.1 Application-Specific Buffer Space Allocation for Networks-on-Chip Router Design ........ 354 Jingcao Hu, Radu Marculescu

5B.2 Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems .................................................. 362

Alexandru Andrei, Marcus Schmitz, Petru Eles, Zebo Peng, Bashir M. Al Hashimi

5B.3 Hardware/Software Managed Scratchpad Memory for Embedded System ...................... 370 Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatović

Session 5C Integrated Placement Applications Moderators: Hai Zhou - Northwestern Univ., Evanston, IL

Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan

5C.1 Physical Placement Driven by Sequential Timing Analysis ................................................. 379 Aaron P. Hurst, Philip Chong, Andreas Kuehlmann

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5C.2 On Interactions between Routing and Detailed Placement .................................................. 387 Devang Jariwala, John Lillis

5C.3 Routability-Driven Placement and White Space Allocation ................................................. 394 Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden

5C.4 True Crosstalk Aware Incremental Placement with Noise Map ......................................... 402 Haoxing Ren, David Z. Pan, Paul G. Villarrubia

Session 5D Novel Directions in Logic Synthesis Moderators: Ankur Srivastava - Univ. of Maryland, College Park, MD

Elena V. Dubrova - Royal Institute of Tech., Stockholm, Sweden

5D.1 On Breakable Cyclic Definitions ............................................................................................. 411 Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton

5D.2 Logical Effort based Technology Mapping ............................................................................ 419 Shrirang K. Karandikar, Sachin S. Sapatnekar

5D.3 Variability Inspired Implementation Selection Problem ...................................................... 423 Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava

5D.4 m-Trie: An Efficient Approach to On-Chip Logic Minimization ........................................ 428 Seraj Ahmed, Rabi Mahapatra

Session 6A Embedded Tutorial: World-Level Methods in Formal Verification Moderator: Ken McMillan - Cadence Design Systems, Inc., Berkeley, CA

6A.1 Verifying Properties of Hardware and Software by Predicate Abstraction and Model Checking ........................................................................................... 437

Randal E. Bryant, Sriram K. Rajamani

Session 6B Interconnect Coding and Optimization Moderators: Rhett Davis - North Carolina State Univ., Raleigh, NC

Borivoje Nikolic - Univ. of California, Berkeley, CA

6B.1 Soft Self-Synchronising Codes for Self-Calibrating Communication .................................. 440 Frédéric Worm, Paolo Ienne, Patrick Thiran

6B.2 SILENT: Serialized Low Energy Transmission Coding for On-Chip Interconnection Networks ....................................................................................... 448

Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo

6B.3 Optimal Wire Retiming without Binary Search .................................................................... 452 Chuan Lin, Hai Zhou

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Session 6C Statistical Timing Methods Moderators: Tom Spyrou - Consultant, Sunnyvale, CA

Yehea I. Ismail - Northwestern Univ., Evanston, IL

6C.1 Interval-Valued Reduced Order Statistical Interconnect Modeling .................................... 460 James D. Ma, Rob A. Rutenbar

6C.2 Static Statistical Timing Analysis for Latch-Based Pipeline Designs .................................. 468 Mango C.-T. Chao, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu

6C.3 Efficient Statistical Timing Analysis through Error Budgeting .......................................... 473 Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava

Session 6D New Methods in Power Grid Analysis Moderators: Chandramouli V. Kashyap - Flexlogics, Inc., Sunnyvale, CA

David Blaauw - Univ. of Michigan, Ann Arbor, MI

6D.1 Voltage-Drop-Constrained Optimization of Power Distribution Network based on Reliable Maximum Current Estimates ................................................................... 479

N. E. Evmorfopoulos, D. P. Karampatzakis, G. I. Stamoulis

6D.2 Fast Flip-Chip Power Grid Analysis via Locality and Grid Shells ...................................... 485 Eli Chiprout

6D.3 HiSIM: Hierarchical Interconnect-Centric Circuit Simulator ............................................ 489 Tsung-Hao Chen, Jeng-Liang Tsai, Charlie C.-P. Chen, Tanay Karnik

Session 7A Advances in SAT-Based Verification Moderators: Ken McMillan - Cadence Design Systems, Inc., Berkeley, CA

Per Bjesse - Synopsys, Inc., Hillsboro, OR

7A.1 Guiding CNF-SAT Search via Efficient Constraint Partitioning ........................................ 498 Vijay Durairaj, Priyank Kalla

7A.2 Incremental Deductive and Inductive Reasoning for SAT-Based Bounded Model Checking ........................................................................................................ 502

Liang Zhang, Mukul R. Prasad, Michael S. Hsiao

7A.3 Efficient SAT-Based Unbounded Symbolic Model Checking using Circuit Cofactoring ........................................................................................................ 510

Malay K. Ganai, Aarti Gupta, Pranav Ashar

7A.4 Efficient Computation of Small Abstraction Refinements ................................................... 518 Bing Li, Fabio Somenzi

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Session 7B Power and Layout-Driven Logic Optimization Moderators: Michel Berkelaar - Magma Design Automation, Eindhoven The Netherlands

Yusuke Matsunaga - Kyushu Univ., Kagus, Japan

7B.1 Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction ....................................................................................................... 527

Feng Gao, John P. Hayes

7B.2 Leakage Control through Fine-Grained Placement and Sizing of Sleep Transistors ........ 533 Vishal Khandelwal, Ankur Srivastava

7B.3 A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits .............................................................................................. 537

Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang

7B.4 A New Incremental Placement Algorithm and its Application to Congestion-Aware Divisor Extraction .................................................................................... 541

Satrajit Chatterjee, Robert Brayton

Session 7C Advances in Floorplanning and Placement Moderators: Dwight D. Hill - Synopsys, Inc., Mountain View, CA

Zhigang Pan - Univ. of Texas, Austin, TX

7C.1 Unification of Partitioning, Placement and Floorplanning .................................................. 550 Saurabh N. Adya, Shubhyant Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov

7C.2 Multilevel Expansion-Based VLSI Placement with Blockages ............................................. 558 Bo Hu, Malgorzata Marek Sadowska

7C.3 An Analytic Placer for Mixed-Size Placement and Timing-Driven Placement .................. 565 Andrew B. Kahng, Qinke Wang

7C.4 Engineering Details of a Stable Force-Directed Placer ......................................................... 573 Kristofer Vorwerk, Andrew Kennings, Anthony Vannelli

Session 7D Programmable Fabrics for Structured Design Moderators: Radu Marculescu - Carnegie Mellon Univ., Pittsburgh, PA

Tanay Karnik - Intel Corp., Hillsboro, OR

7D.1 An Integrated Design Flow for a Via-Configurable Gate Array ......................................... 582 Yajun Ran, Malgorzata Marek-Sadowska

7D.2 A METAL and VIA Maskset Programmable VLSI Design Methodology using PLAs ......................................................................................................... 590

Nikhil Jayakumar, Sunil P. Khatri

7D.3 Analysis and Evaluation of a Hybrid Interconnect Structure for FPGAs .......................... 595 Renqiu Huang, Ranga Vemuri

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7D.4 Low-Power Programmable Routing Circuitry for FPGAs .................................................. 602 Jason H. Anderson, Farid N. Najm

Session 8A New Issues in Clocking Moderators: Premal Buch - Magma Design Automation, Inc., Cupertino, CA

Weiping Shi - Texas A&M Univ., College Station, TX

8A.1 A Yield Improvement Methodology using Pre- and Post-Silicon Statistical Clock Scheduling .................................................................................................... 611

Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja

8A.2 Clock Schedule Verification Under Process Variations ........................................................ 619 Ruiming Chen, Hai Zhou

8A.3 A Novel Clock Distribution and Dynamic De-Skewing Methodology ................................. 626 Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri

Session 8B Innovative Models/Methods in Analog and Digital Diagnosis Moderators: Linda Milor - Georgia Institute of Tech., Atlanta, GA

Manuel d’Abreu - SUN Microsystems, Sunnyvale, CA

8B.1 On Per-Test Fault Diagnosis using the X-Fault Model ......................................................... 633 Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng (L.-T.) Wang,

Kewal K. Saluja, Kozo Kinoshita

8B.2 Diagnosis of Small-Signal Parameters for Broadband Amplifiers through S-Parameter Measurements and Sensitivity-Guided Evolutionary Search ........................ 641

Fang Liu, Sule Ozev, Martin Brooke

8B.3 An Efficient Method for Improving the Quality of Per-Test Fault Diagnosis .................... 648 Chunsheng Liu

Session 8C Estimation and Management of Design Metrics Moderators: Seda Ogrenci Memik - Northwestern Univ., Evanston, IL

Barry Pangrle - Synopsys, Inc., Mountain View, CA

8C.1 A Unified Theory of Timing Budget Management ................................................................ 653 Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh

8C.2 Dynamic Range Estimation for Nonlinear Systems .............................................................. 660 Bin Wu, Jianwen Zhu, Farid N. Najm

8C.3 Power Estimation for Cycle-Accurate Functional Descriptions of Hardware .................... 668 Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

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Session 8D Advanced Analog/RF Macromodeling and Simulation Moderators: Gu-Yeon Wei - Harvard Univ., Cambridge, MA

Joel R. Phillips - Cadence Berkeley Labs, San Jose, CA

8D.1 Efficient Harmonic Balance Simulation using Multi-Level Frequency Decomposition ....................................................................................................... 677

Peng Li, Lawrence T. Pileggi

8D.2 Frequency Domain Simulation of High-Q Oscillators with Homotopy Methods ............... 683 Xiaochun Duan, Kartikeya Mayaram

8D.3 Automated Oscillator Macromodelling Techniques for Capturing Amplitude Variations and Injection Locking ........................................................................ 687

Xiaolue Lai, Jaijeet Roychowdhury

Session 9A Estimation Techniques for Physical Design Moderators: Martin D.F. Wong - Univ. of Illinois, Urbana, IL

Hardy K. Leung - Magma Design Automation, Santa Clara, CA

9A.1 FLUTE: Fast Lookup Table based Wirelength Estimation Technique .............................. 696 Chris Chu

9A.2 Wire-Length Prediction using Statistical and Probabilistic Techniques ............................. 702 Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava,

Miodrag Potkonjak

9A.3 Accurate Estimation of Global Buffer Delay within a Floorplan ........................................ 706 Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, C. N. Sze

Session 9B Timing Model Validation and Efficient On-Chip Test Compression Moderators: Martin Margala - Univ. of Rochester, Rochester, NY

Dan Saab - Case Western Reserve Univ., Cleveland, OH

9B.1 A Path-Based Methodology for Post-Silicon Timing Validation .......................................... 713 Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng

9B.2 Frugal Linear Network-Based Test Decompression for Drastic Test Cost Reductions .................................................................................................. 721

Wenjing Rao, Alex Orailoglu, George Su

9B.3 Design Space Exploration for Aggressive Test Cost Reduction in Circular Scan Architectures .................................................................................................... 726

Baris Arslan, Alex Orailoglu

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Session 9C Embedded Tutorial: Emerging Technologies on the Design Manufacturing Interface

Moderator: Andreas Kuehlmann - Cadence Berkeley Labs, Berkeley, CA

9C.1 Design/Process Learning from Electrical Test ....................................................................... 733 Bernd Koenemann

9C.2 Backend CAD Flows for “Restrictive Design Rules” ............................................................ 739 Mark Lavin, Fook-Luen Heng, Greg Northrop

Session 9D Optimization Techniques for FPGAs and Reconfigurability Moderators: James C. Hoe - Carnegie Mellon Univ., Pittsburgh, PA

Narendra V. Shenoy - Synopsys, Inc., Mountain View, CA

9D.1 Hermes: LUT FPGA Technology Mapping Algorithm for Area Minimization with Optimum Depth .............................................................................. 748

Maxim Teslenko, Elena Dubrova

9D.2 DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs ........................................................................................................................... 752

Deming Chen, Jason Cong

9D.3 Vdd Programmability to Reduce FPGA Interconnect Power .............................................. 760 Fei Li, Yan Lin, Lei He

9D.4 Configuration Bitstream Compression for Dynamically Reconfigurable FPGAs ............. 766 Ju Hwa Pan, Tulika Mitra, Weng-Fai Wong

Session 10A Innovative Methods in High-Level Design Moderators: Forrest D. Brewer - Univ. of California, Santa Barbara, CA

Michael Kishinevsky - Intel Corp., Hillsboro, OR

10A.1 High-Level Synthesis: An Essential Ingredient for Designing Complex ASICs ................. 775 Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave

10A.2 High-Level Synthesis using Computation-Unit Integrated Memories ................................ 783 Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

10A.3 Improved use of the Carry-Save Representation for the Synthesis of Complex Arithmetic Circuits ............................................................................. 791

Ajay K. Verma, Paolo Ienne

Session 10B Power Analysis and Optimization Moderators: David Overhauser - Cadence Design Systems, Inc., San Jose, CA

Rajendran Panda - FreeScale Semiconductor Inc., Austin, TX

10B.1 Formal Derivation of Optimal Active Shielding for Low-Power On-Chip Buses .............. 800 Maged Ghoneima, Yehea Ismail

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10B.2 A General Framework for Probabilistic Low-Power Design Space Exploration Considering Process Variation ................................................................................................ 808

Ashish Srivastava, Dennis Sylvester

10B.3 Timing Analysis Considering Spatial Power/Ground Level Variation ............................... 814 Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera

Session 10C Routing Moderators: Hannah Yang - Intel Corp., Hillsboro, OR

Charles Chiang - Synopsys, Inc., Mountain View, CA

10C.1 Simultaneous Escape Routing and Layer Assignment for Dense PCBs .............................. 822 Muhammet Mustafa Ozdal, Martin D. F. Wong

10C.2 A Provably Good Algorithm for High Performance Bus Routing ....................................... 830 Muhammet Mustafa Ozdal, Martin D. F. Wong

10C.3 Simultaneous Short-Path and Long-Path Timing Optimization for FPGAs ...................... 838 Ryan Fung, Vaughn Betz, William Chow

Session 10D Analog Sizing and Optimization Moderators: Mar Hershenson - Sabio Labs., Palo Alto, CA

Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN

10D.1 Analog Performance Space Exploration by Fourier-Motzkin Elimination with Application to Hierarchical Sizing .......................................................................................... 847

Guido Stehr, Helmut Graeb, Kurt Antreich

10D.2 Robust Analog/RF Circuit Design with Projection-Based Posynomial Modeling .............. 855 Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi

10D.3 Techniques for Improving the Accuracy of Geometric-Programming based Analog Circuit Design Optimization ...................................................................................... 863

Jintae Kim, Jaeseo Lee, Lieven Vandenberghe, Chih-Kong Ken Yang

Session 11A Variational Analysis of Interconnects Moderators: Chung-Kuan Cheng - Univ. of California, San Diego, La Jolla, CA

Nick Van Der Meijs - Delft Univ. of Tech., Delft, The Netherlands

11A.1 Variational Interconnect Analysis via PMTBR ..................................................................... 872 Joel R. Phillips

11A.2 Stochastic Analysis of Interconnect Performance in the Presence of Process Variations ................................................................................................ 880

Janet Wang, Praveen Ghanta, Sarma Vrudhula

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11A.3 A Stochastic Integral Equation Method for Modeling the Rough Surface Effect on Interconnect Capacitance ................................................................................................... 887

Zhenhai Z. Zhu, Alper Demir, Jacob White

Session 11B Test Generation for New Fault Models and Circuits Moderator: Bruce Cory - Nvidia, Santa Clara, CA

11B.1 Detection of Multiple Transitions in Delay Fault Test of SPARC64 Microprocessor ........ 893 Daisuke Maruyama, Akira Kanuma, Takashi Mochiyama, Hiroaki Komatsu,

Yaroku Sugiyama, Noriyuki Ito

11B.2 Minimizing the Number of Test Configurations for FPGAs ................................................ 899 Erik Chmelař

11B.3 SPIN-TEST: Automatic Test Pattern Generation for Speed-Independent Circuits .......... 903 Feng Shi, Yiorgos Makris

Session 11C Embedded Tutorials: How to Bridge the Abstraction Gap in System Level Modeling and Design?

Moderator: Wolfgang Rosenstiel - Univ. of Tuebingen, Tuebingen, Germany

11C.1 How to Bridge the Abstraction Gap in System Level Modeling and Design ...................... 910 A. Bernstein, M. Burton, F. Ghenassia

Session 11D Hierarchical Mixed-Signal Modeling and Design Moderators: Pei-Hsin Ho - Synopsys ATG, Portland, OR

Ken McMillan - Cadence Design Systems, Berkeley, CA

11D.1 Analyzing Software Influences on Substrate Noise: An ADC Perspective ........................ 916 ByungTae Kang, N. Vijaykrishnan, Mary Jane Irwin

11D.2 Design Space Exploration for a UMTS Front-End Exploiting Analog Platforms .............. 923 F. De Bernardinis, S. Gambini, F. Vincis, F. Svelto, R. Castello, A. Sangiovanni

Vincentelli

11D.3 Adaptive Sampling and Modeling of Analog Circuit Performance Parameters with Pseudo-Cubic Splines ...................................................................................................... 931

Glenn Wolfe, Ranga Vemuri

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ICCAD-2005

Proposals for Panel Sessions and Tutorials are also invited.Panel suggestions should describe the topic and should list suggestedparticipants. Tutorial suggestions should focus on the state-of-the art in aspecific area. Both half-day and full-day tutorial suggestions are welcome.

PAPER SUBMISSION: ICCAD submissions must be made electronicallyin PDF format through the ICCAD web site. Reference the ICCAD web pagefor instructions on electronic submissions: http://www.iccad.com.

Please submit the following in PDF format:

• One pdf file which should contain the complete paper including the

title and abstract, but excluding the authors’ names and affiliations

This file should be no more than 8 pages using proceedings formatdouble columned, 9pt. or 10pt. fonts including figures, tables andreferences. (In the proceedings, four pages are free of charge and eachpage beyond four pages is charged $100.00 per page).

• Papers in the wrong format, exceeding the eight page limit, or

identifying the authors or their affiliations will be rejected

immediately.

- Previously published papers will not be considered; this includespapers appearing in published workshop proceedings. Paperspresented only orally, or only available via informal distributionat a workshop or meeting can be submitted for publicationat ICCAD.

- Authors should clearly address the significance of their contributionas part of the paper.

AUTHOR’S SCHEDULE

Deadline for submissions: April 20, 2005

Notification of acceptance: June 30, 2005

Deadline for final version: August 8, 2005

Papers will not be accepted for submission after 5:00 PM

Mountain Daylight Time, April 20, 2005. This deadline is firm

and inflexible. No exceptions will be made.

One or more of the outstanding submissions will be recognized withthe: IEEE/ACM William J. McCalla ICCAD Best Paper Award

Please direct all correspondence to:

ICCAD Publications Department

MP Associates, Inc. Telephone: (303) 530-45625405 Spine Rd., Ste. 102 Fax: (303) 530-4334Boulder, CO 80301 Email: iccadpapers@mpassociates.com

November 6-10, 2005

ICCAD Home Page: http://www.iccad.com

In addition to traditional CAD topics, ICCAD has expanded its focus toinclude innovative design technologies for devices, circuits, andsystems. Original technical submissions focusing on, but not limited to,the following topics are invited:

ICCAD serves the EDA and Design professionals,

highlighting new challenges and innovative solutions for

Integrated-Circuit Design Technologies and Systems

C A L L F O R P A P E R S

DOUBLETREE HOTEL

SAN JOSE, CA

1) PHYSICAL DESIGN AND TEST

1.1 High-Level physical design and synthesis. Estimation and hierarchymanagement. Partitioning, floorplanning and global placement.

1.2 Routing and detailed physical design. Detailed and incrementalplacement, detailed routing, post-placement layout and optimization.Clock network Design.

1.3 Design and CAD for analog, RF, and mixed signal. Mixed technologydesign (thermal, packaging, micro-mechanical).

1.4 Testing. Fault modeling, delay test, analog and mixed signal test. Faultsimulation. ATPG. BIST and DFT. Memory test and repair. Core,system, and, MEMS test. Power issues in Test. Test data compression.

2) SYNTHESIS AND SYSTEM DESIGN

2.1 Logic synthesis. Interaction between physical design and logic synthesis.Technology mapping. Synthesis for FPGAs. Asynchronous circuitdesign. Optimization for area, timing, power, and yield.

2.2 High-Level synthesis. Refinement Techniques. Direct compilation andpost-optimization. Physically aware techniques for early exploration.Micro-architectural transformations. Protocol and interface design forcorrectness. Memory system synthesis.

2.3 System synthesis. HW and SW co-optimization and co-exploration.Multi-processor systems (heterogeneous, homogeneous,reconfigurable). HW/SW platforms. Compilation and code generationTechniques.

2.4 Embedded and programmable systems. Real-time software and RTOS.Reuse techniques. Rapid system prototyping. Methodologies and case studies.

3) VERIFICATION, MODELING AND SIMULATION

3.1 Interconnect parameter extraction and circuit model generation.3.2 Signal integrity analysis. Power/Ground network analysis.Thermal analysis.3.3 Gate, switch, and circuit level timing and power analysis. LVS.3.4 Formal verification techniques. HW/SW co-simulation. Switch, logic and

behavioral simulation and design validation. Software verification.Emulation.

4) INNOVATIVE DESIGN TECHNOLOGIES FOR DEVICES, CIRCUITS

AND SYSTEMS

4.1 Novel ideas in layout, circuits, and logic. Sample topics: 3-D integration,X-routing, multi-threshold devices, biasing, novel transistors.

4.2 Trends and perspectives in architecture and system-level design, withemphasis on power, performance and configurability: SoC, NoC, SiP,and programmable platforms.

4.3 Analysis and design for manufacturability, reliability, and robustness.Design fabrics such as FPGAS, mask and via-programmable fabrics,and structured ASICS.

4.4 Emerging technologies. Modeling, simulation and analysis for newdevice structures. Nanotechnology, MEMS, molecular andbioelectronics, single electron and optical/photonic devices and circuits.

NOVEMBER 6-10, 2005

AUTHOR INFORMATION AND FORMAT

GENERAL CHAIR

Majid Sarrafzadeh

Univ. of California

majid@cs.ucla.edu

PROGRAM CHAIR

Soha Hassoun

Tufts University

soha@cs.tufts.edu

PROGRAM VICE CHAIR

Georges Gielen

Katholieke University Leuven

georges.gielen@esat.kuleuven.ac.be

TUTORIAL CHAIR

Sani Nassif

IBM Corp.

nassif@us.ibm.com

PAST CHAIR

Hidetoshi Onodera

Kyoto Univ.

onodera@i.kyoto-u.ac.jp

NOVEMBER 6-10, 2005

AREAS OF INTEREST

Author Index

A Abadir, Magdy ..................................................... 204 Adya, Saurabh N. ................................................ 550 Ahmed, Seraj ....................................................... 428 Al Hashimi, Bashir M. ......................................... 362 Ali, Moayad Fahim .............................................. 204 Alpert, Charles J. ................................................. 706 Aluru, N. R. ......................................................... 241 Amin, Chirayu S. ......................................... 246, 254 Anderson, Jason H. .............................................. 602 Andrei, Alexandru ............................................... 362 Antreich, Kurt ...................................................... 847 Armoni, Roy ........................................................ 198 Arslan, Baris ........................................................ 726 Arvind .................................................................. 775 Ashar, Pranav ...................................................... 510 Asheghi, Mehdi ................................................... 319

B Bai, Zhaojun .......................................................... 74 Baik, DongHyun .................................................. 611 Balakrishnan, Venkataramanan R. ........................ 93 Banerjee, Ansuman .............................................. 198 Basu, Prasenjit ..................................................... 198 Becer, M. R. ........................................................ 160 Benini, L. ............................................................. 125 Bernstein, A. ........................................................ 910 Betz, Vaughn ....................................................... 838 Bjesse, Per ............................................................. 42 Boning, Duane ..................................................... 138 Borälv, Arne .......................................................... 42 Bozorgzadeh, Elaheh ........................................... 653 Brayton, Robert ........................................... 411, 541 Brooke, Martin .................................................... 641 Bryant, Randal E. ................................................ 437 Burton, M. ........................................................... 910

C Castello, R. .......................................................... 923 Chakrabarti, P. P. ................................................. 198 Chakrabarty, Krishnendu ..................................... 223 Chandra, Rajit ...................................................... 319 Chandra, Vikas .................................................... 275 Chang, Shih-Chieh .............................................. 537 Chang, Yao-Wen ................................................. 300 Chao, Mango C.-T. .............................................. 468 Chatterjee, Satrajit ............................................... 541

Chaturvedi, Shubhyant ......................................... 550 Chen, Charlie C.-P. ...................................... 489, 611 Chen, Deming ...................................................... 752 Chen, Ruiming ............................................. 155, 619 Chen, Tsung-Hao ................................................. 489 Cheng, Kwang-Ting ..................................... 468, 713 Cheng, Lei ............................................................ 292 Cheung, Newton ................................................... 183 Chiang, Charles ...................................................... 74 Chiprout, Eli ......................................................... 485 Chmelař, Erik ....................................................... 899 Choi, Kihwan ......................................................... 29 Chong, Philip ........................................................ 379 Chou, Pai H. ........................................................... 21 Choudhuri, Siddharth ........................................... 653 Chow, William ..................................................... 838 Chu, Chris ............................................................ 696 Clarke, Edmund ...................................................... 66 Cong, Jason .......................................... 306, 394, 752

D Dartu, Florentin .................................................... 254 Das, Sayantan ....................................................... 198 Dasgupta, Pallab ................................................... 198 Dave, Nirav .......................................................... 775 Davoodi, Azadeh .................................. 423, 473, 702 De Bernardinis, F. ................................................ 923 Demir, Alper ........................................................ 887 Drechsler, Rolf ..................................................... 204 Duan, Xiaochun .................................................... 683 Dubrova, Elena ..................................................... 748 Durairaj, Vijay ...................................................... 498

E Eles, Petru ............................................................ 362 Evmorfopoulos, N. E. ........................................... 479

F Fallah, Farzan ....................................................... 169 Feldmann, Peter ...................................................... 88 Fix, Limor ............................................................ 198 Freund, Roland W. ................................................. 80 Fung, Ryan ........................................................... 838

G Gambini, S. ........................................................... 923 Ganai, Malay K. ................................................... 510

Gao, Feng ............................................................ 527 Gavrilov, S. .......................................................... 160 Gayasen, Aman ................................................... 107 Ghanta, Praveen ................................................... 880 Ghenassia, F. ....................................................... 910 Ghiasi, Soheil ...................................................... 653 Ghoneima, Maged ............................................... 800 Givargis, Tony ..................................................... 190 Glebov, A. ........................................................... 160 Gopalakrishnan, Padmini ................................ 2, 855 Graeb, Helmut ..................................................... 847 Gupta, Aarti ......................................................... 510 Gupta, Smriti ....................................................... 210

H Habitz, Peter A. ................................................... 336 Hakim, Nagib ...................................................... 138 Hanna, Ziyad ......................................................... 58 Hashimoto, Masanori .......................................... 814 Hauan, Steinar ..................................................... 229 Hayes, Jerry D. .................................................... 336 Hayes, John P. ..................................................... 527 He, Lei ................................................................. 760 Heald, Raymond .................................................. 347 Heng, Fook-Luen ................................................. 739 Henkel, Jörg ......................................................... 183 Hoe, James C. ...................................................... 175 Hosangadi, Anup ................................................. 169 Hsiao, Michael S. ................................................ 502 Hsieh, Cheng-Tao ................................................ 537 Hu, Bo ................................................................. 558 Hu, Jiang ...................................................... 283, 706 Hu, Jingcao .......................................................... 354 Huang, Chao ........................................................ 783 Huang, Renqiu ..................................................... 595 Huang, Wei .......................................................... 327 Hurst, Aaron P. .................................................... 379

I Ienne, Paolo ................................................. 440, 791 Ignjatović, Aleksandar ......................................... 370 Irwin, M. J. ........................................... 107, 120, 916 Ismail, Yehea ........................................ 246, 254, 800 Ito, Noriyuki ........................................................ 893

J Jain, Jitesh ............................................................. 93 Janapsatya, Andhi ................................................ 370 Jariwala, Devang ................................................. 387 Jayakumar, Nikhil ........................................ 590, 626

Jha, Niraj K. ................................................. 668, 783 Jiang, Jie-Hong R. ................................................ 411

K Kahng, Andrew B. ................................................ 565 Kaiss, Daher ........................................................... 58 Kajihara, Seiji ....................................................... 633 Kalla, Priyank ....................................................... 498 Kandemir, M. ............................................... 107, 120 Kang, ByungTae .................................................. 916 Kanuma, Akira ..................................................... 893 Kapoor, Arjun ...................................................... 626 Karampatzakis, D. P. ............................................ 479 Karandikar, Shrirang K. ....................................... 419 Karnik, Tanay ....................................................... 489 Kasnavi, Alireza ................................................... 141 Kastner, Ryan ....................................................... 169 Keller, Igor ........................................................... 147 Kennings, Andrew ................................................ 573 Khandelwal, Vishal ....................... 423, 473, 533,702 Khasidashvili, Zurab .............................................. 58 Khatri, Sunil ................................................. 590, 626 Kim, Jintae ........................................................... 863 Kim, Young-Il ...................................................... 218 Kinoshita, Kozo .................................................... 633 Koenemann, Bernd ............................................... 733 Koh, Cheng-Kok ............................................. 93, 394 Kolcu, I. ................................................................ 120 Komatsu, Hiroaki ................................................. 893 Kozhaya, Joseph N. .............................................. 315 Kroening, Daniel .................................................... 66 Krogh, Bruce H. ................................................... 210 Kuehlmann, Andreas ...................................... 50, 379 Kundu, Sandip ...................................................... 468 Kyung, Chong-Min .............................................. 218

L Lach, John ............................................................ 327 Lai, Xiaolue .......................................................... 687 Lavin, Mark .......................................................... 739 Le, Jiayong ............................................................... 2 Lee, Jaeseo ........................................................... 863 Lee, Kangmin ....................................................... 448 Lee, Leonard ........................................................ 713 Lee, Se-Joong ....................................................... 448 Lee, Wonbok .......................................................... 29 Li, Bing ................................................................ 518 Li, Chen ................................................................ 394 Li, Fei ................................................................... 760 Li, Gang ................................................................ 241 Li, Peng ........................................................ 319, 677

Li, Xin ............................................................. 2, 855 Lillis, John ........................................................... 387 Lin, Chuan ........................................................... 452 Lin, Jian-Cheng ................................................... 537 Lin, Yan ............................................................... 760 Liu, Chunsheng ................................................... 648 Liu, Fang ............................................................. 641 Liu, Frank .............................................................. 88 Liu, Jinfeng ............................................................ 21 Lu, Zhijian ........................................................... 327

M Ma, James D. ....................................................... 460 Macii, E. .............................................................. 125 Madden, Patrick H. .............................................. 394 Mahapatra, Rabi .................................................. 428 Mahmoodi, Hamid ................................................. 10 Mak, T. M. ........................................................... 713 Makris, Yiorgos ................................................... 903 Marculescu, Radu ................................................ 354 Markov, Igor L. ................................................... 550 Maruyama, Daisuke ............................................. 893 Mayaram, Kartikeya ............................................ 683 Melhem, Rami ....................................................... 35 Mishchenko, Alan ................................................ 411 Mitra, Tulika ........................................................ 766 Miyoshi, Tokiharu ............................................... 633 Mochiyama, Takashi ........................................... 893 Mohan, Chunduri Rama ...................................... 198 Mohanram, Kartik ............................................... 100 Mong, Wai Sum .................................................. 131 Mossé, Daniel ........................................................ 35 Mukherjee, Tamal ................................................ 229 Mukhopadhyay, Saibal .......................................... 10

N Nácul, André C. ................................................... 190 Najm, Farid N. ............................................. 602, 660 Nassif, Sani R. ............................................. 138, 315 Nikhil, Rishiyur S. ............................................... 775 Northrop, Greg .................................................... 739

O Oh, C. .................................................................. 160 Omedes, Olivier ................................................... 261 Onodera, Hidetoshi .............................................. 814 Oppold, Jeffery H. ............................................... 336 Orailoglu, Alex ............................................ 721, 726 Ozdal, Muhammet Mustafa ......................... 822, 830 Ozev, Sule ........................................................... 641

P Pan, David Z. ........................................................ 402 Pan, Ju Hwa .......................................................... 766 Panda, R. .............................................................. 160 Papa, David A. ..................................................... 550 Parameswaran, Sri ........................................ 183, 370 Patel, K. ................................................................ 125 Pedram, Massoud ................................................... 29 Peng, Zebo ............................................................ 362 Pfeiffer, Anton J. .................................................. 229 Phillips, Joel R. .................................................... 872 Pileggi, Lawrence T. ................ 2, 275, 319, 677, 855 Poncino, M. .......................................................... 125 Potkonjak, Miodrag .............................................. 702 Prasad, Mukul R. .................................................. 502 Püschel, Markus ................................................... 175

Q Qian, Haifeng ....................................................... 315

R Raghunathan, Anand .................................... 668, 783 Rajamani, Sriram K. ............................................. 437 Ramdani, Mohamed ............................................. 261 Ran, Yajun ............................................................ 582 Rao, Ravishankar ................................................. 268 Rao, Wenjing ........................................................ 721 Ravi, Srivaths ............................................... 668, 783 Raychowdhury, Arijit ........................................... 237 Ren, Haoxing ........................................................ 402 Robert, Michel ...................................................... 261 Rosenband, Daniel L. ........................................... 775 Roy, Jarrod A. ...................................................... 550 Roy, Kaushik .................................................. 10, 237 Roychowdhury, Jaijeet ......................................... 687 Rutenbar, Rob A. .......................................... 210, 460

S Sadowska, Malgorzata Marek ...................... 558, 582 Safarpour, Sean .................................................... 204 Saluja, Kewal K. .......................................... 611, 633 Samaan, Samie B. ................................................ 343 Sapatnekar, Sachin S. ............................ 315,419, 706 Sarrafzadeh, Majid ............................................... 653 Schmit, Herman .................................................... 275 Schmitz, Marcus ................................................... 362 Seth, Vikram ........................................................ 283 Shahram, Mahmoud ............................................. 141 Shanbhag, Naresh R. ............................................ 111

Shi, Feng .............................................................. 903 Sinha, Debjit .......................................................... 14 Skaba, Marcelo ...................................................... 58 Skadron, Kevin .................................................... 327 Smith, Alexander ................................................. 204 Soloviev, R. ......................................................... 160 Soma, Ramakrishna ............................................... 29 Somenzi, Fabio .................................................... 518 Srinivasan, Suresh ............................................... 107 Srivastava, Ankur ......................... 423, 473, 533, 702 Srivastava, Ashish ............................................... 808 Stamoulis, G. I. .................................................... 479 Stan, Mircea ......................................................... 327 Stehr, Guido ......................................................... 847 Su, Fei .................................................................. 223 Su, George ........................................................... 721 Su, Yangfeng ......................................................... 74 Sugiyama, Yaroku ............................................... 893 Svelto, F. .............................................................. 923 Sylvester, Dennis ................................................. 808 Sze, C. N. ............................................................. 706

T Teslenko, Maxim ................................................. 748 Thiran, Patrick ..................................................... 440 Tsai, Jeng-Liang .......................................... 489, 611 Tseng, Ken ........................................................... 147

V Vandenberghe, Lieven ......................................... 863 Vannelli, Anthony ............................................... 573 Vemuri, Ranga ............................................. 595, 931 Veneris, Andreas ................................................. 204 Verghese, Nishath ................................................ 147 Verma, Ajay K. ................................................... 791 Vijaykrishnan, N. ......................................... 107, 916 Villarrubia, Paul G. .............................................. 402 Vincentelli, A. Sangiovanni ................................ 923 Vincis, F. ............................................................. 923 Vorwerk, Kristofer .............................................. 573 Vrudhula, Sarma .......................................... 268, 880

W Wang, Janet ......................................................... 880 Wang, Jian ............................................................. 74 Wang, Joddy W. .................................................. 141 Wang, Laung-Terng (L.-T.) ................................. 633 Wang, Li-C. ................................................. 468, 713 Wang, Ping .......................................................... 347 Wang, Qinke ........................................................ 565

Wei, Jie ................................................................. 306 Wen, Xiaoqing ..................................................... 633 White, Jacob ......................................................... 887 Wolfe, Glenn ........................................................ 931 Wong, Jennifer L. ................................................. 702 Wong, Martin D. F. .............................. 292, 822, 830 Wong, Weng-Fai .................................................. 766 Worm, Frédéric .................................................... 440 Wu, Bin ................................................................ 660

X Xie, Min ............................................................... 394 Xie, Y. .................................................................. 107 Xu, Anthony ......................................................... 275 Xu, Yang .............................................................. 855

Y Yamaguchi, Junji .................................................. 814 Yang, Chia Lin ..................................................... 300 Yang, Chih-Kong Ken .......................................... 863 Yoo, Hoi-Jun ........................................................ 448 Yuh, Ping-Hung ................................................... 300

Z Zejda, Jindrich ...................................................... 141 Zelinski, Adam C. ................................................ 175 Zeng, Xuan ............................................................. 74 Zhang, Liang ........................................................ 502 Zhang, Ming ......................................................... 111 Zhang, Yan ........................................................... 306 Zhao, Min ............................................................. 283 Zhong, Lin ............................................................ 668 Zhou, Dian .............................................................. 74 Zhou, Hai ........................................ 14, 155, 452, 619 Zhou, Quming ...................................................... 100 Zhu, Dakai .............................................................. 35 Zhu, Jianwen ................................................ 131, 660 Zhu, Zhenhai Z. .................................................... 887 Zolotov, V. ........................................................... 160 Zuchowski, Paul S. ............................................... 336