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Seminar March 2017IBM Norway @ Norefjell Ski & Spa
Technology ReviewPOWER Technology & RoadmapChristopher HalesExecutive IT SpecialistHPC, OpenPOWER & Emerging TechnologiesIBM POWER Systems DivisionIBM Technical Staff
US Patent: 8230434B2IBM Outstanding Technical AwardInvention Achievement AwardHigh Value Patent Application AwardIBM Redbooks Gold Author
Materials may not be reproduced in whole or in part without the prior written permission of IBM.
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Contents
Market & Technology Context
POWER8 – Pivotal Technology Platform
POWER9 Processor Family & Technology
Speculation: Processors, Emerging Memory, etc
Questions
5
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Today’s challenges demand innovation – data expansion!
“Moore’s Law” needs full system optimisation augmented by accelerators
Structured & Unstructured data; how do you turn in to value ?
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Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Component Density on Silicon SubstrateMoore’s Law
Gordon Moore
Two Field Effect Transistors in cross-section of POWER6 4.2GHz microprocessor chip
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Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Component Density on Silicon SubstrateMoore’s Law
The future of CMOS technology¹
the number of components . . [on a chip] . . will double each year• Gordon Moore 1965
Driver for transistor scaling is . . . Economics• The more components on a chip, the lower the cost per component• Important dynamic: the rate of increase of components is greater than the rate on
increase in cost per chip Moore pointed out 3 sources of density improvement:
• 50% - lithography resolution• 25% - larger chip sizes• 25% - innovation in component formation (transistors)
Lithography –pattern delineation on wafers• Limited by 0.5 wavelength of laser light-source²• Photo-resist polymer properties• Volume production processes
¹Source for all bulleted information: Dr. R. D. Isaac, “The future of CMOS technology”, IBM Journal of Research & Development, Vol 44 No. 3 May 2000 ²IBM have used proximity X-ray lithography for exploratory integrated circuits which has a wavelength of 1.1nm. Problems with lens and mirror accuracy.
Gordon Moore
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Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Component Density on Silicon SubstrateMoore’s Law
Increasing component density through scaling
Decreasing gate distance (source, drain)
Decreasing t to sample current
Opportunity to increase core’s frequency
10
Field Effect Transistor
Gate Source
Drain
α β
ct
)(
ncyCoreFreque
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Public Domain POWER Processor Roadmap: plan of record
POWER8 Architecture POWER9 Architecture
2014POWER8
12 cores
22nm
New Micro-Architecture
New ProcessTechnology
2016POWER8w/ NVLink
12 cores22nm
EnhancedMicro-
ArchitectureWith NVLink
2017P9 SO24 cores
14nm
New Micro-Architecture
Direct attachmemory
New ProcessTechnology
Optimized for Data-Centric Workloads
Integrated PCIe
CAPI Acceleration / I/O
Scale-Out Datacenter TCO Optimization
Scale-up performance Optimization
Acceleration Enhancements to CAPI and NVLINK
Modularity for OpenPOWER
TBDP9 SU
TBD cores
14nm
EnhancedMicro-
Architecture
BufferedMemory
POWER6 Architecture POWER7 Architecture
2007POWER6
2 cores
65nm
New Micro-Architecture
New ProcessTechnology
2008POWER6+
2 cores
65nm+
EnhancedMicro-
Architecture
EnhancedProcess
Technology
2010POWER7
8 cores
45nm
New Micro-Architecture
New ProcessTechnology
2012POWER7+
8 cores
32nm
EnhancedMicro-
Architecture
New ProcessTechnology
High Frequency
Enhanced RAS
Dynamic Energy Management
Large eDRAM L3 Cache
Optimized VSX
Enhanced Memory Subsystem
Focus on EnterpriseTechnology and Performance Driven
Focus on Scale-Out and EnterpriseCost and Acceleration Driven
2018 - 20P8/9 SO
10nm - 7nm
Existing Micro-
Architecture
FoundryTechnology
Partner ChipPOWER8/9
OpenPOWEREcosystem
DesignTargeting
Partner Markets & SystemsLeveraging Modulatrity
2020+
New Micro-Architecture
NewTechnology
POWER10
New Features and
Functions
Future
TBD
Price, performance, feature, and ecosystem innovation
12
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Contents
Market & Technology Context
POWER8 – Pivotal Technology Platform
POWER9 Processor Family & Technology
Speculation: Processors, Emerging Memory, etc
Questions
14
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Public Domain POWER Processor Roadmap: plan of record
POWER8 Architecture POWER9 Architecture
2014POWER8
12 cores
22nm
New Micro-Architecture
New ProcessTechnology
2016POWER8w/ NVLink
12 cores22nm
EnhancedMicro-
ArchitectureWith NVLink
2017P9 SO24 cores
14nm
New Micro-Architecture
Direct attachmemory
New ProcessTechnology
Optimized for Data-Centric Workloads
Integrated PCIe
CAPI Acceleration / I/O
Scale-Out Datacenter TCO Optimization
Scale-up performance Optimization
Acceleration Enhancements to CAPI and NVLINK
Modularity for OpenPOWER
TBDP9 SU
TBD cores
14nm
EnhancedMicro-
Architecture
BufferedMemory
POWER6 Architecture POWER7 Architecture
2007POWER6
2 cores
65nm
New Micro-Architecture
New ProcessTechnology
2008POWER6+
2 cores
65nm+
EnhancedMicro-
Architecture
EnhancedProcess
Technology
2010POWER7
8 cores
45nm
New Micro-Architecture
New ProcessTechnology
2012POWER7+
8 cores
32nm
EnhancedMicro-
Architecture
New ProcessTechnology
High Frequency
Enhanced RAS
Dynamic Energy Management
Large eDRAM L3 Cache
Optimized VSX
Enhanced Memory Subsystem
Focus on EnterpriseTechnology and Performance Driven
Focus on Scale-Out and EnterpriseCost and Acceleration Driven
2018 - 20P8/9 SO
10nm - 7nm
Existing Micro-
Architecture
FoundryTechnology
Partner ChipPOWER8/9
OpenPOWEREcosystem
DesignTargeting
Partner Markets & SystemsLeveraging Modulatrity
2020+
New Micro-Architecture
NewTechnology
POWER10
New Features and
Functions
Future
TBD
Price, performance, feature, and ecosystem innovation
15
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER8 provides for State-of the art UNIX and IBM iplatforms with industrial robustness
Highest quality virtualization (similar to System Z)• PowerVM Hypervisor – trusted component• Full VM isolation or WPAR approach• Guaranteed processor capacity for each VM• Grouping of VM within MSPP (capacity management/guarantee)• VIOS + LPM
Modern management tooling• PowerVC (based on OpenStack and open components)• PowerSC for security & compliance
State-of-the-art Operating Systems• AIX, IBM I, Popular Linux distros
Unmatched scalability and reliability• 2 socket to 16 socket in single SMP image with excellent scaling• Industry leading RAS
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Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER8 provides for State-of the art UNIX and IBM iplatforms with industrial robustness
Enabled cross-over market and easy access to open software
• Support BigEndian and LittleEndian data formats (VM basis)
Innovations to deliver astonishing memory bandwidth
• Memory buffer and DDR4 overprovisioning
I/O on-chip PCIe Gen3
• 1GB/s in each direction for each 1x Lane
• Supports 8x and 16x PCIe slots/adapters
• Propagates 16x to I/O drawer via fibre-optics for I/O fan-out
Acceleration of key workload elements
• In-core acceleration
• On-chip acceleration
• In system acceleration (CAPI)
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Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER8: Large compute/data capacity & key pivotal technology platform
Processor Chip• 675mm2 22nm SOI• 15 levels of metal
12 processor cores• SMT8, OoO, 8 IF/dispatch, 10 instr issue• 20 execution units
Integrated SMP Interconnect• Four 8B X-bus Single Ended• Three 2B A-bus Differential 6.4 GHz• Largest SMP: big!• Distributed SMP protocol using PCI physicals
Integrated Memory Controllers• 2 Memory Controllers• 8 DMI high speed ports at 9.6 Ghz (230 GB/s / P8)• 16MB memory cache / buffer chip (128MB / P8)
Integrated IO Subsystem• 2 x PCI Gen3 16x or 1 PCI Gen3 16x + 2 PCI gen3 8x
Caches• L2 - 512 KB SRAM / Core• L3 - 96 MB eDRAM shared• L4 - Up to 128 MB eDRAM (off-chip)
CAPI interface via PCIeG3• Acceleration for FPGA and other AFUs
19
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER8: Large compute/data capacity & key pivotal technology platform
Processor Chip• 675mm2 22nm SOI• 15 levels of metal
12 processor cores• SMT8, OoO, 8 IF/dispatch, 10 instr issue• 20 execution units
Integrated SMP Interconnect• Four 8B X-bus Single Ended• Three 2B A-bus Differential 6.4 GHz• Largest SMP: big!• Distributed SMP protocol using PCI physicals
Integrated Memory Controllers• 2 Memory Controllers• 8 DMI high speed ports at 9.6 Ghz (230 GB/s / P8)• 16MB memory cache / buffer chip (128MB / P8)
Integrated IO Subsystem• 2 x PCI Gen3 16x or 1 PCI Gen3 16x + 2 PCI gen3 8x
Caches• L2 - 512 KB SRAM / Core• L3 - 96 MB eDRAM shared• L4 - Up to 128 MB eDRAM (off-chip)
CAPI interface via PCIeG3• Acceleration for FPGA and other AFUs
20
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
VSUFXU
IFU
DFU
ISU
LSU
Core Micro-Architecture Speculative superscalar inner core organization
Multi-threaded core design• ST, SMT2, SMT4, SMT8
Aggressive branch prediction• Prediction for up to eight branches per cycle• Support for up to 20 predicted taken branches in flight
Out of order issue of up to 10 operations• Register renaming on GPRs, FPRs, VRFs, etc.
15 execution units• 2 x Two symmetric load/store units (LSU)• 2 x load only units (LU) • 2 x symmetric fixed-point units (FXU)• 4 x floating-point units (FPU)• 2 x VMX execution units• 1 x Crypto unit• 1 x decimal floating-point unit (DFU)• 1 x Branch execution unit (BR)• (1 x Condition Register Logical execution unit (CRL))
Large number of instructions in flight• Up to 128 instructions in instruction fetch buffer• Up to 224 instructions in the inner-core (after dispatch)• Fast, selective flush of incorrect speculative instructions and
results
22
Core Performance vs . POWER7~1.6x Thread~2x Max SMT
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER8 Memory Organization (Max config shown)
POWER8Processor
MemoryBuffer
DRAMChips
128 MB Memory
128 MB Memory
128 MB Memory
128 MB Memory
128 MB Memory
128 MB Memory
128 MB Memory
128 MB Memory
Up to 1 TB memorycapacity per fullyconfigured socket
23
Up to 8 high speed DMI ports(9.6 Gb/s) up to 230 GB/s sustained
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER8 CAPI (Coherent Accelerator Processor Interface)
26
POWER8
CAPP
Coherence Bus
POWER8
PCIe Gen 3Transport for encapsulated messages
CustomHardware
ApplicationPSL
FPGA or ASIC
The CAPI port is used to connect auxiliary specialized processors such as GPUs, ASICs and FPGAs. Units attached to CAPI can use the same memory address space as the CPU. At the 2013 ACM/IEEE Supercomputing Conference, IBM and Nvidiaannounced an engineering partnership to closely couple POWER8 with Nvidia GPUs in future systems.
Virtual Addressing• Accelerator works in same address space as cores• Pointers de-referenced same as the host application• Removes OS & device driver overhead
Hardware Managed Cache Coherence• Enables the accelerator to participate in “Locks” as a
normal thread Lowers Latency over IO communication model
Processor Service Layer (PSL)• Present robust, durable interfaces to applications• Offload complexity / content from CAPP
Customizable Hardware Application Accelerator • Specific system SW, middleware, or user application• Written to durable interface provided by PSL
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Industry leading innovation for accelerated workloads“Minksy” systems built on POWER8 with NVlink
Introducing NVlink 1.0
• High speed, low latency bus
• CPU GPU comms
• GPU GPU comms
• 40 GB/s in each direction (80 GB/s agg.) per GPU
• 2.5X bandwidth of PCIeG3 with lower latency
Introducing “Minsky”
• 230 GB/s memory bandwidth
• 4 x NVIDIA Tesla P100 GPUs on planar (SXM2)
• NVlink 160 GB/s in each direction (320 GB/s agg.)
• ~58 GB/s mem BW per GPU
27
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Industry leading innovation for accelerated workloads“Minksy” systems built on POWER8 with NVlink
P100GPU
Power8CPU
GPUMemory
System Memory
P100GPU
80 GB/s
GPUMemory
NVLink
115 GB/s
P100GPU
Power8CPU
GPUMemory
System Memory
P100GPU
80 GB/s
GPUMemory
NVLink
115 GB/s
28
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Contents
Market & Technology Context
POWER8 – Pivotal Technology Platform
POWER9 Processor Family & Technology
Speculation: Processors, Emerging Memory, etc
Questions
30
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Public Domain POWER Processor Roadmap: plan of record
POWER8 Architecture POWER9 Architecture
2014POWER8
12 cores
22nm
New Micro-Architecture
New ProcessTechnology
2016POWER8w/ NVLink
12 cores22nm
EnhancedMicro-
ArchitectureWith NVLink
2017P9 SO24 cores
14nm
New Micro-Architecture
Direct attachmemory
New ProcessTechnology
Optimized for Data-Centric Workloads
Integrated PCIe
CAPI Acceleration / I/O
Scale-Out Datacenter TCO Optimization
Scale-up performance Optimization
Acceleration Enhancements to CAPI and NVLINK
Modularity for OpenPOWER
TBDP9 SU
TBD cores
14nm
EnhancedMicro-
Architecture
BufferedMemory
POWER6 Architecture POWER7 Architecture
2007POWER6
2 cores
65nm
New Micro-Architecture
New ProcessTechnology
2008POWER6+
2 cores
65nm+
EnhancedMicro-
Architecture
EnhancedProcess
Technology
2010POWER7
8 cores
45nm
New Micro-Architecture
New ProcessTechnology
2012POWER7+
8 cores
32nm
EnhancedMicro-
Architecture
New ProcessTechnology
High Frequency
Enhanced RAS
Dynamic Energy Management
Large eDRAM L3 Cache
Optimized VSX
Enhanced Memory Subsystem
Focus on EnterpriseTechnology and Performance Driven
Focus on Scale-Out and EnterpriseCost and Acceleration Driven
2018 - 20P8/9 SO
10nm - 7nm
Existing Micro-
Architecture
FoundryTechnology
Partner ChipPOWER8/9
OpenPOWEREcosystem
DesignTargeting
Partner Markets & SystemsLeveraging Modulatrity
2020+
New Micro-Architecture
NewTechnology
POWER10
New Features and
Functions
Future
TBD
Price, performance, feature, and ecosystem innovation
31
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER9 Processor – Common Features
32
New Core Microarchitecture
• Stronger thread performance
• Efficient agile pipeline
• POWER ISA v3.0
Enhanced Cache Hierarchy
• 120MB NUCA L3 architecture
• 12 x 20-way associative regions
• Advanced replacement policies
• Fed by 7 TB/s on-chip bandwidth
Cloud + Virtualization Innovation
• Quality of service assists
• New interrupt architecture
• Workload optimized frequency
• Hardware enforced trusted execution
Leadership Hardware Acceleration Platform
• Enhanced on-chip acceleration
• Nvidia NVLink 2.0: High bandwidth, advanced new features
• CAPI 2.0: Coherent accelerator and storage attach (PCIe G4)
• OpenCAPI 3.0: Improved latency and bandwidth, open interface
State of the Art I/O Subsystem
• PCIe Gen4 – 48 lanes
High Bandwidth Signaling Technology
• 16 Gb/s interface
– Local SMP
• 25 Gb/s interface – 25G Link
– Accelerator, remote SMP
14nm finFET Semiconductor Process
• Improved device performance and reduced energy
• 17 layer metal stack and eDRAM
• 8.0 billion transistors
SM
P In
terc
on
nec
t &
O
ff-C
hip
Acc
eler
ato
r E
na
ble
me
nt
On-Chip Accel
Memory SignalingSMP/Accelerator Signaling
SMP/Accelerator Signaling Memory Signaling
PC
Ie S
ign
alin
g
SM
P S
ign
alin
g
Core
L2L3
Region
Core
Core
L2L3
Region
Core
Core
L2L3
Region
Core
Core
L2L3
Region
Core
PCIe
Core
L2
L3 Region
Core
Core
L2
L3 Region
Core
Core
L2
L3 Region
Core
Core
L2
L3 Region
Core
Core
L2
L3 Region
Core
Core
L2
L3 Region
Core
Core
L2
L3 Region
Core
Core
L2
L3 Region
Core
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Four targeted implementations
Scale-Out – 2 Socket Optimized
Robust 2 socket SMP systemDirect Memory Attach• Up to 8 DDR4 ports • Commodity packaging form factor
Scale-Up – Multi-Socket Optimized
Scalable System Topology / Capacity • Large multi-socketBuffered Memory Attach• 8 Buffered channels
SMT4 Core
24 SMT4 Cores / ChipLinux Ecosystem Optimized
SMT8 Core
12 SMT8 Cores / ChipPowerVM Ecosystem Continuity
Core Count / Size
SMP scalability / Memory subsystem
POWER9 Processor Family
33
“Nimbus” “Cumulus”
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
New POWER9 Cores: completely new microarchitecture of the POWER ISA core
Optimized for Stronger Thread Performance and Efficiency• Increased execution bandwidth efficiency for a range of workloads including commercial,
cognitive and analytics• Sophisticated instruction scheduling and branch prediction for unoptimized applications and
interpretive languages• Adaptive features for improved efficiency and performance especially in lower memory
bandwidth systems
34
Available with SMT4 or SMT8 Cores4 or 8 threaded core built from modular execution slices
POWER9 SMT8 Core• PowerVM Ecosystem Continuity• Strongest Thread• Optimized for Large Partitions
POWER9 SMT4 Core• Linux Ecosystem Focus• Core Count / Socket• Virtualization Granularity
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
128bSuper-slice
DW
LSU
64b VSU
64bSlice
POWER9 SMT8 Core
DW
LSU
64b VSU
DW
LSU
64b VSU
Modular Execution Slices
VSUFXU
IFU
DFU
ISU
LSU
POWER8 SMT8 Core
4 x 128b Super-slice
POWER9 Core Execution Slice Microarchitecture
Re-factored Core Provides Improved Efficiency & Workload Alignment
• Enhanced pipeline efficiency with modular execution and intelligent pipeline control
• Increased pipeline utilization with symmetric data-type engines: Fixed, Float, 128b, SIMD
• Shared compute resource optimizes data-type interchange
35
POWER9 SMT4 Core
2 x 128b Super-slice
LSU
IFU
ISU ISU
IFU
ExecSlice
LSU
ExecSlice
ExecSlice
ExecSlice
ExecSlice
ExecSlice
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
17 Layers of Metal
Big Caches for Massively Parallel Compute
and Heterogeneous InteractionExtreme Switching Bandwidth for the
Most Demanding Compute and Accelerated Workloads
eDRAM POWER9
10M
Processing Cores
10M 10M 10M 10M 10M 10M 10M 10M 10M
7 TB/s
10M 10M
L3 Cache: 120 MB Shared Capacity NUCA Cache• 10 MB Capacity + 512k L2 per SMT8 Core
• Enhanced Replacement with Reuse & Data-Type Awareness
12 x 20 way associativity
High-Throughput On-Chip Fabric• Over 7 TB/s On-chip Switch
• Move Data in/out at 256 GB/s per SMT8 Core
256 GB/s x 12
POWER9Nvidia GPUMemory
IBM &PartnerDevices
IBM &PartnerDevices
PCIeDevice
SM
P
NV
Lin
k 2
PC
Ie
Ne
w C
AP
I
DD
R
CA
PI
POWER9 – Data Capacity & Throughput
37
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER9 – Dual Memory SubsystemsDirect DDR4 or buffered memory leveraging DMI ports
8 Direct DDR4 Ports• Up to 120 GB/s of sustained
bandwidth• Low latency access• Commodity packaging form factor• Adaptive 64B / 128B reads
8 Buffered Channels• Up to 230GB/s of sustained bandwidth • Extreme capacity – up to 8TB / socket• Superior RAS with chip kill and lane
sparing• Compatible with POWER8 system
memory• Agnostic interface for alternate
memory innovations
38
Scale OutDirect Attach Memory
Scale UpBuffered Memory
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER9PowerAccel
On ChipAccel
25GLink
Nvidia GPUs
I/O
CAPI
NVLink
New CAPI
PCIeG4
CAPI 2.0
PCIe G4
ASIC / FPGA
Devices
ASIC / FPGA
Devices
PCIeDevices
NVLink 2.0
OpenCAPI
POWER9 – Premier Acceleration Platform
Extreme Processor / Accelerator Bandwidth and Reduced Latency
Coherent Memory for all Accelerators
Virtual Addressing Capability for all Accelerators
OpenPOWER Community Enablement• Robust Accelerated Compute Options
State of the Art I/O and Acceleration Attachment Signalling• PCIe Gen 4 x 48 lanes – 192 GB/s duplex bandwidth• 25G Link x 48 lanes – 300 GB/s duplex bandwidth
Robust Accelerated Compute Options with OPEN standards• On-Chip Acceleration – Gzip x1, 842 Compression x2, AES/SHA x2• CAPI 2.0 – 4x bandwidth of POWER8 (Gen3) using PCIe Gen4 on P9• NVLink 2.0 – Next generation of GPU/CPU bandwidth and integration• OpenCAPI – High BW, low latency & open interface using 25G Link
40
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Socket Performance
Scale-Out configuration @ constant frequency
POWER9 Performance
44
Note: simulated (therefore expected) performance results
IBM Confidential
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
POWER9 Processor
Enhanced Core and Chip Architecture• New Core Optimized for Commercial and Accelerated Workloads• Bandwidth, Scale, and Capacity, Ingest and Analyze
Processor Family with Scale-Out and Scale-Up Optimized Silicon• Enabling a Range of Platform Optimizations – from HSDC Clusters to Enterprise
Class Systems• Extreme Virtualization Capabilities for the Cloud
Premier Acceleration Platform• Heterogeneous Compute Options to Enable New Application Paradigms• State of the Art I/O• Engineered to be Open
High Bandwidth Memory and SMP interconnect for Enterprise Class
Built for the Cognitive Era45
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Contents
Market & Technology Context
POWER8 – Pivotal Technology Platform
POWER9 Processor Family & Technology
Speculation: Processors, Emerging Memory, etc
Questions
62
Norway POWER Seminar 20-22 March 2017© 2017 International Business Machines Corporation
Questions?
63