nmi presentation sept 2007

NMI Presentation Notes12th September 2007

IC Mask Design LimitedUnit 12G Maynooth Business CampusMaynooth, Co. Kildare, Ireland.

Topics:1. Analog Layout at 90 nanometer 2. RF Layout at 90 nanometer

Analog Layout at 90 nanometerThere are various challages in Analog layout at 90 nanometer.The topics for discussion are:

Shallow Trench Isolation Stress (STI) Well Proximity Effect (WPE)

RF Layout at 90 nanometerAs frequencies increase, with some CMOS circuits operating in the RF range, layout quality has a larger influence on circuit perfomance. The topics for discussion are:

Interconnect Interconnect Parasitics

Device Parasitics Understanding and optimising device parasitics

ICMaskDesign Adrian O'Shaughnessy

STI So what exactly is it?

STI is a technique to electrically isolate mos transistors from each other. LOCUS (local oxidation of silicon) was the technique used previous to this. Basically this involved growing a thick pad of oxide between adjacent devices. The problem with it really was scalability. As geometries were getting smaller it wasn't really an option, so Shallow Trench Isolation was introduced.

This involved etching out a shallow trench into the substrate between devices and then filling with an oxide.

So why is it so important that we understand it?

Basically if STI isn't taking into account it can lead to circuit failure. So the designer has to be aware of it and most importantly the layout engineer has to understand and know how to deal with it.

So what problems does it introduce?

The STI process stresses the mos transistors which can lead to a degradation or variation in performance. So this can affect things like matching. If your current mirror is experiencing a variation across it's transistors then they won't be matched and offsets could be introduced.

Worse still will be that the current output will be much less than expected so things like biasing currents could be affected.

So how does it stress the mos transistors?

First of all when the trench is etched into the substrate this will cause some mechanical stress. In other words the silicon itself will experience stress and the degree of stress that the transistor experiences is related to the distance of the gate to the closest STI region, that is the distance of the channel to the closest oxide.

So how can we as layout engineers fix it?

1. Well we could match it. If for example in a current mirror we ensure that each transistor experiences the same STI stress then they are matched. The problem with this though is the designer has to be aware that this is the technique that we are using because this technique could result in a degradation in current output and so the designer has to allow for this in their simulations.

2. Another technique is to share regions. Here we have utilised area and we have eliminated the STI stress. The important thing to note is we that must extend the poly to active distance on the outer mos transistors. We can do this by simply drawing in the extra diffusion area or by adding in dummy devices


WPE

The Well Proximity Effect is another effect that if not understood has the potential to cause circuit failure.

So what is it?

Basically this involves the scattering of ions (ion scattering) during the implantation of the wells.

So what does this cause?

The result is a well surface concentration that changes with lateral distance from the mask edge over the range of 1 micron or more.

This later non-uniformity in well doping causes the MOS threshold voltages and other electrical characteristics to vary with the distance of the transistor to the well edge.

In some instances Vt has been found to increase by as much as 50mV as the device moves closer to the edge.

If this isn't taken into account such things as current mirrors can be shifted out of saturation leading to circuit failure.

So how is it fixed?

The layout engineer must insure that the mos devices either experience the same WPE effect or must ensure that there is enough of a distance from the well edge so as to negate the effects of WPE. Characterisation tests reveal that 2-5 microns should be sufficient.


RF Layout at 90 NanometresINTRO Good layout practice at high frequencies is extremely important because bad layout can and will introduce parasitics that may result in extra current needed to drive these parasitic loads.

It could also of course stop your circuit from working at all as it may limit it's frequency response.

Interconnect

Lets look at the parasitics that's introduced by interconnect.

Every single piece of interconnect we put down will have an associated parasitic resistance. This resistance is calculated by multiplying it's sheet resistance by it's length over width – Rs * (L/W)

Interconnect will also introduce different types of parasitic capacitance such as parallel plate, Fringe and cross coupling which will all have a combinational affect and create one overall parasitic capacitance.

So have can we improve on the parasitic resistance?

1. Reduce Length. If we properly floorplan our blocks it should be possible to minimise the interconnect between them.

2. Increase Width. Increasing the width will reduce the number of squares. It is common for differential signals to be wider than the minimum width.

3. Use Higher Layers. Higher metals have a lower sheet resistance than lower ones therefore reducing its overall resistance. This will also have the added advantage of decreasing the capacitance to substrate.


Device Parasitics

INTRO

When we put down a device in layout we introduce parasitics. Simple as that. So what happens when we put down a mos device?

Simple MOS Parasitics

We introduce a whole host of resistive and capacitive parasitics and as a layout engineer there are some on these parasitics that can be optimised and there's some that can't.

Parasitics that we can't optimise are directly related to the length of the device which we can't change.

We can optimise the gate resistance by tying both ends of the poly in metal thereby connecting another resistor, in this case metal1, in parallel with in.

Connecting the gate in metal will improve the resistance by 200% - 400%.

We can improve the drain and source parasitic capacitance by folding the device. But which one do we optimise? This is particularly done on differential pairs. If we optimise the source area then we're optimising a region that is going to ground if it's an NMOS device. Any good?

If we optimise the drain area then we're optimising the output node which in RF circuits is highly sensitive to capacitance. So it's best to optimise this.

We can also improve the substrate resistance by putting in lots of well contacts. This will help prevent against latch-up and also serve as noise protection.


nmi presentation sept 2007

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