Jyuo-Min ShyuIndustrial Technology Research Institute (ITRI)

Aug. 15, 2006

Nanotechnology Opportunities from a System Application Perspective

ITRS Revisited

A reference document of technology requirements, potential solutions, and their timing for the industryRequired to sustain Moore’s Law— Cost reduction per function

Industry consensus on the whats and whens of needs

Moore’s Law: Competition

Technology development ahead of scheduleWidespread SoC realizations through steadily down-scaled device size, and improved device cost and performanceTechnology limits reached sooner than anticipated

Time

Prog

ress

Breakthrough needed

- ITRS (2001), Executive Summary

“Traditional scaling ... is indeed beginning to show the fundamental limits ... of the planar CMOS process.”

Touching the Red Brickwall

Emerging Research Devices

Architecture

Non-classical

CMOS

Memory

Logic

Time

Emerging Technology Sequence

StrainedSi

VerticalTransistor

FinFET Planardouble gate

Phase ChangeNano FG SET Molecular

Magnetic RAM

SETRSFQ QCA Molecular

RTD-FET

Quantumcomputing

CNNDefectTolerant

QCA

3DIntegration

FD SOI

Molecular

EmergingTechnology

Vectors

Technology from System Perspective

Logic devices— CMOS: faster, smaller, less power, more reliable, lower cost

Memory— Faster on-chip memory to catch up with CPU speed— New NVM for data storage and for running program code

➪ CMOS as the platform for technology development

Two Approaches

Top-down— Litho (optical, e-beam, X-ray) and etch— New materials (eg., hi-k and low-k) and molecular-precision process &

patterning to deal with standby power and process variations …— The future is simpler to extrapolate, but is approaching the end of the road at

around 22nm?— Shift to heterogeneous integration and multi-core architectures

Bottom-up— Deals with atoms and molecule assembly— Progress path not clear

Recent Nanometer Design Technology

0.13um – 90nm— Chips to 50M+ gates— Timing delays based on wire-to-wire coupling— Variable metal pitch— Key EDA technologies: signal integrity and power design

65nm and below— Chips with 100M+ gates— Timing delays based on subwavelength and inductive effects— Key EDA technologies: subwavelength-aware P&R, DFM/DFR

Optimizing the Interface: DFM

Source: Semiconductor International (Jul. 2006)

Dealing with Manufacturing Uncertainties

Uncertainties: physical dimensions, device parameters, electrical parameters, …Resolution Enhancement Techniques (RET)— Optical Proximity Correction (OPC) to allow subwavelength

features to be printed

Hot topics in EDA— Statistical Timing Analysis— Statistical (Leakage) Power Analysis

Strained Silicon for Higher Mobility

Si

SiGe

Strained Si

Gate

S Dstrained Si

relaxed SiGe

Si substrate

Memory Opportunities

Word Line Bit Line

ProgrammableTransistor Element

(C, R)

GND

Opportunities!

ga te

na no crys ta l

d ra insou rce

tu nne ld ie le c tric

ga te

na no crys ta l

d ra insou rce

tu nne ld ie le c tric

EcEfEv

Control GatePolySi n+

Floating GatePolySi n+ Si substrate

- - - -

Nanocrystal

-- --- -

Potential pocket

Dealing with Scaled NVM Device

Tunnelling Effect

Motorola: 4Mb (130nm, 2003); 24Mb (90nm, 2006) demo

Tunneling oxide

Blocking oxide: Al2O3

Gate

Source p-Si

TiN-nc

Drain

TEM image of TiN nanocrystals (TiN-nc) with TiN/Al2O3 layers

p-Si

SiO2~3.5nm TiN-nc

Al2O3

Nanocrystal NVM

Source: ITRI (May 2006)

ALD-formed nano-laminated trapping layer

Novel Functional Device: MRAM

OFF

Write Current He

Write Current Hh

Write Read

Fixed-layer

Bit-line

Bit-line

ON

Free-layer

Tunneling Oxide

Sensing Current

M1

M2

M3

M4

D S

G

Integration with CMOS

Source: ITRI (Aug. 2005)

Bank0256Kb

Bank1256Kb

Emerging Research Devices

Architecture

Non-classical

CMOS

Memory

Logic

Time

Emerging Technology Sequence

StrainedSi

VerticalTransistor

FinFET Planardouble gate

Phase ChangeNano FG SET Molecular

Magnetic RAM

SETRSFQ QCA Molecular

RTD-FET

Quantumcomputing

CNNDefectTolerant

QCA

3DIntegration

FD SOI

Molecular

EmergingTechnology

Vectors

Carbon-Nanotube Device

Source: IBM (2001)

Diameter: 1 – 2 nm

Ring Oscillator Built in a Single CNT

Source: Z. Chen at al, Science (Mar. 24, 2006)

5-stage ring oscillator (running at 52MHz): with 12 FETs side by side along the length of a 18um SWCNT (diameter: 2nm)Polarities of FETs are controlled by using metals with different work functions: Pd for p-FET and Al for n-FETProblems: CNT quality, alignment, integration with CMOS, …

Controlled CNT Growth?

Thermal CVD

Computing with Imperfect Devices: Nanocomputers?

Molecular Switch

Source: M. R. Stan et al, “Circuit Design for Hybrid CMOS/Molecular Electronics” (Sept. 2005)

Nanowire

Defect-tolerant computing?!

“NRAM” to Replace SRAM?

Source: Scientific American (Jan. 2006)

Conclusion

Nanoelectronic opportunities abundant from system application

perspective (with CMOS as the nanotech platform)

— Enhanced silicon CMOS logic devices

— Novel memory elements

There are still years ahead before we see a “bottom-up”

manufacturing tool for use on a large scale and high throughput with

nano-scale features