n-channel depletion-mode vertical dmos fet in single … sheets/microchip... · contact factory for...

7
Supertex inc. Supertex inc. www.supertex.com DN2625 Doc.# DSFP-DN2625 C060313 Features Very low gate threshold voltage Designed to be source-driven Low switching losses Low effective output capacitance Designed for inductive loads Well matched for low second harmonic when driven by Supertex MD2130 Applications Medical ultrasound beamforming Ultrasonic array focusing transmitter Piezoelectric transducer waveform drivers High speed arbitrary waveform generator Normally-on switches Solid state relays Constant current sources Power supply circuits General Description The Supertex DN2625 is a low threshold depletion-mode (normally- on) transistor utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. The DN2625DK6-G contains two MOSFETs in an 8-lead, dual pad DFN package. The DN2625K6-G in the 14-lead QFN package is not recommended for new designs, but may continue to be purchased for existing designs. Absolute Maximum Ratings Parameter Value Drain-to-source voltage 250V Drain-to-gate voltage 250V Gate-to-source voltage ±20V Operating and storage temperature -55 O C to +150 O C Soldering temperature* 300 O C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. GATE SOURCE DRAIN GATE SOURCE SOURCE SOURCE GATE SOURCE SOURCE SOURCE DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN 1 2 3 4 11 10 9 8 5 6 7 14 13 12 Pin Configuration TO-252 D-PAK 14-Lead QFN (top view) 8-Lead DFN (dual pad) (top view) 8 1 2 3 4 7 6 5 S1 G1 D1 S2 G2 D1 D2 D2 D1 D2 N-Channel Depletion-Mode Vertical DMOS FET in Single and Dual Options Product Summary BV DSX /BV DGX V GS(OFF) (max) I DS (pulsed) (V GS = 0.9V) (min) 250V -2.1V 3.3A -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. * This package obsolete. For single MOSFETs use the TO-252 D-PAK (K4), for dual MOSFETs use the 8-Lead DFN (K6) (dual pad). Ordering Information Part Number Package Option Packing DN2625K4-G TO-252 D-PAK 1000/Bag DN2625DK6-G 8-Lead DFN 490/Tray DN2625DK6-G M932 8-Lead DFN 2500/Reel DN2625K6-G* 14-Lead QFN 490/Tray Typical Thermal Resistance Package θ ja TO-252 D-PAK 1 81 O C/W 8-Lead DFN (dual pad) 2 29 O C/W 14-Lead QFN 2 23 O C/W 1. 4-layer, 1oz, 3x4inch PCB, with 20-via for drain pad. 2. 4-layer, 1oz, 3x4inch PCB, with 12-via for drain pad.

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Page 1: N-Channel Depletion-Mode Vertical DMOS FET in Single … Sheets/Microchip... · Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead ... Change in V GS(OFF)

Supertex inc.

Supertex inc. www.supertex.com

DN2625

Doc.# DSFP-DN2625 C060313

Features Very low gate threshold voltage Designed to be source-driven Low switching losses Low effective output capacitance Designed for inductive loads Well matched for low second harmonic when

driven by Supertex MD2130

Applications Medical ultrasound beamforming Ultrasonic array focusing transmitter Piezoelectric transducer waveform drivers High speed arbitrary waveform generator Normally-on switches Solid state relays Constant current sources Power supply circuits

General DescriptionThe Supertex DN2625 is a low threshold depletion-mode (normally-on) transistor utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

The DN2625DK6-G contains two MOSFETs in an 8-lead, dual pad DFN package. The DN2625K6-G in the 14-lead QFN package is not recommended for new designs, but may continue to be purchased for existing designs.

Absolute Maximum Ratings Parameter ValueDrain-to-source voltage 250V

Drain-to-gate voltage 250V

Gate-to-source voltage ±20V

Operating and storage temperature -55OC to +150OC

Soldering temperature* 300OCAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.

* Distance of 1.6mm from case for 10 seconds.

GATESOURCE

DRAIN

GATE

SOURCE

SOURCE

SOURCE

GATE SOURCE SOURCE SOURCE

DRAIN DRAIN DRAIN

DRAIN DRAIN DRAIN

1

2

3

4

11

10

9

8 5 6 7

14 13 12

Pin Configuration

TO-252 D-PAK

14-Lead QFN(top view)

8-Lead DFN (dual pad)(top view)

8 1

2

3

4

7

6

5

S1

G1

D1

S2

G2

D1

D2

D2

D1

D2

N-Channel Depletion-Mode Vertical DMOS FET in Single and Dual Options

Product SummaryBVDSX/BVDGX

VGS(OFF)(max)

IDS (pulsed)(VGS = 0.9V)

(min)

250V -2.1V 3.3A

-G denotes a lead (Pb)-free / RoHS compliant package.Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.* This package obsolete. For single MOSFETs use the TO-252 D-PAK (K4), for dual MOSFETs use the 8-Lead DFN (K6) (dual pad).

Ordering InformationPart Number Package Option Packing

DN2625K4-G TO-252 D-PAK 1000/BagDN2625DK6-G 8-Lead DFN 490/TrayDN2625DK6-G M932 8-Lead DFN 2500/ReelDN2625K6-G* 14-Lead QFN 490/Tray

Typical Thermal Resistance

Package θja

TO-252 D-PAK1 81OC/W8-Lead DFN (dual pad)2 29OC/W14-Lead QFN2 23OC/W1. 4-layer, 1oz, 3x4inch PCB, with 20-via for drain pad.2. 4-layer, 1oz, 3x4inch PCB, with 12-via for drain pad.

Page 2: N-Channel Depletion-Mode Vertical DMOS FET in Single … Sheets/Microchip... · Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead ... Change in V GS(OFF)

2Supertex inc.

www.supertex.comDoc.# DSFP-DN2625 C060313

DN2625

Electrical Characteristics (TA = 25OC unless otherwise specified)

Sym Parameter Min Typ Max Units ConditionsBVDSX Drain-to-source breakdown voltage 250 - - V VGS = -2.5V, ID = 50µABVDGX Drain-to-gate breakdown voltage 250 - - V VGS = -2.5V, ID = 50µAVGS(OFF) Gate-to-source off voltage -1.5 - -2.1 V VDS = 15V, ID = 100µA

ΔVGS(OFF) Change in VGS(OFF) with temperature - - -4.5 mV/OC VDS = 15V, ID = 100µAIGSS Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V

ID(OFF) Drain-to-source leakage current- - 1.0

µAVDS = 250V, VGS = -5.0V

- - 200 VDS = 250V, VGS = -5.0V, TA = 125OC

IDSS Saturated drain-to-source current 1.1 - - A VGS = 0V, VDS = 15V

IDS(PULSE) Pulsed drain-to-source current 3.1 3.3 - A VGS = 0.9V, VDS = 15V (with duty cycle of 1%)

RDS(ON) Static drain-to-source on-resistance - - 3.5 Ω VGS = 0V, ID = 1.0AΔRDS(ON) Change in RDS(ON) with temperature - - 1.1 %/OC VGS = 0V, ID = 200mA

GFS Forward transconductance 100 - - mmho VDS = 10V, ID = 150mACISS Input capacitance - 800 1000

pFVGS = -2.5V,VDS = 25V,f = 1.0MHz

COSS Common source output capacitance - 70 210CRSS Reverse transfer capacitance - 18 70td(ON) Turn-on delay time - - 10

ns

VDD = 25V,ID = 150mA,RGEN = 3.0Ω,VGS = 0v to -10V

tr Rise time - - 20td(OFF) Turn-off delay time - - 10

tf Fall time - - 20VSD Diode forward voltage drop - - 1.8 V VGS = -2.5V, ISD = 150mAQG Total gate charge - - 7.04

nCID = 3.5A,VDS = 100V,VGS = 1.5V

QGS Gate-to-source charge - - 0.783QGD Gate-to-drain charge - - 3.73

Thermal CharacteristicsPackage ID

(continuous)1ID

(pulsed)IDR

1 IDRM

TO-252 D-PAK 1.1A 3.3A 1.1A 3.3A8-Lead DFN (dual pad) 1.1A 3.3A 1.1A 3.3A14-Lead QFN 1.1A 3.3A 1.1A 3.3ANotes:

1. ID (Continuous) is limited by max. Tj.

Product Marking

YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging

Si YYWW DN2625

LLLLLLL

TO-252 D-PAK 8-Lead DFN (dual pad) 14-Lead QFNThis package is not recommended

for new designs.

D2625D LLLLLL YYWW AAACCC

L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging

DN2625 LLLLLL YYWW AAACCC

L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging

Packages may or may not include the following marks: Si or

OBSOLETE

Page 3: N-Channel Depletion-Mode Vertical DMOS FET in Single … Sheets/Microchip... · Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead ... Change in V GS(OFF)

3Supertex inc.

www.supertex.comDoc.# DSFP-DN2625 C060313

DN2625

Typical Performance CurvesOutput Characteristics

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0 50 100 150 200 250VDS (volts)

I D (a

mps

)

VGS = 2.0VVGS = 1.5VVGS = 1.0VVGS = 0.5VVGS = 0VVGS = -0.5VVGS = -1.0VVGS = -1.5VVGS = -2.0V

90%

10%

90% 90%

10%10%

PulseGenerator

VDD

RL

OUTPUT

D.U.T.

t(ON)

td(ON)

t(OFF)

td(OFF)tr

INPUT

INPUT

OUTPUT

0V

VDD

RGEN

0V

-10V

tf

Switching Waveforms and Test Circuit

Saturation Characteristics

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 1 2 3 4 5 6 7 8 9 10VDS (V)

I D (A

)

VGS = -2VVGS = -1.5VVGS = -1VVGS = -0.5VVGS = 0VVGS = 0.5VVGS = 1VVGS = 1.5VVGS = 2V

Transfer Characteristics BVDSX Variation With Temperature

0

1

2

3

4

5

6

7

8

9

10

-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0

VGS (V)

I D (a

mps

)

-55OC

25OC

125OC

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

-50 -25 0 25 50 75 100 125 150

Tj (OC)

BV

DS

X (n

orm

aliz

ed)

VGS = -2.5VID = 1mA

Page 4: N-Channel Depletion-Mode Vertical DMOS FET in Single … Sheets/Microchip... · Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead ... Change in V GS(OFF)

4Supertex inc.

www.supertex.comDoc.# DSFP-DN2625 C060313

DN2625Typical Performance Curves (cont.)

On-Resistance vs Drain Current

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

ID (A)

RD

S(O

N) (

ohm

s)

VGS = 1V

Transconductance vs Drain Current

VGS(OFF) and RDS(ON) Variation With Temperature

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

ID (A)

GFS

(Sie

men

s)

-55OC

25OC

125OC

VDS = 10V

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

-50 -25 0 25 50 75 100 125 150

Tj (OC)

VG

S(O

FF) (

norm

aliz

ed)

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

VGS(OFF) @100µAVDS = 15V

RDS(ON) @VGS = 1VID =1A R

DS

(ON

) (no

rmal

ized

)

Page 5: N-Channel Depletion-Mode Vertical DMOS FET in Single … Sheets/Microchip... · Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead ... Change in V GS(OFF)

5Supertex inc.

www.supertex.comDoc.# DSFP-DN2625 C060313

DN26253-Lead TO-252 D-PAK Package Outline (K4)

Note:1. Although 4 terminal locations are shown, only 3 are functional. Lead number 2 was removed.

1 2 3

4

L4 L5

b b2 e

D1

E1

L1L

SeatingPlane

A1GaugePlane

θ

D

E

View B

Front View Side ViewRear View

View B

θ1

H

c2A

L3

L2

b3

Note 1

Symbol A A1 b b2 b3 c2 D D1 E E1 e H L L1 L2 L3 L4 L5 θ θ1

Dimen-sion

(inches)

MIN .086 .000* .025 .030 .195 .018 .235 .205 .250 .170.090BSC

.370 .055.108REF

.020BSC

.035 .025* .045 0O 0O

NOM - - - - - - .240 - - - - .060 - - - - -

MAX .094 .005 .035 .045 .215 .035 .245 .217* .265 .182* .410 .070 .050 .040 .060 10O 15O

JEDEC Registration TO-252, Variation AA, Issue E, June 2004.* This dimension is not specified in the JEDEC drawing.Drawings not to scale.Supertex Doc. #: DSPD-3TO252K4, Version E041309.

Page 6: N-Channel Depletion-Mode Vertical DMOS FET in Single … Sheets/Microchip... · Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead ... Change in V GS(OFF)

6Supertex inc.

www.supertex.comDoc.# DSFP-DN2625 C060313

DN26258-Lead DFN Package Outline (K6)5.00x5.00mm body, 0.90mm height (max), 1.27mm pitch (dual pad)

Symbol A A1 A3 b D D2 E E2 e K1 L L1 θ

Dimension(mm)

MIN 0.80 0.000.20REF

0.35 4.90 1.93 4.90 1.901.27BSC

0.40REF

0.40 0.00 0O

NOM 0.85 - 0.40 5.00 2.03 5.00 2.00 0.50 - -

MAX 0.90 0.05 0.45 5.10 2.13 5.10 2.10 0.60 0.15 14O

Drawings not to scaleSupertex Doc. #: DSPD-8DFNK65x5P127, Version A040209

Bottom View

E2

View B

Note 1(Index AreaD/2 x E/2)

1

8

Note 1

E2

D2

K1K1/2

SeatingPlane

Top View

Side View

A

A1

D

E

eb

A3 L

L1

View B

Note 1(Index AreaD/2 x E/2)

Note 3

Note 2

1

8

θ

D2

Notes:1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or

a printed indicator.2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.3. The inner tip of the lead may be either rounded or square.

Page 7: N-Channel Depletion-Mode Vertical DMOS FET in Single … Sheets/Microchip... · Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead ... Change in V GS(OFF)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receivesan adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilityto the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry andspecifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888www.supertex.com7

DN2625

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-DN2625 C060313

14-Lead QFN Package Outline (K6)5.00x5.00mm body, 1.00mm height (max), 1.27mm pitch

Symbol A A1 A3 b D D2 E E2 e AA BB CC DD θ

Dimension(mm)

MIN 0.80 0.000.20REF

0.46 4.85 4.45 4.85 2.521.27BSC

0.152 0.473 0.66 0.456 0O

NOM 0.90 0.02 0.51 5.00 4.50 5.00 2.57 0.252 0.523 0.71 0.506 -MAX 1.00 0.05 0.58 5.15 4.55 5.15 2.62 0.352 0.583 0.77 0.566 14O

Drawings not to scale.Supertex Doc. #: DSPD-14QFNK65X5P127, Version B090808.

Notes:1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or

a printed indicator.

SeatingPlane

Top View

Side View

Bottom View

E

D

E2Pin 1

e DDCCAA

ExposedPad

14

1

14

BB

D2

Note 1(Index AreaD/2 x E/2) Note 1

(Index AreaD/2 x E/2)

e

b

A

A1

A3

θ