MVSIS

MVSIS Group Minxi Gao,, Jie-Hong Jiang, Yunjian Jiang, Yinghua Li, Subarna Sinha and Robert K. Brayton

Dept. of Electrical Engineering and Computer Science University of California, Berkeley

Outline

Motivation: From binary to multi-valueDesign specificationMVSIS optimizations Node simplification Kernel and cube extraction Pairing and encoding Network manipulation

DemoConclusions

History

Multi-valued logic

E. L. Post, “Introdution to a general theory of elementary propositions”,Amer. J. Math., Jun 1921

J. C. Muzio and D. M. Miller, “On the minimization of many-valued functions”,Proc. 9th Int. Symp. Multiple-valued Logic, 1979

S. L. Hurst, “Multiple-valued logic – its status and its future”,IEEE Trans. On Computers, Jun 1984

J. C. Muzio and T. C. Wesselkamper, “Multiple-valued switching theory”Bristol: Hilger, 1986

R. K. Brayton and S. P. Khatri, “Multi-valued logic synthesis”,Proc. 12th Int. Conf. On VLSI Design, Jan 1999

Incomplete references

Motivations

Synchronous hardware synthesisSoftware synthesis from synchronous specificationsAsynchronous hardware synthesisMulti-valued devices?

Current-mode CMOS devices Optical logic circuits

Motivation – synchronous hardware

Design and synthesis from multi-valued logic Natural method of specification Larger design space

MVSIS

Verilog-MV

BLIF-MV

MV-OptimizeOpt-Encode

SIS

Encode

Two-level MV-PLA synthesisR.Rudell, et al “Espresso-MV”, 1987

Multi-level FSM synthesis (single MV)L.Lavagno, et al “MIS-MV”, 1990

FSM state encodingT.Villa, et al, “Nova”, 1990E.Goldberg, et al, “Minsk”, 1999

vl2mv

Motivation – software synthesis

Synchronous programming of embedded systems

Esterel/Lustre/Signal Interactive FSM semantics Code generation from logic FSM’s

C/Assembly

POLISVCC

POLISF.Balerin, et al, “Synthesis of software programsfor embedded control applications”, TCAD 1999

ESTERELG.Berry, “The foundations of Esterel”, 2000

MVSISY.Jiang, et al, “Logic optimization and code generationfor embedded control applications”, CODES 2000

MVSIS

MV-OptimizeCode Gen

Current source

Linear sum

PMOS current mirror

Threshold detector

Motivation – multi-valued devices

Multi-valued current-mode MOS signed digit arithmetic High-speed, Low supply voltage

T. Hanyu and M. Kameyama, “A 200 MHz pipelined multiplier using 1.5 V-supplymultiple-valued MOS current-mode circuits with dual-rail source-coupled logic”,IEEE Journal of Solid-Statee Circuits, 1995

Building blocks

x

yx+yvm

m

x y1 y2

Ix

IT

Iy

Functional SemanticsNetwork of MV-nodesEach variable xn has its own range{0, 1,…, |Pn|-1}

Values are treated uniformlyMV-literal: X{0,2}

MV-cube: X{0,2}Z{0,1}

MV-function

F

0-set: F{0} = u{0} v{0} + u{0} v{1} w{0,1}

F(u,v,w): {0,1} x {0,1,2} x {0,1,2} {0,1,2}

2-set: F{2} = u{1} v{1,2} + u{1} v{0} w{1,2}

1-set: F{1} = <default>

Each output value is called an i-set

Latch

Design Specification

BLIF-MV subset Deterministic (no pseudo inputs) Single output MV nodes Flat network, no hierarchy Constant initial states (.reset)

Extension External don’t care networks (.exdc)

.model simple

.inputs a b

.outputs f

.mv f 3

.mv x 3

.table x a b -> f

.def 00 1 1 11 0 - 11 1 1 20 - 0 2

.reset x0.latch f x

.exdc

.inputs a b

.outputs f

.table a b -> f

.def 00 0 1.end

MVSIS Optimization

MVSIS optimizations Node simplification Kernel and cube extraction Pairing Encoding Network manipulations

Node Simplification

Two-level: Espresso-MV

Multi-level

Minimize each i-set independentlyDon’t care: input minterm that produces all output valuesPartial care: input minterm that produces a subset of output values

Compatible observability don’t cares(CODC)Satisfiability don’t cares (SDC)External don’t cares (XDC)

Q1Q2...Qr

imageimage

i

DDii

DCDC

ii

care setcare set

P1P2...Pn

mvsis> simplifymvsis> fullsimpmvsis> reset_default

100 11 011 101 0101 10 111 011 0110 10 110 110 0

100 11 111 101 1111 01 100 111 1100 11 110 110 1

<default> 2

a b c d z

101 01 100 001 -010 01 001 101 -

Algebraic Decomposition

Kernel extraction

Semi-algebraic divisionResubstitutionFactoring/Decomposition

[-q]: Two-cube divisors[-g]: Best divisors

mvsis> fx [-q] [-g]mvsis> decompmvsis> factormvsis> resub

F = a{0,1,2} b{0,1,2,3}c{3} + b{1,2,3} c{3}

+ a{0}b{1,2,3} c{0} +a{0} b{0,1,2,3}c{1}

= (c{3} +a{0}c{0,1})(a{0,1,2} c{1,3} +b{1,2,3} c{0,3})

M. Gao and R. K. Brayton, “Multi-valued Multi-level Network Decomposition”, IWLS, June 2001.

Pairing and Encoding

Pair_decode/Merge

Encode Merge some i-sets

Bit-pairing to create multi-valued nodeExplore different encodings

mvsis> pair_decodemvsis> merge mvsis> encodemvsis> elim_part

100 11 011 101 0101 10 111 011 0110 10 110 110 0

<default> 1

a b c d x 100 11 011 101

0101 10 111 011 0<default> 1

a b c d y

SOP further simplifiedOutput literal count reduced

100 11 011 101 0101 10 111 011 0100 11 111 101 1111 01 100 111 1110 10 110 110 1

<empty> 2

a b c d z

<default> 3

x0y0

x0y1

x1y0

x1y1

z0

z1

z2

z3

merge

Other Commands

Network manipulations

IO interface

Verification

mvsis> eliminatemvsis> collapseMvsis> sweep

mvsis> read_blifmvmvsis> read_blifmvsis> write_blifmv

mvsis> validate –m [mdd|simu]mvsis> gen_vecmvsis> simulatemvsis> qcheck

Printing

Sequential

mvsis> print_statsmvsis> print_factormvsis> print_rangemvsis> print_iomvsis> print_valuemvsis> print_part_value

mvsis> extract_seq_dc

Design Flow

Typical design flowmvsis> source mvsis.scriptmvsis> encode -imvsis> source mvsis.scriptb

Example #1

Matrix multiplication (3 values)#2 X 2 matrix mult over the ring Z_3.model matmul.inputs a11 a12 a21 a22 .inputs b11 b12 b21 b22 .outputs c11 c12 c21 c22 .mv a11, a12, a21, a22 3.mv b11, b12, b21, b22 3.mv c11, c12, c21, c22 3

.table a11 a12 b11 b21 c110 0 - - 00 1 - - =b210 2 - 0 00 2 - 1 20 2 - 2 11 0 - - =b111 1 0 0 01 1 0 1 11 1 0 2 21 1 1 0 1… ….table a11 a12 b12 b22 c120 0 - - 00 1 - - =b220 2 - 0 00 2 - 1 20 2 - 2 1

1 0 - - =b121 1 0 0 01 1 0 1 11 1 0 2 2… ….table a21 a22 b11 b21 c210 0 - - 00 1 - - =b210 2 - 0 00 2 - 1 20 2 - 2 11 0 - - =b111 1 0 0 01 1 0 1 11 1 0 2 21 1 1 0 11 1 1 1 21 1 1 2 01 1 2 0 21 1 2 1 01 1 2 2 11 2 0 0 01 2 0 1 21 2 0 2 11 2 1 0 11 2 1 1 0… …

.table a21 a22 b12 b22 c220 0 - - 00 1 - - =b220 2 - 0 00 2 - 1 20 2 - 2 11 0 - - =b121 1 0 0 01 1 0 1 11 1 0 2 21 1 1 0 1… ….end

[cadntws11:/home/wjiang/mvsis/examples/bob] mvsis[cadntws11:/home/wjiang/mvsis/examples/bob] mvsisUC Berkeley, MVSIS 0.95 (compiled 24-May-01 at 2:19 PM)UC Berkeley, MVSIS 0.95 (compiled 24-May-01 at 2:19 PM)mvsis> helpmvsis> helpalias chng_name collapse alias chng_name collapse decomp delete echo decomp delete echo elim_part eliminate encode elim_part eliminate encode extract_seq_dc factor fullsimp extract_seq_dc factor fullsimp fx gen_vec help fx gen_vec help history merge pair_decode history merge pair_decode print print_altname print_factor print print_altname print_factor print_io print_level print_part_value print_io print_level print_part_value print_range print_stats print_value print_range print_stats print_value qcheck quit read_blif qcheck quit read_blif read_blifmv reset_default reset_name read_blifmv reset_default reset_name resub runtime set resub runtime set simplify simulate source simplify simulate source sweep unalias undo sweep unalias undo unset usage validate unset usage validate write_blifmv write_blifmv mvsis> mvsis> mvsis> read_blifmv matmul-cmvsis> read_blifmv matmul-cmvsis> mvsis>

mvsis> chng_namemvsis> chng_namechanging to short-name modechanging to short-name modemvsis> print_statsmvsis> print_statsmatmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop)matmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop)mvsis> mvsis>

mvsis> set autoexec pfsmvsis> set autoexec pfsmatmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop), 216 lits(fact.)matmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop), 216 lits(fact.)mvsis> mvsis> mvsis> print_rangemvsis> print_range{i}:{i}: 33{j}:{j}: 33{k}:{k}: 33{l}:{l}: 33a:a: 33b:b: 33c:c: 33d:d: 33e:e: 33f:f: 33g:g: 33h:h: 33matmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop), 216 lits(fact.)matmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop), 216 lits(fact.)mvsis> mvsis>

mvsis> print_iomvsis> print_ioprimary inputs: a b c d e f g hprimary inputs: a b c d e f g hprimary outputs: {i} {j} {k} {l}primary outputs: {i} {j} {k} {l}mvsis> mvsis>

mvsis> simplifymvsis> simplifymatmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact.)matmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact.)mvsis> mvsis> mvsis> reset_defaultmvsis> reset_defaultmatmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact.)matmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact.)mvsis> mvsis>

mvsis> fullsimpmvsis> fullsimpmatmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact.)matmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact.)mvsis> mvsis> mvsis> pair_decode 1mvsis> pair_decode 1m{0} = a{0}e{2} + e{0}m{0} = a{0}e{2} + e{0}m{1} = a{0}e{1}m{1} = a{0}e{1}m{3} = a{1}e{2} + a{2}e{1}m{3} = a{1}e{2} + a{2}e{1}n{0} = a{0}f{2} + f{0}n{0} = a{0}f{2} + f{0}n{1} = a{0}f{1}n{1} = a{0}f{1}n{3} = a{1}f{2} + a{2}f{1}n{3} = a{1}f{2} + a{2}f{1}o{0} = e{0}c{2} + c{0}o{0} = e{0}c{2} + c{0}o{1} = e{0}c{1}o{1} = e{0}c{1}o{3} = e{1}c{2} + e{2}c{1}o{3} = e{1}c{2} + e{2}c{1}p{0} = f{0}c{2} + c{0}p{0} = f{0}c{2} + c{0}p{1} = f{0}c{1}p{1} = f{0}c{1}p{3} = f{1}c{2} + f{2}c{1}p{3} = f{1}c{2} + f{2}c{1}q{0} = b{0}g{2} + g{0}q{0} = b{0}g{2} + g{0}q{1} = b{0}g{1}q{1} = b{0}g{1}q{3} = b{1}g{2} + b{2}g{1}q{3} = b{1}g{2} + b{2}g{1}r{0} = b{0}h{2} + h{0}r{0} = b{0}h{2} + h{0}r{1} = b{0}h{1}r{1} = b{0}h{1}r{3} = b{1}h{2} + b{2}h{1}r{3} = b{1}h{2} + b{2}h{1}s{0} = g{0}d{2} + d{0}s{0} = g{0}d{2} + d{0}s{1} = g{0}d{1}s{1} = g{0}d{1}s{3} = g{1}d{2} + g{2}d{1}s{3} = g{1}d{2} + g{2}d{1}t{0} = h{0}d{2} + d{0}t{0} = h{0}d{2} + d{0}t{1} = h{0}d{1}t{1} = h{0}d{1}t{3} = h{1}d{2} + h{2}d{1}t{3} = h{1}d{2} + h{2}d{1}matmul: 12 nodes, 4 POs, 64 cubes(sop), 184 lits(sop), 160 lits(fact.)matmul: 12 nodes, 4 POs, 64 cubes(sop), 184 lits(sop), 160 lits(fact.)mvsis> mvsis>

mvsis> simplifymvsis> simplifymatmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)mvsis> mvsis>

mvsis> reset_defaultmvsis> reset_defaultmatmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)mvsis> mvsis>

mvsis> fullsimpmvsis> fullsimpmatmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)mvsis> mvsis>

mvsis> print_factormvsis> print_factor{i}{1} = m{2}q{2} + m{1}q{0} + m{0}q{1}{i}{1} = m{2}q{2} + m{1}q{0} + m{0}q{1}{i}{2} = m{2}q{0} + m{1}q{1} + m{0}q{2}{i}{2} = m{2}q{0} + m{1}q{1} + m{0}q{2}{j}{1} = n{2}r{2} + n{1}r{0} + n{0}r{1}{j}{1} = n{2}r{2} + n{1}r{0} + n{0}r{1}{j}{2} = n{2}r{0} + n{1}r{1} + n{0}r{2}{j}{2} = n{2}r{0} + n{1}r{1} + n{0}r{2}{k}{1} = o{2}s{2} + o{1}s{0} + o{0}s{1}{k}{1} = o{2}s{2} + o{1}s{0} + o{0}s{1}{k}{2} = o{2}s{0} + o{1}s{1} + o{0}s{2}{k}{2} = o{2}s{0} + o{1}s{1} + o{0}s{2}{l}{1} = p{2}t{2} + p{1}t{0} + p{0}t{1}{l}{1} = p{2}t{2} + p{1}t{0} + p{0}t{1}{l}{2} = p{2}t{0} + p{1}t{1} + p{0}t{2}{l}{2} = p{2}t{0} + p{1}t{1} + p{0}t{2}m{0} = a{0} + e{0}m{0} = a{0} + e{0}m{2} = a{2}e{1} + a{1}e{2}m{2} = a{2}e{1} + a{1}e{2}n{0} = a{0} + f{0}n{0} = a{0} + f{0}n{2} = a{2}f{1} + a{1}f{2}n{2} = a{2}f{1} + a{1}f{2}o{0} = c{0} + e{0}o{0} = c{0} + e{0}o{2} = c{2}e{1} + c{1}e{2}o{2} = c{2}e{1} + c{1}e{2}p{0} = c{0} + f{0}p{0} = c{0} + f{0}p{2} = c{2}f{1} + c{1}f{2}p{2} = c{2}f{1} + c{1}f{2}q{0} = b{0} + g{0}q{0} = b{0} + g{0}q{2} = b{2}g{1} + b{1}g{2}q{2} = b{2}g{1} + b{1}g{2}r{0} = b{0} + h{0}r{0} = b{0} + h{0}r{2} = b{2}h{1} + b{1}h{2}r{2} = b{2}h{1} + b{1}h{2}s{0} = d{0} + g{0}s{0} = d{0} + g{0}s{2} = d{2}g{1} + d{1}g{2}s{2} = d{2}g{1} + d{1}g{2}t{0} = d{0} + h{0}t{0} = d{0} + h{0}t{2} = d{2}h{1} + d{1}h{2}t{2} = d{2}h{1} + d{1}h{2}matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)mvsis> mvsis>

mvsis> validate -m mdd matmul-cmvsis> validate -m mdd matmul-cNetworks are combinationally equivalent according to MDD method.Networks are combinationally equivalent according to MDD method.matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(sop), 96 lits(fact.)mvsis> mvsis>

[cadntws11:/home/wjiang/mvsis/examples/bob] mvsis[cadntws11:/home/wjiang/mvsis/examples/bob] mvsisUC Berkeley, MVSIS 0.95 (compiled 24-May-01 at 2:19 PM)UC Berkeley, MVSIS 0.95 (compiled 24-May-01 at 2:19 PM)mvsis> mvsis> mvsis> read_blifmv red-add.mvmvsis> read_blifmv red-add.mvmvsis> mvsis> mvsis> chng_namemvsis> chng_namechanging to short-name modechanging to short-name modemvsis> mvsis> mvsis> print_iomvsis> print_ioprimary inputs: a b c d eprimary inputs: a b c d eprimary outputs: {f} {g} {h}primary outputs: {f} {g} {h}mvsis> mvsis> mvsis> set autoexec pfsmvsis> set autoexec pfsred_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)red_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)mvsis> mvsis> mvsis> reset_defaultmvsis> reset_defaultred_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)red_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)mvsis> mvsis>

mvsis> simplifymvsis> simplifyred_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> fullsimpmvsis> fullsimpred_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> print_rangemvsis> print_range{f}:{f}: 22{g}:{g}: 22{h}:{h}: 22a:a: 88b:b: 88c:c: 88d:d: 88e:e: 88red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> encodemvsis> encodered_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> print_rangemvsis> print_range{f}:{f}: 22 o:o: 22{g}:{g}: 22 p:p: 22{h}:{h}: 22 q:q: 22i:i: 22 r:r: 22j:j: 22 s:s: 22k:k: 22 t:t: 22l:l: 22 u:u: 22m:m: 22 v:v: 22n:n: 22 w:w: 22red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> simplifymvsis> simplifyred_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> fullsimpmvsis> fullsimpred_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> print_iomvsis> print_ioprimary inputs: i j k l m n o p q r s t u v wprimary inputs: i j k l m n o p q r s t u v wprimary outputs: {f} {g} {h}primary outputs: {f} {g} {h}red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact.)mvsis> mvsis>

mvsis> read_blifmv red-add.mvmvsis> read_blifmv red-add.mvred_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)red_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)mvsis> mvsis>

mvsis> help encodemvsis> help encode

Feb 16, 2001 MVSIS(1)Feb 16, 2001 MVSIS(1) encode [-i] [-n] [-s]encode [-i] [-n] [-s] Encode the whole network into a binary one, considering both output Encode the whole network into a binary one, considering both output and input constraints. For sequential networks, a latch is encodedand input constraints. For sequential networks, a latch is encoded with constraints generated from both its inputs and outputswith constraints generated from both its inputs and outputs

-i keep primary inputs and outputs as multi-valued; add interface-i keep primary inputs and outputs as multi-valued; add interface nodes between the internal encoded binary network and PI/POs.nodes between the internal encoded binary network and PI/POs. This option allows validation of the result.This option allows validation of the result.

-n use natural code-n use natural code

-s use NO_COMP rather than ESPRESSO as the intermediate minimization-s use NO_COMP rather than ESPRESSO as the intermediate minimization method. The difference is only in performance. Ordinary usersmethod. The difference is only in performance. Ordinary users should not be concerned with this option.should not be concerned with this option.

red_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)red_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact.)mvsis> mvsis>

mvsis> encode -nmvsis> encode -nred_adder: 3 nodes, 3 POs, 1251 cubes(sop), 9432 lits(sop), 577 lits(fact.)red_adder: 3 nodes, 3 POs, 1251 cubes(sop), 9432 lits(sop), 577 lits(fact.)mvsis> mvsis>

mvsis> simplify -t 1000mvsis> simplify -t 1000red_adder: 3 nodes, 3 POs, 315 cubes(sop), 2010 lits(sop), 156 lits(fact.)red_adder: 3 nodes, 3 POs, 315 cubes(sop), 2010 lits(sop), 156 lits(fact.)mvsis> mvsis> mvsis> simplify -t 1000 -m exactmvsis> simplify -t 1000 -m exactred_adder: 3 nodes, 3 POs, 300 cubes(sop), 1989 lits(sop), 130 lits(fact.)red_adder: 3 nodes, 3 POs, 300 cubes(sop), 1989 lits(sop), 130 lits(fact.)mvsis> mvsis>

mvsis> validate -m mdd red-add-bin.mvmvsis> validate -m mdd red-add-bin.mvNetworks differ on (at least) primary output s1 i-set 0Networks differ on (at least) primary output s1 i-set 0Incorrect input is:Incorrect input is:0 x1_b00 x1_b01 x1_b11 x1_b11 x1_b21 x1_b20 x0_b00 x0_b00 x0_b10 x0_b10 x0_b20 x0_b20 y1_b00 y1_b00 y1_b10 y1_b10 y1_b20 y1_b20 y0_b00 y0_b00 y0_b10 y0_b10 y0_b20 y0_b20 cin_b00 cin_b00 cin_b10 cin_b10 cin_b20 cin_b2

Networks are NOT combinationally equivalent.Networks are NOT combinationally equivalent.red_adder: 3 nodes, 3 POs, 300 cubes(sop), 1989 lits(sop), 130 lits(fact.)red_adder: 3 nodes, 3 POs, 300 cubes(sop), 1989 lits(sop), 130 lits(fact.)mvsis> mvsis>

Conclusions

Multi-valued logic important in various applicationsPresented MVSIS, an multi-valued logic synthesis software infrastructureRelease 1.0 on Linux platform (as of June, 2001)

Support registers Support external don’t care networks External don’t cares from incomplete specification Sequential don’t care extraction Verification based on MDD representations Bug fixes

http://www-cad.eecs.berkeley.edu/Respep/Research/mvsis