multi-core ble 5.1 soc family with system pmu · da1469x multi-core ble 5.1 soc family with system...
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 1 of 733 © 2019 Dialog Semiconductor
General Description
The DA1469x is a family of multi-core wireless microcontrollers, combining the latest ARM Cortex M33TM application processor with floating-point unit, advanced power management functionality, a cryptographic security engine, analog and digital peripherals, a dedicated sensor node controller, and a software configurable protocol engine with a radio that is compliant to the Bluetooth® 5.1 low energy standard.
The DA1469x is based on an ARM Cortex-M33TM CPU with an 8-region MPU and a single-precision FPU offering up to 144 dMIPS. The dedicated application processor executes code from embedded memory (RAM) or external QSPI FLASH via a 16 kB 4-way associative cache controller, which is equipped with an on the fly decrypting capability without extra wait states. Bluetooth 5.1 connectivity is guaranteed by a new software-configurable Bluetooth low energy protocol engine (MAC) with an ultra-low-power radio transceiver, capable of +6 dBm output power and -97 dBm sensitivity offering a total link budget of 102 dBm.
An optimized programmable sensor node controller allows sensor node operations and data acquisition without CPU intervention, achieving best-in-class power consumption.
The advanced power management unit of the DA1469x enables it to run on primary and secondary batteries, as well as provide power to external devices through the integrated SIMO DCDC and integrated LDOs. The on-chip JEITA-compliant hardware charger makes it possible to natively charge rechargeable batteries over USB.
A variety of standard and advanced peripherals enable interaction with other system components and the development of advanced user interfaces and feature-rich applications.
Key Features
■ Complies with Bluetooth 5.1, ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan)
■ Flexible processing power
□ 32 kHz up to 96 MHz 32-bit ARM Cortex-M33 with 16 kBytes, 4-way associative cache and FPU
□ A flexible and configurable BLE MAC engine implementing the controller stack up to HCI
□ A sensor node controller running uCode for sensors manipulation
□ A uCode based motor controller for manipulating analog gear boxes for hands on watches
□ Optimized power modes (Extended sleep, Deep sleep and Hibernation)
■ Memories
□ 512 kB Data SRAM with retention capabilities
□ 4 kB One-Time-Programmable (OTP) memory
□ 16 kB Cache SRAM with retention capabilities
□ 128 kB ROM (including boot ROM and PKI routines for Flash image authentication)
■ Power management
□ SIMO Buck DC-DC converter (2.4 V-4.75 V)
□ Four power supply pins for external devices, alive while DA1469x is asleep
□ Supports Li-Polymer, Li-Ion, coin cells, NiMH and alkaline batteries
□ Hardware charger (up to 5.0 V) with programmable curves and JEITA support
□ Programmable thresholds for brownout detection
■ Digital controlled oscillators
□ 32 MHz crystal (±20 ppm max) and RC oscillator
□ 32 kHz crystal (±50 ppm, ±500 ppm max) and RCX oscillator
■ Application cryptographic engine with AES-256, SHA-1, SHA-256, SHA-512 and a FIPS 140-2-compliant True Random Number Generator (TRNG)
■ A Real Time Clock with 10 ms resolution
■ 4 General purpose, 24-bit up/down timers with PWM
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 2 of 733 © 2019 Dialog Semiconductor
■ Digital interfaces
□ Up to 55 General Purpose I/Os
□ Decrypt-on-the-fly QSPI FLASH interface
□ Separate QSPI PSRAM interface
□ Parallel/SPI LCD Controller with own DMA
□ 3 x UARTs up to 1 Mbps, one UART extended to support ISO7816
□ 2 SPI+™ controllers
□ 2 I2C controllers at 100 kHz, 400 kHz or 3.4 MHz
□ PDM interface with HW sample rate converter
□ I2S/PCM master/slave interface up to 8 channels
□ USB 1.1 Full Speed device interface
■ Analog interfaces
□ 8-channel 10-bit SAR ADC, 3.4 Msamples/sec
□ 8-channel 14-bit ΣΔ ADC, 1000 samples/sec
□ Haptic driver interface to LRA/ERM motors
□ 2 matched White LED drivers
■ Radio transceiver
□ Single wire antenna: no RF matching or RX/TX switching required
□ Supply current at VBAT2: TX: 3.5 mA, RX: 2.2 mA (with ideal DC-DC)
□ Configurable transmit output power -18 to +6 dBm
□ -97 dBm receiver sensitivity
□ 2 Mbps support
■ Packages:
□ VFBGA86, 6x6, 0.55 mm pitch
□ VFBGA100, 5x5, 0.475 mm pitch
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 3 of 733 © 2019 Dialog Semiconductor
Applications
■ Fitness trackers
■ Sport watches
■ Smartwatches
■ Voice-controlled remote controls
■ Rechargeable keyboards
■ Toys
■ Consumer appliances
■ Home automation
■ Industrial automation
Key Benefits
■ Lowest power consumption
■ Smallest system size
■ Lowest system cost
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 4 of 733 © 2019 Dialog Semiconductor
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 3
Key Benefits ......................................................................................................................................... 3
Contents ............................................................................................................................................... 4
Figures ................................................................................................................................................ 13
Tables ................................................................................................................................................. 15
1 Block Diagram ............................................................................................................................. 33
2 Application Information .............................................................................................................. 34
3 DA1469x Product Family ............................................................................................................ 36
4 Pinout ........................................................................................................................................... 37
4.1 VFBGA86 Pinout ................................................................................................................. 37
4.2 VFBGA100 Pinout ............................................................................................................... 49
5 Specifications .............................................................................................................................. 63
5.1 Absolute Maximum Ratings ................................................................................................ 64
5.2 Recommended Operating Conditions ................................................................................. 64
5.3 DC Characteristics .............................................................................................................. 65
5.4 Timing Characteristics ......................................................................................................... 67
5.5 Thermal Characteristics ...................................................................................................... 67
5.6 Reset Characteristics .......................................................................................................... 68
5.7 Brown-Out Detector Characteristics ................................................................................... 68
5.8 General Purpose ADC Characteristics ............................................................................... 68
5.9 ΣΔ ADC Characteristics ...................................................................................................... 69
5.10 DC-DC Converter Characteristics ....................................................................................... 70
5.11 LDOs Characteristics .......................................................................................................... 71
5.12 32 kHz Crystal Oscillator Characteristics ............................................................................ 77
5.13 32 MHz Crystal Oscillator Characteristics ........................................................................... 78
5.14 RCX Oscillator Characteristics ............................................................................................ 79
5.15 32MHz RC Oscillator Characteristics .................................................................................. 79
5.16 PLL Characteristics ............................................................................................................. 79
5.17 Charger Characteristics ...................................................................................................... 79
5.18 Battery Check Characteristics ............................................................................................. 83
5.19 Digital I/O Characteristics.................................................................................................... 83
5.20 QSPI Characteristics ........................................................................................................... 84
5.21 LED Characteristics ............................................................................................................ 85
5.22 LRA Characteristics ............................................................................................................ 86
5.23 USB Characteristics ............................................................................................................ 86
5.24 Radio Characteristics .......................................................................................................... 86
6 System Overview ......................................................................................................................... 94
6.1 Internal Blocks ..................................................................................................................... 94
6.2 Digital Power Domains ........................................................................................................ 95
6.3 HW FSM (POWERUP, WAKEUP, GOTO Sleep) ............................................................... 97
6.3.1 HW FSM .............................................................................................................. 97
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 5 of 733 © 2019 Dialog Semiconductor
6.3.2 POWERUP .......................................................................................................... 97
6.3.3 WAKEUP Options ................................................................................................ 98
6.3.3.1 Slow WAKEUP ................................................................................ 99
6.3.3.2 Fast WAKEUP ................................................................................. 99
6.3.3.3 Ultra-Fast WAKEUP ...................................................................... 100
6.3.4 Go-To-Sleep ...................................................................................................... 100
6.4 Power Modes and Rails .................................................................................................... 100
6.5 OTP ................................................................................................................................... 105
6.5.1 OTP Segments .................................................................................................. 105
6.5.2 Configuration Script ........................................................................................... 105
6.5.3 Keys and Indexing ............................................................................................. 106
6.5.4 Customer Application Area ................................................................................ 107
6.6 FLASH ............................................................................................................................... 107
6.7 Booting .............................................................................................................................. 109
6.7.1 Initialization ........................................................................................................ 111
6.7.2 Configuration Script ........................................................................................... 111
6.7.3 Retrieve Application Code ................................................................................. 111
6.7.4 Device Administration ........................................................................................ 111
6.7.5 Load Image ........................................................................................................ 112
6.8 Memory Map ..................................................................................................................... 112
6.9 Resource Sharing ............................................................................................................. 114
6.10 Remapping ........................................................................................................................ 115
6.11 Security Features .............................................................................................................. 115
6.11.1 Secure Keys Manipulation ................................................................................. 116
6.11.2 Secure Boot ....................................................................................................... 116
6.11.3 Secure Access ................................................................................................... 116
6.11.4 Validation ........................................................................................................... 117
6.11.5 Cryptography Operations................................................................................... 117
7 Power .......................................................................................................................................... 118
7.1 Introduction ....................................................................................................................... 118
7.2 Architecture ....................................................................................................................... 119
7.2.1 SIMO DC-DC Converter .................................................................................... 119
7.2.2 LDOs .................................................................................................................. 120
7.2.3 Switching between DC-DC and LDOs ............................................................... 120
7.2.4 Low power clamps ............................................................................................. 121
7.2.5 Battery check ..................................................................................................... 121
7.2.6 Charger .............................................................................................................. 122
7.2.6.1 JEITA ............................................................................................. 123
7.2.6.2 Errors and Flags ............................................................................ 124
7.2.6.3 Timers ............................................................................................ 125
7.2.7 Charger Detection .............................................................................................. 126
7.2.7.1 Contact Detection .......................................................................... 127
7.2.7.2 Primary Charger Detection ............................................................ 127
7.2.7.3 Secondary Charger Detection ....................................................... 127
7.2.7.4 Smartphone Charger Detection ..................................................... 128
8 Power Domain Controller (PDC) .............................................................................................. 129
8.1 Introduction ....................................................................................................................... 129
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 6 of 733 © 2019 Dialog Semiconductor
8.2 Architecture ....................................................................................................................... 130
8.2.1 Look-Up Table ................................................................................................... 130
8.2.2 Operation ........................................................................................................... 131
8.3 Programming ..................................................................................................................... 132
9 Brown-Out Detector .................................................................................................................. 133
9.1 Introduction ....................................................................................................................... 133
9.2 Architecture ....................................................................................................................... 134
9.2.1 Brown-Out Detector Monitor Levels .................................................................. 134
9.2.2 Brown-Out Detector Clock ................................................................................. 134
9.3 Programming ..................................................................................................................... 134
10 Reset ........................................................................................................................................... 135
10.1 Introduction ....................................................................................................................... 135
10.2 Architecture ....................................................................................................................... 136
10.2.1 Power-On Reset From Pin................................................................................. 138
10.3 Programming ..................................................................................................................... 139
11 ARM Cortex M33 ........................................................................................................................ 140
11.1 Introduction ....................................................................................................................... 140
11.2 Architecture ....................................................................................................................... 140
11.2.1 Interrupts ............................................................................................................ 140
11.2.2 Reference .......................................................................................................... 142
12 Cache Controller ....................................................................................................................... 143
12.1 Introduction ....................................................................................................................... 143
12.2 Architecture ....................................................................................................................... 144
12.2.1 Cacheable Range .............................................................................................. 144
12.2.2 Runtime Reconfiguration ................................................................................... 144
12.2.2.1 Cache Line Reconfiguration .......................................................... 144
12.2.2.2 TAG Memory Word ........................................................................ 145
12.2.2.3 Associativity Reconfiguration ......................................................... 145
12.2.3 Replacement Strategy ....................................................................................... 145
12.2.4 Cache Reset ...................................................................................................... 145
12.2.5 Miss Rate Monitor .............................................................................................. 146
12.2.6 Miss Latency and Power.................................................................................... 146
12.3 Programming ..................................................................................................................... 147
12.3.1 Cache Controller Programming ......................................................................... 147
12.3.2 Miss Rate Monitor Programming ....................................................................... 147
13 Bus .............................................................................................................................................. 148
13.1 Introduction ....................................................................................................................... 148
13.2 Architecture ....................................................................................................................... 149
14 Configurable MAC (CMAC) ....................................................................................................... 151
14.1 Introduction ....................................................................................................................... 151
14.2 Architecture ....................................................................................................................... 152
14.2.1 Dataflow ............................................................................................................. 152
14.2.2 Diagnostics ........................................................................................................ 152
15 Sensor Node Controller (SNC) ................................................................................................. 153
15.1 Introduction ....................................................................................................................... 153
15.2 Architecture ....................................................................................................................... 153
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 7 of 733 © 2019 Dialog Semiconductor
15.2.1 Sensor Node Instruction Set .............................................................................. 154
15.2.2 SNC Clocking Considerations ........................................................................... 156
15.3 Programming ..................................................................................................................... 156
16 Memory Controller .................................................................................................................... 157
16.1 Introduction ....................................................................................................................... 157
16.2 Architecture ....................................................................................................................... 158
16.3 Programming ..................................................................................................................... 158
17 Clock Generation ....................................................................................................................... 161
17.1 Clock Tree ......................................................................................................................... 161
17.2 Crystal Oscillators ............................................................................................................. 163
17.2.1 Frequency Control (32 MHz Crystal) ................................................................. 163
17.3 RC Oscillators ................................................................................................................... 164
17.3.1 Frequency Calibration ........................................................................................ 164
17.4 PLL .................................................................................................................................... 164
18 OTP Controller ........................................................................................................................... 166
18.1 Introduction ....................................................................................................................... 166
18.2 Architecture ....................................................................................................................... 166
18.3 Programming ..................................................................................................................... 168
19 Quad SPI FLASH Controller ..................................................................................................... 169
19.1 Introduction ....................................................................................................................... 169
19.2 Architecture ....................................................................................................................... 170
19.2.1 Interface ............................................................................................................. 170
19.2.2 Initialization FSM ............................................................................................... 170
19.2.3 SPI Modes ......................................................................................................... 171
19.2.4 Access Modes ................................................................................................... 172
19.2.5 Endianess .......................................................................................................... 172
19.2.6 Erase Suspend/Resume .................................................................................... 172
19.2.7 On-the-fly Decryption ......................................................................................... 174
19.2.8 Timing ................................................................................................................ 174
19.3 Programming ..................................................................................................................... 176
19.3.1 Auto Mode ......................................................................................................... 176
19.3.2 Manual Mode ..................................................................................................... 176
19.3.3 Clock Selection .................................................................................................. 177
19.3.4 Receiving Data .................................................................................................. 177
19.3.5 Delay Line Configuration ................................................................................... 177
20 Quad SPI RAM/FLASH Controller ............................................................................................ 178
20.1 Introduction ....................................................................................................................... 178
20.2 Architecture ....................................................................................................................... 179
20.2.1 Interface ............................................................................................................. 179
20.2.2 SPI Modes ......................................................................................................... 179
20.2.3 Access Modes ................................................................................................... 179
20.2.4 Endianness ........................................................................................................ 180
20.2.5 Erase Suspend/Resume .................................................................................... 180
20.2.6 Low Power Considerations ................................................................................ 182
20.3 Programming ..................................................................................................................... 183
20.3.1 Auto Mode ......................................................................................................... 183
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 8 of 733 © 2019 Dialog Semiconductor
20.3.2 Manual Mode ..................................................................................................... 185
20.3.3 Clock Selection .................................................................................................. 185
20.3.4 Received Data ................................................................................................... 185
20.3.5 Delay Line Configuration ................................................................................... 185
21 Step Motor Controller ............................................................................................................... 186
21.1 Introduction ....................................................................................................................... 186
21.2 Architecture ....................................................................................................................... 187
21.2.1 Commands and Waves ..................................................................................... 187
21.2.2 Pattern Generators (PGs) .................................................................................. 189
21.2.3 Interrupt Generator ............................................................................................ 190
21.3 Programming ..................................................................................................................... 190
22 LCD Controller ........................................................................................................................... 192
22.1 Introduction ....................................................................................................................... 192
22.2 Architecture ....................................................................................................................... 193
22.2.1 Parallel LCD Interfaces ...................................................................................... 193
22.2.1.1 HSYNC / VSYNC Parallel Interface ............................................... 193
22.2.1.2 JDI Parallel Interface ..................................................................... 193
22.2.2 Serial LCD Interfaces ......................................................................................... 194
22.2.2.1 SPI3/4 Serial Interface ................................................................... 194
22.2.2.2 JDI SPI Serial Interface ................................................................. 195
22.2.3 Color Input Formats ........................................................................................... 196
22.2.4 Color Output Formats ........................................................................................ 198
22.2.4.1 SPI Output Formats ....................................................................... 198
22.2.4.2 JDI SPI Output Formats ................................................................ 198
22.3 Programming ..................................................................................................................... 199
23 DMA Controller .......................................................................................................................... 200
23.1 Introduction ....................................................................................................................... 200
23.2 Architecture ....................................................................................................................... 201
23.2.1 DMA Peripherals ................................................................................................ 201
23.2.2 Input/Output Multiplexer..................................................................................... 201
23.2.3 DMA Channel Operation.................................................................................... 201
23.2.4 DMA Arbitration ................................................................................................. 203
23.2.5 Freezing DMA Channels.................................................................................... 203
23.2.6 Secure DMA Channel ........................................................................................ 203
23.3 Programming ..................................................................................................................... 203
23.3.1 Memory to Memory Transfer ............................................................................. 203
23.3.2 Peripheral to Memory Transfer .......................................................................... 204
24 Crypto Engine ............................................................................................................................ 205
24.1 Introduction ....................................................................................................................... 205
24.2 Architecture ....................................................................................................................... 205
24.2.1 AES .................................................................................................................... 206
24.2.2 Operation Modes ............................................................................................... 206
24.2.3 HASH ................................................................................................................. 206
24.3 Programming ..................................................................................................................... 206
24.3.1 AES Engine Programming ................................................................................. 206
24.3.2 HASH Engine Programming .............................................................................. 207
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 9 of 733 © 2019 Dialog Semiconductor
25 True Random Number Generator ............................................................................................ 208
25.1 Introduction ....................................................................................................................... 208
25.2 Architecture ....................................................................................................................... 208
25.3 Programming ..................................................................................................................... 208
26 Wake-Up Controller ................................................................................................................... 210
26.1 Introduction ....................................................................................................................... 210
26.2 Architecture ....................................................................................................................... 210
26.3 Programming ..................................................................................................................... 211
27 General Purpose ADC ............................................................................................................... 212
27.1 Introduction ....................................................................................................................... 212
27.2 Architecture ....................................................................................................................... 212
27.2.1 Input Channels and Input Scale ........................................................................ 213
27.2.2 Operation ........................................................................................................... 213
27.2.2.1 Enabling the ADC .......................................................................... 215
27.2.3 Operating Modes ............................................................................................... 215
27.2.3.1 Manual Mode ................................................................................. 215
27.2.3.2 Continuous Mode ........................................................................... 215
27.2.4 Conversion Modes ............................................................................................. 215
27.2.4.1 ADC Conversion ............................................................................ 215
27.2.4.2 Oversampling Mode....................................................................... 217
27.2.4.3 Chopper Mode ............................................................................... 217
27.2.5 Additional Settings ............................................................................................. 218
27.2.6 Non-Ideal Effects ............................................................................................... 218
27.2.7 Offset Calibration ............................................................................................... 218
27.2.8 Zero-Scale Adjustment ...................................................................................... 219
27.2.9 Common Mode Adjustment ............................................................................... 219
27.2.10 Input Impedance, Inductance and Input Settling ............................................... 219
27.3 Programming ..................................................................................................................... 220
28 ΣΔ ADC ....................................................................................................................................... 221
28.1 Introduction ....................................................................................................................... 221
28.2 Architecture ....................................................................................................................... 221
28.3 Programming ..................................................................................................................... 222
29 Audio Unit (AU) .......................................................................................................................... 223
29.1 Introduction ....................................................................................................................... 223
29.2 Architecture ....................................................................................................................... 224
29.2.1 Data Paths ......................................................................................................... 224
29.2.2 Up/Down Sampler .............................................................................................. 225
29.2.3 PCM Interface .................................................................................................... 225
29.2.3.1 Channel Access and Delay ........................................................... 225
29.2.3.2 Clock Generation ........................................................................... 225
29.2.3.3 External Synchronization ............................................................... 228
29.2.3.4 Data Formats ................................................................................. 228
29.2.4 PDM Interface .................................................................................................... 231
29.2.5 DMA Support ..................................................................................................... 232
29.2.6 Interrupts ............................................................................................................ 232
29.3 Programming ..................................................................................................................... 232
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 10 of 733 © 2019 Dialog Semiconductor
29.3.1 PDM Input to PCM Output ................................................................................. 232
30 I2C Interface ............................................................................................................................... 234
30.1 Introduction ....................................................................................................................... 234
30.2 Architecture ....................................................................................................................... 235
30.2.1 I2C Behavior ...................................................................................................... 235
30.2.1.1 START and STOP Generation .......................................................................... 236
30.2.1.2 Combined Formats ............................................................................................ 236
30.2.2 I2C Protocols ..................................................................................................... 236
30.2.2.1 START and STOP Conditions ........................................................................... 236
30.2.2.2 Addressing Slave Protocol................................................................................. 237
30.2.2.3 Transmitting and Receiving Protocols ............................................................... 238
30.2.3 Multiple Master Arbitration ................................................................................. 239
30.2.4 Clock Synchronization ....................................................................................... 240
30.3 Programming ..................................................................................................................... 241
31 UART ........................................................................................................................................... 242
31.1 Introduction ....................................................................................................................... 242
31.2 Architecture ....................................................................................................................... 243
31.2.1 UART (RS232) Serial Protocol .......................................................................... 243
31.2.2 Clock Support .................................................................................................... 245
31.2.3 Interrupts ............................................................................................................ 245
31.2.4 Programmable THRE Interrupt .......................................................................... 246
31.2.5 Shadow Registers .............................................................................................. 248
31.2.6 Direct Test Mode ............................................................................................... 248
31.3 Programming ..................................................................................................................... 248
32 Smart Card Interface ................................................................................................................. 250
32.1 Introduction ....................................................................................................................... 250
32.2 Architecture ....................................................................................................................... 250
32.2.1 ISO7816-3 Clock Generation ............................................................................ 250
32.2.2 ISO7816-3 Timer – Guard Time ........................................................................ 251
32.2.3 ISO7816-3 Error Detection ................................................................................ 251
32.3 Programming ..................................................................................................................... 251
33 SPI+ Interface ............................................................................................................................. 253
33.1 Introduction ....................................................................................................................... 253
33.2 Architecture ....................................................................................................................... 254
33.2.1 Master Mode ...................................................................................................... 254
33.2.2 Slave Mode ........................................................................................................ 254
33.2.3 SPI_POL and SPI_PHA..................................................................................... 254
33.2.4 SPI_DO Idle Levels ........................................................................................... 254
33.2.5 Write Only Mode ................................................................................................ 254
33.2.6 Read Only Mode ................................................................................................ 255
33.2.7 Bidirectional Transfers with FIFO ...................................................................... 255
33.2.8 TXreq Mode ....................................................................................................... 255
33.2.9 DMA Operation Requirements .......................................................................... 255
33.2.10 The 9-Bit Mode .................................................................................................. 255
33.2.11 Timing Diagrams ................................................................................................ 255
33.3 Programming ..................................................................................................................... 257
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 11 of 733 © 2019 Dialog Semiconductor
34 Real Time Clock ......................................................................................................................... 258
34.1 Introduction ....................................................................................................................... 258
34.2 Architecture ....................................................................................................................... 258
34.3 Programming ..................................................................................................................... 259
35 General Purpose Timers ........................................................................................................... 261
35.1 Introduction ....................................................................................................................... 261
35.2 Architecture ....................................................................................................................... 261
35.3 Programming ..................................................................................................................... 262
36 Watchdog Timers ...................................................................................................................... 264
36.1 Introduction ....................................................................................................................... 264
36.2 Architecture ....................................................................................................................... 265
36.3 Programming ..................................................................................................................... 265
36.3.1 System Watchdog .............................................................................................. 265
36.3.2 CMAC Watchdog ............................................................................................... 266
37 USB Controller ........................................................................................................................... 267
37.1 Introduction ....................................................................................................................... 267
37.2 Architecture ....................................................................................................................... 268
37.2.1 Serial Interface Engine ...................................................................................... 268
37.2.2 Endpoint Pipe Controller (EPC) ......................................................................... 268
37.2.3 Functional States ............................................................................................... 269
37.2.3.1 Line Condition Detection ............................................................... 269
37.2.4 Functional State Diagram .................................................................................. 270
37.2.5 Address Detection ............................................................................................. 272
37.2.6 Transmit and Receive Endpoint FIFOs ............................................................. 273
37.2.7 Bidirectional Control Endpoint FIFO0 ................................................................ 274
37.2.8 Transmit Endpoint FIFO .................................................................................... 275
37.2.9 Receive Endpoint FIFO ..................................................................................... 276
37.2.10 Interrupt Hierarchy ............................................................................................. 277
37.2.11 USB Power Saving Modes ................................................................................ 278
37.2.11.1 Freezing USB Node ....................................................................... 279
37.2.11.2 Integrated resistors ........................................................................ 279
38 Haptic Driver .............................................................................................................................. 281
38.1 Introduction ....................................................................................................................... 281
38.2 Architecture ....................................................................................................................... 281
38.2.1 Resonance Control ............................................................................................ 283
38.3 Programming ..................................................................................................................... 284
38.4 Legal.................................................................................................................................. 285
39 LEDs Driver ................................................................................................................................ 286
39.1 Introduction ....................................................................................................................... 286
39.2 Architecture ....................................................................................................................... 286
39.3 Programming ..................................................................................................................... 287
40 Input/Output Ports ..................................................................................................................... 288
40.1 Introduction ....................................................................................................................... 288
40.2 Architecture ....................................................................................................................... 288
40.2.1 Programmable Pin Assignment ......................................................................... 288
40.2.1.1 Priority ............................................................................................ 289
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 12 of 733 © 2019 Dialog Semiconductor
40.2.1.2 Direction Control ............................................................................ 289
40.2.2 General Purpose Port Registers ........................................................................ 289
40.2.2.1 Port Data Register ......................................................................... 289
40.2.2.2 Port Set Data Output Register ....................................................... 289
40.2.2.3 Port Reset Data Output Register ................................................... 289
40.2.3 Fixed Assignment Functionality ......................................................................... 290
40.2.4 GPIO State Retention While Sleeping ............................................................... 293
40.2.5 Special I/O Considerations ................................................................................ 294
41 Radio ........................................................................................................................................... 295
41.1 Introduction ....................................................................................................................... 295
41.2 Architecture ....................................................................................................................... 295
41.2.1 Receiver ............................................................................................................. 295
41.2.2 Synthesizer ........................................................................................................ 296
41.2.3 Transmitter ......................................................................................................... 296
41.2.4 RFIO .................................................................................................................. 296
41.2.5 Biasing ............................................................................................................... 296
41.2.6 RF Monitoring .................................................................................................... 296
42 Registers .................................................................................................................................... 297
42.1 AMBA Bus Registers ......................................................................................................... 297
42.2 LCD Controller Registers .................................................................................................. 300
42.3 LRA/ERM Registers .......................................................................................................... 311
42.4 Memory Controller Registers ............................................................................................ 319
42.5 OTP Controller Registers .................................................................................................. 326
42.6 LED Controller Registers .................................................................................................. 331
42.7 QSPI Flash Registers ........................................................................................................ 333
42.8 QSPI Ram Registers ......................................................................................................... 348
42.9 RF Monitor Registers ........................................................................................................ 363
42.10 Real Time Clock Registers................................................................................................ 365
42.11 Motor Controller Registers ................................................................................................ 371
42.12 Sensor Node Controller Registers .................................................................................... 378
42.13 SPI Controller Registers.................................................................................................... 383
42.14 Timers Registers ............................................................................................................... 388
42.15 True Random Number Generator Controller Registers .................................................... 404
42.16 UART Registers ................................................................................................................ 404
42.17 USB Controller Registers .................................................................................................. 486
42.18 Silicon Version Registers .................................................................................................. 523
42.19 Wake-Up Controller Registers .......................................................................................... 524
42.20 Watchdog Controller Registers ......................................................................................... 527
42.21 General Purpose / ΣΔ ADC Registers .............................................................................. 528
42.22 General Purpose I/O Registers ......................................................................................... 534
42.23 General Purpose Registers ............................................................................................... 557
42.24 I2C Controller Registers .................................................................................................... 560
42.25 Power Domain Controller Registers .................................................................................. 607
42.26 DCDC Converter Registers ............................................................................................... 615
42.27 DMA Controller Registers ................................................................................................. 624
42.28 Charger Registers ............................................................................................................. 651
42.29 Clock Generation Controller Registers ............................................................................. 683
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 13 of 733 © 2019 Dialog Semiconductor
42.30 Cache Controller Registers ............................................................................................... 710
42.31 Audio Unit Registers ......................................................................................................... 714
42.32 Analog Miscellaneous Registers ....................................................................................... 721
42.33 Crypto-Engine Registers ................................................................................................... 722
43 Ordering Information ................................................................................................................ 728
44 Package information ................................................................................................................. 729
44.1 Moisture Sensitivity Level (MSL) ....................................................................................... 729
44.2 Soldering information ........................................................................................................ 729
44.3 Package outlines ............................................................................................................... 729
Revision History .............................................................................................................................. 732
Figures
Figure 1: DA1469x Block Diagram ...................................................................................................... 33 Figure 2: Activity Tracker ..................................................................................................................... 34 Figure 3: Analog Watch ....................................................................................................................... 34 Figure 4: Sport Watch .......................................................................................................................... 35 Figure 5: VFBGA86 Ball Assignment .................................................................................................. 37 Figure 6: VFBGA100 Ball Assignment ................................................................................................ 49 Figure 7: Digital Power Domains and Blocks Mapping ....................................................................... 96 Figure 8: POWERUP, WAKEUP, GOTO Sleep HW FSM .................................................................. 97 Figure 9: POWERUP Timing Diagram ................................................................................................ 98 Figure 10: Slow Wake-Up Timing ........................................................................................................ 99 Figure 11: Fast WAKEUP timing ......................................................................................................... 99 Figure 12: Ultra Fast Wake-Up timing ............................................................................................... 100 Figure 13: FLASH Regions and Layout ............................................................................................. 108 Figure 14: BootROM flowchart .......................................................................................................... 110 Figure 15: Power Management Unit Architecture ............................................................................. 118 Figure 16: SIMO DCDC block diagram ............................................................................................. 119 Figure 17: Battery Check Block Diagram .......................................................................................... 121 Figure 18: Charger HW Finite State Machine Diagram ..................................................................... 123 Figure 19: Battery Temperature Monitoring FSM .............................................................................. 124 Figure 20: Charger Detection Circuit ................................................................................................. 126 Figure 21: Power Domain Controller block diagram ......................................................................... 129 Figure 22: Brown-Out Detector Block Diagram ................................................................................. 133 Figure 23: BOD FSM Timing Diagram in Sleep Mode ...................................................................... 134 Figure 24: Reset Block Diagram ....................................................................................................... 135 Figure 25: Power-on Reset timing diagram ....................................................................................... 139 Figure 26: Cache Controller Block Diagram ...................................................................................... 144 Figure 27: Bus Architecture ............................................................................................................... 149 Figure 28: Configurable MAC Block Diagram ................................................................................... 151 Figure 29: CMAC Diagnostics Timing Diagram................................................................................. 152 Figure 30: Sensor Node Controller Block Diagram ........................................................................... 153 Figure 31: Internal Architecture of the Memory Controller ................................................................ 157 Figure 32: Example of Memory Segments Mapping ......................................................................... 160 Figure 33: Clock Tree Diagram ......................................................................................................... 162 Figure 34: Crystal Oscillator Circuits ................................................................................................. 163 Figure 35: XTAL32MHz Oscillator Frequency Trimming ................................................................... 164 Figure 36: OTP Controller Block Diagram ......................................................................................... 166 Figure 37: QSPI FLASH Controller Block Diagram ........................................................................... 169 Figure 38: Erase Suspend/Resume in Auto Mode ............................................................................ 173 Figure 39: QSPI Input Timing ............................................................................................................ 175 Figure 40: QSPI Output Timing ......................................................................................................... 175 Figure 41: Quad SPI RAM/FLASH Controller ................................................................................... 178 Figure 42: Erase Suspend/Resume in Auto Mode ............................................................................ 182
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 14 of 733 © 2019 Dialog Semiconductor
Figure 43: QSPI Split Burst Timing for Low Power (QSPI_FORENSEQ_EN=1) .............................. 183 Figure 44: QSPI Burst Timing for High Performance (QSPI_FORENSEQ_EN=0) .......................... 183 Figure 45: Motor Controller Block Diagram ....................................................................................... 186 Figure 46: Commands and Waveform Format .................................................................................. 187 Figure 47: Loading Waves into Waves Memory Space .................................................................... 189 Figure 48: Waveform Generation in Signal Pairs .............................................................................. 189 Figure 49: LCD Controller Block Diagram ......................................................................................... 192 Figure 50: HSYNC/VSYNC Typical Waveform ................................................................................. 193 Figure 51: HSYNC/VSYNC Color Bits Waveform ............................................................................. 193 Figure 52: DMA controller block diagram .......................................................................................... 200 Figure 53: DMA channel diagram ...................................................................................................... 202 Figure 54: AES/HASH Architecture ................................................................................................... 205 Figure 55: TRNG block diagram ........................................................................................................ 208 Figure 56: Wake-Up Controller Block Diagram ................................................................................. 210 Figure 57: General-Purpose ADC Block Diagram ............................................................................. 212 Figure 58: GPADC Operation Flow Diagram .................................................................................... 214 Figure 59: Block diagram of the ΣΔ ADC .......................................................................................... 221 Figure 60: Audio Unit Block Diagram ................................................................................................ 224 Figure 61: PCM Interface Formats .................................................................................................... 229 Figure 62: I2S Mode .......................................................................................................................... 230 Figure 63: TDM mode (left justified mode) ........................................................................................ 230 Figure 64: IOM format ....................................................................................................................... 231 Figure 65: PDM Mono/Stereo formats ............................................................................................... 231 Figure 66: SRC PDM Input Transfer Function .................................................................................. 231 Figure 67: I2C Controller Block Diagram ........................................................................................... 234 Figure 68: Data Transfer on the I2C Bus .......................................................................................... 235 Figure 69: START and STOP Conditions .......................................................................................... 236 Figure 70: 7-bit Address Format ........................................................................................................ 237 Figure 71: 10-bit Address Format ...................................................................................................... 237 Figure 72: Master-Transmitter Protocol ............................................................................................. 238 Figure 73: Master-Receiver Protocol ................................................................................................. 239 Figure 74: START BYTE Transfer ..................................................................................................... 239 Figure 75: Multiple Master Arbitration ............................................................................................... 240 Figure 76: Multiple Master Clock Synchronization. ........................................................................... 241 Figure 77: UART Block Diagram ....................................................................................................... 243 Figure 78: Serial Data Format ........................................................................................................... 243 Figure 79: Receiver Serial Data Sampling Points ............................................................................. 244 Figure 80: Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode ................... 247 Figure 81: Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode ... 248 Figure 82: Smart Card (ISO7816-3) Block Diagram ......................................................................... 250 Figure 83: SPI Block Diagram ........................................................................................................... 253 Figure 84: SPI Master/Slave, Mode 0: SPI_POL=0 and SPI_PHA=0 ............................................... 256 Figure 85: SPI Master/Slave, Mode 1: SPI_POL=0 and SPI_PHA=1 ............................................... 256 Figure 86: SPI Master/Slave, Mode 2: SPI_POL=1 and SPI_PHA=0 ............................................... 256 Figure 87: SPI Master/slave, Mode 3: SPI_POL=1 and SPI_PHA=1 ............................................... 257 Figure 88: Real Time Clock Block Diagram ...................................................................................... 258 Figure 89: General Purpose Timer’s Block Diagram ......................................................................... 261 Figure 90: System Watchdog Block Diagram.................................................................................... 264 Figure 91: USB Node Block Diagram ................................................................................................ 268 Figure 92: Endpoint Operation .......................................................................................................... 269 Figure 93: Node Functional State Diagram ....................................................................................... 271 Figure 94: USB Function Address/Endpoint Decoding ..................................................................... 273 Figure 95: Endpoint 0 Operation ....................................................................................................... 275 Figure 96: USB Tx FIFO Operation ................................................................................................... 276 Figure 97: USB Rx FIFO Operation .................................................................................................. 277 Figure 98: USB Interrupt Register Hierarchy..................................................................................... 278 Figure 99: USB_Dp Resistor Switching ............................................................................................. 279 Figure 100: USB_Dm Resistor Switching .......................................................................................... 280 Figure 101: Block Diagram of the Haptic Driver ................................................................................ 281
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 15 of 733 © 2019 Dialog Semiconductor
Figure 102: Circuit Diagram of the Haptic Driver and Equivalent Electrical Model of an LRA .......... 283 Figure 103: LED Driver Block Diagram ............................................................................................. 286 Figure 104: Port P0 and P1 with Programmable Pin Assignment..................................................... 288 Figure 105: Latching of Digital Pad Signals ...................................................................................... 293 Figure 106: Latching of QSPI Pad Signals ........................................................................................ 293 Figure 107: Radio Block Diagram ..................................................................................................... 295 Figure 108: VFBGA86 Package Outline Drawing ............................................................................. 730 Figure 109: VFBGA100 Package Outline Drawing ........................................................................... 731
Tables
Table 1: DA1469x Product Family Differentiation ............................................................................... 36 Table 2: DA14691/5 Pin Description ................................................................................................... 38 Table 3: DA14697/9 Pin Description ................................................................................................... 50 Table 4: Absolute Maximum Ratings ................................................................................................... 64 Table 5: Recommended Operating Conditions ................................................................................... 64 Table 6: DC Characteristics................................................................................................................. 65 Table 7: Timing Characteristics ........................................................................................................... 67 Table 8: Thermal Characteristics ........................................................................................................ 67 Table 9: PAD_RST - DC Characteristics ............................................................................................. 68 Table 10: BOD - DC Characteristics ................................................................................................... 68 Table 11: GP_ADC - Recommended Operating Conditions ............................................................... 68 Table 12: GP_ADC - DC Characteristics ............................................................................................ 68 Table 13: GP_ADC - Timing Characteristics ....................................................................................... 69 Table 14: SD_ADC - DC Characteristics ............................................................................................. 69 Table 15: SD_ADC - AC Characteristics ............................................................................................. 70 Table 16: SD_ADC - Electrical performance ....................................................................................... 70 Table 17: DCDC - Recommended Operating Conditions ................................................................... 70 Table 18: DCDC - DC Characteristics ................................................................................................. 70 Table 19: LDO_1V8 - Recommended Operating Conditions .............................................................. 71 Table 20: LDO_1V8 - DC Characteristics ........................................................................................... 72 Table 21: LDO_1V8 - AC Characteristics ............................................................................................ 72 Table 22: LDO_1V8_RET - Recommended Operating Conditions ..................................................... 72 Table 23: LDO_1V8_RET - DC Characteristics .................................................................................. 72 Table 24: LDO_1V8P_RET - Recommended Operating Conditions .................................................. 73 Table 25: LDO_1V8P_RET - DC Characteristics ................................................................................ 73 Table 26: LDO_CORE - Recommended Operating Conditions .......................................................... 73 Table 27: LDO_CORE - DC Characteristics ....................................................................................... 73 Table 28: LDO_CORE_RET - Recommended Operating Conditions ................................................. 74 Table 29: LDO_CORE_RET - DC Characteristics .............................................................................. 74 Table 30: LDO_VBAT - Recommended Operating Conditions ........................................................... 74 Table 31: LDO_VBAT - DC Characteristics ........................................................................................ 75 Table 32: LDO_1V8P - Recommended Operating Conditions ............................................................ 75 Table 33: LDO_1V8P - DC Characteristics ......................................................................................... 75 Table 34: LDO_1V8P - AC Characteristics ......................................................................................... 76 Table 35: LDO_USB - Recommended Operating Conditions ............................................................. 76 Table 36: LDO_USB - DC Characteristics .......................................................................................... 76 Table 37: LDO_VBAT_RET - Recommended Operating Conditions .................................................. 76 Table 38: LDO_VBAT_RET - DC Characteristics ............................................................................... 76 Table 39: BG_REF - DC Characteristics ............................................................................................. 77 Table 40: OSC_XTAL32K - Recommended Operating Conditions .................................................... 77 Table 41: OSC_XTAL32K - DC Characteristics .................................................................................. 78 Table 42: OSC_XTAL32K - Timing Characteristics ............................................................................ 78 Table 43: OSC_XTAL32M - Recommended Operating Conditions .................................................... 78 Table 44: OSC_RCX - Timing Characteristics .................................................................................... 79 Table 45: OSC_RC32MEG - Timing Characteristics .......................................................................... 79 Table 46: PLL_SYS - DC Characteristics ............................................................................................ 79
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DA1469x
Multi-core BLE 5.1 SoC family with system PMU
Datasheet Revision 2.0 21-Feb-2019
CFR0011-120-00 16 of 733 © 2019 Dialog Semiconductor
Table 47: PLL_SYS - Timing Characteristics ...................................................................................... 79 Table 48: Charger - DC Characteristics .............................................................................................. 79 Table 49: USB_CHRG_DET - DC Characteristics .............................................................................. 82 Table 50: BATCHECK - DC Characteristics ........................................................................................ 83 Table 51: GPIO - DC Characteristics .................................................................................................. 83 Table 52: GPIO_LOWDRV - DC Characteristics ................................................................................ 84 Table 53: QSPIF - DC Characteristics ................................................................................................ 84 Table 54: QSPIR - DC Characteristics ................................................................................................ 85 Table 55: LED_DRIVER - DC Characteristics..................................................................................... 85 Table 56: LED_DRIVER - AC Characteristics ..................................................................................... 86 Table 57: LRA - Recommended Operating Conditions ....................................................................... 86 Table 58: LRA - AC Characteristics .................................................................................................... 86 Table 59: GPIO_USB - DC Characteristics ......................................................................................... 86 Table 60: Radio BLE 1M - Recommended Operating Conditions....................................................... 86 Table 61: Radio BLE 1M - DC Characteristics .................................................................................... 87 Table 62: Radio BLE 1M - AC Characteristics .................................................................................... 88 Table 63: Radio BLE 2M - Recommended Operating Conditions....................................................... 90 Table 64: Radio BLE 2M - DC Characteristics .................................................................................... 90 Table 65: Radio BLE 2M - AC Characteristics .................................................................................... 91 Table 66: Power Domains Description ................................................................................................ 96 Table 67: Wake Up Modes .................................................................................................................. 98 Table 68: Power Rails Configuration ................................................................................................. 102 Table 69: OTP Layout ....................................................................................................................... 105 Table 70: Configuration Script Commands and Description ............................................................. 105 Table 71: Configuration Script example ............................................................................................ 106 Table 72: Memory Map ...................................................................................................................... 112 Table 73: Busy Status Register ......................................................................................................... 115 Table 74: Remapping Options ........................................................................................................... 115 Table 75: Security Configuration Options ..................................................