mulldonoch 3 user manual issue 2 - mouser.com

© Enterpoint Ltd. – Mulldonoch 3 Manual – Issue 2.0 11/12/15 1

Mulldonoch 3 User Manual

Issue – 2.0


Kit Contents

You should receive the following items with your Mulldonoch 3 development kit:

1 – Mulldonoch 3 Board

2 – Programming adapter

You will also need a programming cable – either Enterpoint's PROG4 cable or an Altera USB

Blaster (or equivalent).

Foreword

PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN

OR POWERING UP YOUR MULLDONOCH 3 BOARD.

PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN

THIS MANUAL.

Trademarks

Cyclone-V, Altera, Quartus II and QSys are the registered trademarks of Altera Corporation, San

Jose, California, US.

Mulldonoch 3 is a trademark of Enterpoint Ltd.


Contents Kit Contents 2

Foreword 2

Trademarks 2

Mulldonoch 3 4

Introduction 5

Mulldonoch 3 FEATURES 6

FPGA 7

BATTERY BACKUP 7

SPI FLASH 8

DDR3 9

LEDS 11

SWITCHES 12

ETHERNET CONTROLLER 13

USB 15

USER IO 19

OPTOISOLATED IO 21

MEMORY CARD HOLDER 23

CLOCK GENERATOR 24

PCIE SWITCH 26

PCIE CONNECTOR 28

MINI PCIE SOCKETS 29

EXPANSION CONNECTOR 30

CAN TRANSCEIVERS 31

DISPLAYPORT INTERFACE 32

RS232 INTERFACE 34

REAL TIME CLOCK 35

FRONT PANEL CONNECTOR 35

POWER CONNECTIONS 36

THERMAL MANAGEMENT 37

POWER REGULATORS 38

CONFIGURING Mulldonoch 3 40

MECHANICAL 45

Medical and Safety Critical Use 46

Warranty 46

Support 46


MULLDONOCH 3

Mulldonoch 3


Introduction Welcome to your Mulldonoch 3 board. Mulldonoch 3 is an FPGA development board in a Mini-

ITX format based on the Altera Cyclone™ V SOC. Mulldonoch 3 aims to do all the normal things

you expect of a motherboard, with a baseline of a dual core ARM® Cortex™-A9 processor, the

Linux™ operating system, and a fast bring up of your basic system. An Altera® SOC couples the

dual A9 cores with programmable hardware acceleration of heavyweight software routines and

algorithms allowing this SOC based motherboard to boost performance by up to X10 that of

competing conventional motherboards and processors.

The advantages of Mulldonoch 3 do not end there. Using ultra-high speed PCI Express® links as an

interconnect Mulldonoch 3 offers an extensive expansion capability with standard Mini-PCIe® card

sockets and a standard X4 PCI Express® socket.

A further high bandwidth custom expansion interface supports Enterpoint off the shelf and full

custom mezzanine boards for those unusual applications where standard expansion cards don’t meet

requirements. More mundanely the product can sup-port human interface and industrial control

panels through simple GPIO, opto-isolated GPIO and internal USB3 features.

Mulldonoch 3 is a good solution for many industrial applications even on its own. However,

Mulldonoch 3 offers a wide range of expansion options to provide extra processing or I/O

capabilities via conventional expansion sockets and further custom options.

The first expansion option is the X4 PCI Express® socket which can take a conventional PCIe®

card for low cost standard card add-ons or advanced options like Enterpoint’s Raggedstone 3 FPGA

board.

The second expansion option uses the available Mini-PCIe® sockets to host industry standard Mini-

PCIe® cards. These cards can offer an extensive range of options including graphics, SATA, SSD,

RS232 and Ethernet. When standard cards don’t meet requirements, Enterpoint’s mezzanine add-

ons can solve the problem. We will be offering a range of off the shelf and full custom mezzanines

to accompany Mulldonoch 3. Enterpoint can offer a fast turn design and manufacture service for

your custom mezzanine requirements.

The Mulldonoch 3 design allows it to be a system development board but its versatility does not

stop there. Without the pain of porting software and FPGA fabric designs your Mulldonoch 3

development platform can seamlessly transform into being your long term system motherboard. Its

Mini-ITX board format allows it to be used with a wide range of low cost standard cases for the

desktop, rack, or vehicle applications and Enterpoint can also offer customised Bill of Materials and

PCB options for customers with annual volume needs as low as 10 or as high as 1 million. Please

contact us on [email protected] should you need further information.

The aim of this manual is to assist in using the main features of Mulldonoch 3.

There are features that are beyond the scope of the manual. Should you need to use these features

then please email [email protected] for detailed instructions.

Mulldonoch 3 is currently fitted with a 5CSXF6C6C6U23C8N Cyclone™ V device. Other variants

may be offered at a later date or as an OEM product.

mailto:[email protected]



Mulldonoch 3 Features

Your Mulldonoch 3 will be supplied un-programmed. Unless you have bought an OEM product

your board will be supplied with a Prog4 USB port programming cable.

The Cyclone™ V FPGA on the standard Mulldonoch 3 board is not supported by the free version of

Quartus™ II tools. You will need the full version, 13 or later, of the tools to enter and build a

design. Using these tools in conjunction with your programming cable you will be able to program

the Cyclone™ V and the supporting SPI Flash on Mulldonoch 3.

DisplayPort

connector

128Mb SPI

Quad Flash

User

memory DDR3

Expansion/

mezzanine

interface

2 Mini PCIe

sockets

6 USB3 Ports FT232R

RS232/USB

slave

interface

PCIE X4

Interface

CYCLONE™ V

SOC

2 x 10/10/1000

Ethernet

GPIO SDCARD

Holder on

back of

board

3 USB2 Ports


FPGA

Mulldonoch 3 has one Cyclone™ V SOC FPGA- 5CSXF6C6C6U23C8N (672pins) which contains

110K LE of Programmable Logic.

Mulldonoch 3 is normally available with commercial grade C8 speed devices fitted. Should you

have an application that needs different size FPGAs, industrial parts or faster speed grades please

contact sales for a quote at [email protected].

Battery backup The Mulldonoch 3 has a battery holder to provide battery backup to the Cyclone™ V FPGA. It is

connected to the FPGA on pin D7. It also supplies power to the Real Time Clock device. The

battery holder accepts a 3V Lithium battery size CR1220/1225 or equivalent.

A 2mm jumper must be fitted to the 3-pin header J29 to allow the Cyclone™ V to exit reset. If the

battery is fitted the jumper must link pins 1 and 2. If it is not fitted the jumper must link pins 2 and

3.

Cyclone™-V FPGA

Battery Holder on

back of board

J29

Pin 1

Pin 3



SPI FLASH MEMORY

There are three 256Mbit Micron N25Q256A13EF840E SPI flash memory devices fitted to

Mulldonoch 3. Two are connected to the Cyclone™ V HPS (U17 and U25) and have common data

and clock connections and individual chip-select signals. The primary purpose of these devices is to

store boot code for the HPS and/or configuration data for the FPGA. Any remaining space can be

used for alternative configurations or code and data storage.

The SPI Flash devices can be accessed via the following pins of the Cyclone™ V HPS:

FUNCTION HPS PIN SIGNAL NAME SPI FLASH PIN

CCLK C14 QUAD1 6

CS (U17) A6 QUAD2 1

CS (U25) B14 QUAD7 1

MISO0/D A8 QUAD3 5

MISO1/Q H16 QUAD4 2

MISO2/WP A7 QUAD5 3

MISO3/HOLD J16 QUAD6 7

The third SPI flash memory device (U43) is connected to the Cyclone™ V FPGA and is intended

for FPGA configuration data. The bitstream size for the Cyclone™ V FPGA is 56,057,408bits, so

the remaining space can be used for alternative configurations or code and data storage.

FUNCTION FPGA PIN SIGNAL NAME SPI FLASH PIN

CCLK AA8 QUAD1 6

CS (U43) AA6 QUAD2 1

MISO0/D AD7 QUAD3 5

MISO1/Q AC6 QUAD4 2

MISO2/WP AC5 QUAD5 3

MISO3/HOLD AB6 QUAD6 7

U43

U25

U17


DDR3

Mulldonoch 3 has two Micron MT41J256M16 4GBit DDR3 devices arranged as a single 32 bit

wide 1GByte interface. This arrangement of DDR3 is supported by the hard core memory controller

that is in the Cyclone™ V FPGA. To add this core to your design the DDR3 ALTMEMPHY

megafunction, part of the Quartus II™ suite, will generate implementation templates in VHDL or

Verilog for this configuration. More details on the memory controller can be found in the user guide

available from www.altera.com.

The DDR3 module has 16 address lines and 32 data lines to address all the available memory,

which can be accessed at speeds down to 1.87ns. The DDR3 has the following connections to the

FPGA:

DDR3

FUNCTION

Cyclone™ V

FPGA PIN

DDR3

FUNCTION

Cyclone™ V

FPGA PIN

A0 C28 DQ5 K26

A1 B28 DQ6 G27

A2 E26 DQ7 F28

A3 D26 DQ8 K25

A4 J21 DQ9 L25

A5 J20 DQ10 J27

A6 C26 DQ11 J28

A7 B26 DQ12 M27

A8 F26 DQ13 M26

A9 F25 DQ14 M28

A10 A24 DQ15 N28

DDR3

http://www.altera.com/


A11 B24

DQ16 N24

A12 D24 DQ17 N25

A13 C24 DQ18 T28

A14 G23 DQ19 U28

A15 N.C. DQ20 N26

BA0 A27 DQ21 N27

BA1 H25 DQ22 R27

BA2 G25 DQ23 V27

CAS# A26 DQ24 R26

CK N21 DQ25 R25

CK# N20 DQ26 AA28

WE# E25 DQ27 W26

ODT0 D28 DQ28 R24

CKE0 L28 DQ29 T24

RAS# A25 DQ30 Y27

CS0# L21 DQ31 AA27

RST# V28 DQS0 R17

DM0 G28 DQS0# R16

DM1 P28 DQS1 R19

DM2 W28 DQS1# R18

DM3 AB28 DQS2 T19

DQ0 J25 DQS2# T18

DQ1 J24 DQS3 U19

DQ2 E28 DQS3# T20

DQ3 D27 RZQ D25

DQ4 J26

The signals shown shaded in yellow are terminated using suitable arrangements of resistors.


LEDS

Mulldonoch 3 has 4 LEDs, one each of Red, Yellow, Blue and Green. The relevant IO pin for an

LED needs to be asserted HIGH to ensure the specified LED turns on. It may be necessary to assign

the pins to 'Z' (High Impedance) in order for the LEDs to be completely 'off'. The table below

shows the connections between the Array FPGAs and the LEDs.

DESIGNATOR COLOUR FPGA PIN

L1 RED *

L2 GREEN AF23

L3 BLUE W12**

L4 YELLOW AF21

*The red LED is a power indicator. It is routed to pin 2 of J11 so that a power indicator can be

implemented on the outside of an enclosure (see section entitled 'Front Panel Connector'. The

standard ITX format of Mulldonoch 3 makes this straightforward to achieve.

**The green LED is also routed to pin 1 of J11 so that a user LED can be implemented on the

outside of an enclosure.

L4 L3 L1 L2


SWITCHES

Mulldonoch 3 has 1 push-button switch and 2 4-bit DIL switches.

Switches 2 and 3 are 4-bit DIP switches. Element 1 is on the right and element 4 is on the left. They

are connected to the Cyclone™ V HPS as shown below, with signal names shown in parentheses:

SWITCH2 SWITCH3

ELEMENT1 R28(USER_SW0) AG8(USER_SW4)

ELEMENT2 P26(USER_SW1) AG9(USER_SW5)

ELEMENT3 T17 (USER_SW2) W14(USER_SW6)*

ELEMENT4 T16(USER_SW3) AF18(MSEL0)**

*USER_SW6 connects to the FPGA fabric.

**MSEL is used to set the speed of the serial configuration for the FPGA. Fast = 0 (switch ON),

slow = 1 (switch OFF)

Switch 1 is a push button switch which connects to the Cyclone™ V on pin A23 via a controller

device and is specifically used to reset the HPS processor.

SWITCH1

SWITCH2

SWITCH3


ETHERNET CONTROLLERS

Mulldonoch 3 has two Micrel KSZ9021RL 10/100/1000Mbps Ethernet PHYs fitted with RJ45

Magnetically isolated sockets. For further information and the component datasheet please refer to

www.micrel.com. The connections between the KSZ9021RL devices and the Cyclone™ V are

shown in the table below. One Ethernet interface (ETH1, PORT1) connects to the HPS side of the

Cyclone™ V. The second Ethernet interface (ETH2, PORT2) connects to the FPGA fabric of the

Cyclone™ V. The KSZ9021RL supports RGMII Ethernet signalling.

FUNCTION(SIGNAL NAME)

KSZ9021RL PIN

PORT1 PORT2

Cyclone™ V PIN Cyclone™ V PIN

ETH_RX0 42 A14 AF25

ETH_RX1 41 A11 AA19

ETH_RX2 38 C15 AG23

ETH_RX3 36 A9 AF27

ETH_TX0 24 A16 AG24

ETH_TX1 25 J14 AH24

ETH_TX2 26 A15 AG25

ETH_TX3 27 D17 AH23

ETH_TX_CTL 33 A12 AF28

Ethernet controller RJ45 Magnetically isolated

Ethernet sockets PORT2 PORT1

http://www.micrel.com/


ETH_TX_CLK 32* J15 AH21

ETH_RX_CTL 43 J13 AH22

ETH_RX_CLK 46* J12 AG21

ETH_MDC 48 A13 AA18

ETH_MDIO 49 E16 AF22

*via series 22ohm resistors


USB

There are three separate USB interfaces on Mulldonoch 3.

Side view of Mulldonoch 3

MINI-B USB

CONNECTOR

U67

USB PORT9

USB PORT7 USB PORT2

USB PORT3

USB PORT1

USB PORT4

U53

U39

U42

U63

U64

USB PORT8

USB PORT6

USB PORT5


1. USB3

The primary USB capability on Mulldonoch 3 is a USB3 host interface with 6 ports. This is

achieved using two TI TUSB7340RKMR devices (U39 and U53). For further information and the

device datasheet please refer to www.ti.com.

The USB3 transmit and receive capability is derived from two of the eight output groups of the

PEX8615BA50BCG PCIE switch U48, which is fed from 4 fast transceiver lanes of the Cyclone™

V. The Clock signals are derived from

The connections between the PCIE switch and U39 and U53 are shown below:

SIGNAL NAME PCIE SWITCH PIN USB DEVICE DEVICE PIN

PCIE_P12_L6_TX_P

PCIE_P12_L6_TX_N

PCIE_P12_L6_RX_P

PCIE_P12_L6_RX_N

CLOCK6_P

CLOCK6_N

PCIE_P14_L7_TX_P

PCIE_P14_L7_TX_N

PCIE_P14_L7_RX_P

PCIE_P14_L7_RX_N

CLOCK7_P

CLOCK7_N

The USB sockets corresponding to ports 1 to 6 shown in the figure above connect to the USB

devices shown below:

USB

CONNECTOR

USB

DEVICE

DEVICE

PORT

USB DEVICE PINS

USB PORT1 U39 1 B15*, A17*, B16, A18, A20*, B18*

USB PORT2 U39 2 B10*, A11*, A10, B9, B12*, A13*

USB PORT3 U39 3 A30*, B28*, A29, B27, B25*, A27*

USB PORT4 U39 4 A8*, B7*, A7, B6, B5*, A5*

USB PORT5 U53 1 B15*, A17*, B16, A18, A20*, B18*

USB PORT6 U53 2 B10*, A11*, A10, B9, B12*, A13*

*via external components

Access to the JTAG connections for these devices can be achieved using the test points provided.

http://www.ti.com/


The second USB interface on the Mulldonoch 3 is a 3-port USB2 interface, which uses a USB3300

phy (U42) and two USB 2541 hubs (U63 and U64). Port 4 of USB hub U63 connects to USB hub

U64, which connects (via filters) to USB Ports 7, 8 and 9 as shown below:

USB CONNECTOR USB DEVICE DEVICE PORT USB DEVICE PINS

USB PORT7 U64 2 3,4

USB PORT8 U64 3 6,7

USB PORT9 U64 4 8,9

The third USB interface on the Mulldonoch 3 is a slave interface which uses an FT232R USB

(U67) to serial UART interface. The datasheet and drivers for this device are available from

http://www.ftdichip.com. When appropriate drivers are installed the Mulldonoch 3 USB port should

be detected as a serial port. Data optimised drivers are available from FTDI.

The TXD and RXD signals from the FT232R are connected to one of the possible UARTs of the

Cyclone™ V. The five CBUS signals are routed to Cyclone™ V FPGA pins. These connections are

shown below:

SIGNAL NAME Cyclone™ V PIN FT232R PIN

FT232_TXD B16 30

FT232_RXD C19 2

CBUS0 D8 22

CBUS1 E8 21

CBUS2 D12 10

CBUS3 E11 11

CBUS4 D11 9

U39

TDI TDO TCK TMS TDI TDO TCK TMS


USER IO

Mulldonoch 3 has two connectors with a total of 48 GPIO (connected to FPGA pins) available for

the user's own circuitry. 20 GPIO are routed to the 40-way 0.1inch pitch IDC header J17. The

remaining 28 are routed to the expansion connector J31, which is a Samtec HSEC8-160-l-L-DV-A,

2x60 way 0.8mm pitch connector. This expansion connector is primarily aimed at connecting with a

custom mezzanine board which a customer may wish to use in conjunction with Mulldonoch 3

(subject to the limitations of the 3.3V power and the FPGA IO pin driving capabilities). The

maximum voltage of a signal on these IO is 3.3V. DO NOT connect a signal with a higher

voltage than this or you risk damaging the Cyclone™ V FPGA.

The IO are routed as LVDS pairs:

SIGNAL FPGA PIN J17 J31 SIGNAL FPGA PIN J17 J31

GPIO_0 AG11(DIFFIO_TX_B48p) 1 GPIO_25 AF28(DIFFIO_TX_B80n) 81

GPIO_1 AH11(DIFFIO_TX_B48n) 2 GPIO_26 AA19(DIFFIO_TX_B59p) 85

GPIO_2 AG13(DIFFIO_TX_B42p) 3 GPIO_27 AA18(DIFFIO_TX_B59n) 87

GPIO_3 AF13(DIFFIO_TX_B42n) 4 GPIO_28 AC22(DIFFIO_TX_B75p) 91

GPIO_4 AG14(DIFFIO_TX_B52p) 5 GPIO_29 AC23(DIFFIO_TX_B75n) 93

GPIO_5 AH13(DIFFIO_TX_B52n) 6 GPIO_30 AH23(DIFFIO_TX_B69p) 97

GPIO_6 W14(DIFFIO_TX_B51p) 7 GPIO_31 AH22(DIFFIO_TX_B69n) 99

GPIO_7 V13(DIFFIO_TX_B51n) 8 GPIO_32 V16(DIFFIO_TX_R8p) 103

GPIO_8 U14(DIFFIO_TX_B43p) 9 GPIO_33 V15(DIFFIO_TX_R8n) 105

GPIO_9 U13(DIFFIO_TX_B43n) 10 GPIO_34 AG24(DIFFIO_TX_B72p) 109

GPIO_10 AF15(DIFFIO_TX_B46p) 11 GPIO_35 AH24(DIFFIO_TX_B72n) 111

GPIO_11 AE15(DIFFIO_TX_B46n) 12 GPIO_36 Y15(DIFFIO_TX_B55p) 115

J17

J31


GPIO_12 AG18(DIFFIO_TX_B60p) 13 GPIO_37 AA15(DIFFIO_TX_B55n) 117

GPIO_13 AH18(DIFFIO_TX_B60n) 14 GPIO_38 AE24(DIFFIO_TX_B74p) 68

GPIO_14 AH17(DIFFIO_TX_B56p) 15 GPIO_39 AE23(DIFFIO_TX_B74n) 70

GPIO_15 AH16(DIFFIO_TX_B56n) 16 GPIO_40 AF25(DIFFIO_TX_B78p) 74

GPIO_16 AD17(DIFFIO_TX_B54p) 17 GPIO_41 AG25(DIFFIO_TX_B78n) 76

GPIO_17 AE17(DIFFIO_TX_B54n) 18 GPIO_42 NOT CONNECTED

GPIO_18 AG10(DIFFIO_TX_B45p) 19 GPIO_43 NOT CONNECTED

GPIO_19 AH9(DIFFIO_TX_B45n) 20 GPIO_44 AB26(DIFFIO_TX_R22p) 86

GPIO_20 AG23(DIFFIO_TX_B70p) 67 GPIO_45 AA26(DIFFIO_TX_R22n) 88

GPIO_21 AF23(DIFFIO_TX_B70n) 69 GPIO_46 AD23(DIFFIO_TX_B67p) 92

GPIO_22 AE20(DIFFIO_TX_B62p) 73 GPIO_47 AE22(DIFFIO_TX_B67n) 94

GPIO_23 AD20(DIFFIO_TX_B62n) 75 GPIO_48 Y24(DIFFIO_TX_R23p) 100

GPIO_24 AF27(DIFFIO_TX_B80p) 79 GPIO_49 W24(DIFFIO_TX_R23n) 102

LVDS termination on individual signal pairs is a programmable option that can be set in build

constraints for the FPGA when using the Quartus toolset. The LVDS pairs are shown in the table

above along with Cyclone™ V pin numbers.


OPTOISOLATED IO

Mulldonoch 3 has two quad optoisolators (U9 and U10, type Liteon LTV-846S see

http://www.us.liteon.com) for a user to connect signals of voltages up to 80V and frequency up to

80KHz. These signals are connected to the board using connectors J7 and J10 (0.1inch pitch 2x5

IDC headers type Toby 302-S-10-DIR1) and are routed through the optoisolators to Cyclone™ V

FPGA pins. A total of 8 signals can be accommodated, 4 inputs and 4 outputs. The connections

between J7, J10, the optoisolators and the FPGA are shown below:

INPUT OPTOISOLATORS

SIGNAL

NAME

J7

PIN

U10 INPUT

PIN

U10 OUTPUT

PIN

SIGNAL

NAME

FPGA PIN

OPTO1_VIN_P 3 7 10 OPTIN1 AG26

OPTO1_VIN_N 4 8

OPTO2_VIN_P 7 3 14 OPTIN2 AH21

OPTO2_VIN_N 8 4

OPTO3_VIN_P 9 1 16 OPTIN3 AG21

OPTO3_VIN_N 10 2

OPTO4_VIN_P 5 5 12 OPTIN4 AE19

OPTO4_VIN_N 6 6

J7 (Inputs)

J10 (Outputs)

http://www.us.liteon.com/


OUTPUT OPTOISOLATORS

SIGNAL NAME J10

PIN

U9 OUTPUT

PIN

U9 INPUT

PIN

SIGNAL

NAME

FPGA PIN

OPTO5_VOUT_P 4 16 1 OPTOUT1 AF21

OPTO5_VOUT_N 3 15

OPTO6_VOUT_P 10 10 7 OPTOUT2 AH26

OPTO6_VOUT_N 9 9

OPTO7_VOUT_P 6 14 3 OPTOUT3 AF22

OPTO7_VOUT_N 5 13

OPTO8_VOUT_P 8 12 5 OPTOUT4 AD19

OPTO8_VOUT_N 7 11


MEMORY CARD HOLDER

Rear view of Mulldonoch 3

The primary purpose of the SDCARD on Mulldonoch 3 is to hold the operating system (e.g. Linux)

from which the ARM processor will run. It is connected to HPS inputs of the Cyclone™ V.

Alternatively, the SDCARD can be used for data storage. To use this socket in a design you may

need to obtain a license from the SD Association at http://www.sdcard.org/home/.

The connections between the Memory Card Holder and the Cyclone™ V are shown below:

FUNCTION SIGNAL PIN

DATA 0 SDCARD2 C13

DATA 1 SDCARD1 B6

DATA 2 SDCARD3 B11

DATA 3 SDCARD4 B9

CMD SDCARD5 D14

CLK SDCARD6 B8

POWER_ON_N SDCARD7 A5

The POWER_ON_N pin must be set LOW for power to be supplied to the Memory Card Socket.

MEMORY

CARD

HOLDER

http://www.sdcard.org/home/


CLOCK GENERATOR

Mulldonoch 3 has a Texas Instruments CDCM6208 2-input, 8-output clock generator (U30) capable

of generating 8 differential clocks with typical RMS jitter of 0.265ps and frequencies 0 to 800MHz.

The clock generator's I2C control interface is connected to the HPS connections of the Cyclone™ V

FPGA. More information and a datasheet for this device can be obtained from www.ti.com.

The primary clock source for the clock generator is the Cyclone™ V FPGA. The secondary clock

source is a 25MHz ASEM oscillator. The 8 clock outputs connect to the Cyclone 5 high speed

transceivers, the Mini PCIE sockets and the USB3 controllers.

The connections between the Clock Generator and other devices are shown below:

CDCM6208 Signal Name CDCM6208 Pin Connects to:

SDA (HPS_I2C1_SDA) 2 Cyclone™ V HPS pin A21

SCL (HPS_I2C1_SCL) 5 Cyclone™ V HPS pin K18

PRI_REF_P 8 Cyclone™ V FPGA pin AG5

PRI_REF_N 9 Cyclone™ V FPGA pin AH4

CLOCK0_P 14 PCIE Switch U14 Pin U10

CLOCK0_N 15 PCIE Switch U14 Pin V10

CLOCK1_P 17 PCIE Socket J1 pin A13

CLOCK1_N 16 PCIE Socket J1 pin A14

CLOCK2_P 20 Mini PCIE Socket J21_PC1 pin A13

CLOCK2_N 21 Mini PCIE Socket J21_PC1 pin A14

CLOCK3_P 23 Mini PCIE Socket J21_PC2 pin A13

CLOCK3_N 22 Mini PCIE Socket J21_PC2 pin A14

CLOCK4_P 26 Cyclone™ V (transceiver) pin V5

CLOCK4_N 25 Cyclone™ V (transceiver) pin V4

CLOCK5_P 29 Cyclone™ V (transceiver) pin P8

CLOCK5_N 28 Cyclone™ V (transceiver) pin N8

CLOCK

GENERATOR

U30

PCIE

SOCKET J1

MINI PCIE

SOCKET

J21_PC2

MINI PCIE

SOCKET

J21_PC1

PCIE

SWITCH U14

http://www.ti.com/


CLOCK6_P 32 USB Controller U17 pin A45

CLOCK6_N 33 USB Controller U17 pin B41

CLOCK7_P 35 USB Controller U39 pin A45

CLOCK7_N 36 USB Controller U39 pin B41


PCIE SWITCH

Mulldonoch 3 has a PLX Technology PEX8615 PCIe switch which supports 12 lanes of PCIe

GEN2. For more information and the device datasheet go to www.plxtech.com. The PEX8615

connects the high speed signals and clocks required for the PCIe socket J1, the two mini PCIe

sockets J21_PC1 and J21_PC2 and the two USB3 controllers U17 and U39.

The speed of the PCIe interface (GEN1 or GEN2) can be selected using a Jumper on J30. The

jumper position shown below is for GEN2.

PEX8615

LA

NE

0

LA

NE

3

LA

NE

4

LA

NE

5

LA

NE

9

LA

NE

11

LA

NE

8

LA

NE

6

LA

NE

7

LA

NE

10

LA

NE

2

LA

NE

1

PCIE SOCKET

J1

MINI PCIE SOCKET

J21_PC1

MINI PCIE SOCKET

J21_PC2

CYCLONE 5 HIGH SPEED

TRANSCEIVERS

USB3 CONTROLLER

U17

USB3 CONTROLLER

U39

J30 – jumper shown in

GEN2 position

J28 – jumper shown in

normal position J28

J30

http://www.plxtech.com/


J28 should have a jumper fitted in the position shown above. Moving the jumper to the alternative

location will reset the PCIe switch.

Access to the JTAG connections for this device can be achieved using a 6x2x1.27mm pitch header

on the rear of the board (J29).

When viewed in the orientation shown above, the pinout is as shown below (pin 1 is top right).

2 1-2.5V

4 3-GND

6 5-TCK

8 7-TDI

10 9-TDO

12 11-TMS

J29


PCIE CONNECTOR

Mulldonoch 3 has a x4 PCIe connector J1 which is connected to the PCIE switch on lanes 8 to 11.

The ancillary connections between the PCIe connector and the Cyclone™ V FPGA are shown

below.

SIGNAL NAME PCIE CONNECTOR PIN FPGA PIN

PCIE_SK_WAKE# B11 AG15

PCIE_PRESENTx2 B17 AA13*

PCIE_PRESENTx4 B31 AA13*

PCIE_SK_PERST# A11 AH14

* also connected to 3.3V via 4.7KΩ resistors

J1


MINI PCIe SOCKETS

Mulldonoch 3 has two mini PCIE sockets, J21_PC1 and J21_PC2. These can accept a wide variety of

commercially available modules to enhance the functionality of Mulldonoch 3, subject to a maximum of

1A current available at 1.5V per socket (or 2A if only one socket is used).

Connector J12_PC1 connects to the PCIe switch on lane 4 and Connector J12_PC2 connects to the PCIe

switch on lane 5.

J21_PC1

J21_PC2


EXPANSION CONNECTOR

Mulldonoch 3 has an expansion connector, principally designed to allow one or more mezzanine

boards to be added. There are also 4 mounting holes to allow a mezzanine board to be attached.

depending on the design of your mezzanine board, some of the functionality of Mulldonoch 3 may

be lost because the connectors (e.g. for the optoisolated IO) may be mechanically unavailable.

Two of the Cyclone™ V high speed transceivers have been routed to this expansion board to allow

high speed communication between the Mulldonoch 3 and a mezzanine board. 15 pairs of GPIO

have also been routed from the Cyclone™ V to the expansion connector. These are arranged as

LVDS pairs.

The connections between the Cyclone™ V FPGA and the expansion connector are shown below.

MEZZANINE BOARD

MOUNTING HOLES (4) EXPANSION

CONNECTOR J31


SIGNAL

NAME

EXPANSION

CONNECTOR PIN

FPGA PIN SIGNAL

NAME

EXPANSION

CONNECTOR PIN

FPGA PIN

GND 1,7,13,19,25,31,37,43,

49,55,63,65,71,77,83,8

9,95,101,107,113,119

GND 2,8,14,20,26,32,38,44,5

0,56,64,66,72,78,84,90,

96,102,108,114,120

NO

CONNECT

15,17,21,23,27,29,33,3

5,39,41,45,47,51,53

NO

CONNECT

16,18,22,24,28,30,34,3

6,40,42,46,48,52,54

5V 57,59,61 12V 58,60,62

EXP_TX4_P H2 EXP_RX4_P 4 K2

EXP_TX4_N H1 EXP_RX4_N 6 K1

EXP_TX5_P 9* D2 EXP_RX5_P 10 F2

EXP_TX5_N 11* D1 EXP_RX5_N 12 F1

GPIO_20 67 AG23(DIFFIO_

TX_B70p)

GPIO_38 68 AE24(DIFFIO_T

X_B74p)

GPIO_21 69 AF23(DIFFIO_

TX_B70n)


X_B74n)

GPIO_22 73 AE20(DIFFIO_

TX_B62p)

GPIO_40 74 AF25(DIFFIO_T

X_B78p)

GPIO_23 75 AD20(DIFFIO_

TX_B62n)

GPIO_41 76 AG25(DIFFIO_T

X_B78n)


TX_B80p)

GPIO_42 80 NOT

CONNECTED


TX_B80n)

GPIO_43 82 NOT

CONNECTED

GPIO_26 85 AA19(DIFFIO_

TX_B59p)

GPIO_44 86 AB26(DIFFIO_T

X_R22p)


TX_B59n)

GPIO_45 88 AA26(DIFFIO_T

X_R22n)

GPIO_28 91 AC22(DIFFIO_

TX_B75p)

GPIO_46 92 AD23(DIFFIO_T

X_B67p)

GPIO_29 93 AC23(DIFFIO_

TX_B75n)


X_B67n)

GPIO_30 97 AH23(DIFFIO_

TX_B69p)

GPIO_48 98 Y24(DIFFIO_TX

_R23p)


TX_B69n)

GPIO_49 100 W24(DIFFIO_T

X_R23n)

GPIO_32 103 V16(DIFFIO_T

X_R8p)

GPIO_33 105 V15(DIFFIO_T

X_R8n)

GPIO_34 109 AG24(DIFFIO_

TX_B72p)


TX_B72n)

GPIO_36 115 Y15(DIFFIO_T

X_B55p)


TX_B55n)

*Note these transceiver signals are also used for the DisplayPort interface. It is not possible to use

these signals on the expansion port and the DisplayPort simultaneously.


CAN TRANSCEIVERS

Mulldonoch 3 has two CAN (Control Area Network) interfaces, which are routed to the HPS

connections of the Cyclone™ V. The CAN interface uses two TI SN65HVD232 devices (U4 AND

U6), which are routed to the Cyclone™ V and to a 2x4 2mm pitch header J14 (Samtec type THD-

04-R). In order to use the CanBus™ interface in a design it may be necessary to obtain a license.

The connections are shown in the table below:

CYCLONE 5

PIN

SIGNAL

NAME

SN65HVD3232

PIN

SIGNAL

NAME

SN65HVD3232 PIN J14 PIN

H17 CAN1_D 1(U4) CAN1_H 7(U4) 1

A17 CAN1_R 4(U4) CAN1_L 6(U4) 3

J18 CAN2_D 1(U6) CAN2_H 7(U6) 5

A20 CAN2_R 4(U6) CAN2_L 6(U6) 7

J14 pins 2,4,6 and 8 are connected to GND.

J14


DISPLAYPORT INTERFACE

Mulldonoch 3 has a DisplayPort interface (J2) which is connected to the Cyclone™ V FPGA. In

order to implement this interface you will need IP for the FPGA, available from Altera or

elsewhere. Enterpoint do not accept any responsibility for the functionality of such third party IP.

Power for the DisplayPort connector is provided by a dedicated MIC2005 regulator. The ENABLE

signal for this regulator is connected to the FPGA pin W21 (signal name Displayport3). The

FAULT# output from this regulator connects to pin W20 of the FPGA (signal name Displayport4).

The connections between the FPGA and the DisplayPort connector are listed below:

DISPLAYPORT

CONNECTOR

FUNCTION SIGNAL NAME FPGA PIN

1 ML_LANE0_P DISPLAYPORT_CH0_P* D2

3 ML_LANE0_N DISPLAYPORT_CH0_N* D1

13 CONFIG1 DISPLAYPORT1 Y17

14 CONFIG2 DISPLAYPORT2 Y18

15 AUX_CH_P DISPLAYPORT_AUX_P AA24

17 AUX_CH_N DISPLAYPORT_AUX_N AA23

18 HOT PLUG DETECT DISPLAYPORT0 AF26

REGULATOR ENABLE DISPLAYPORT3 W21

REGULATOR FAULT# DISPLAYPORT4 W20

*THESE CONNECTIONS ARE ROUTED TO THE HIGH SPEED TRANSCEIVER

OUTPUT EXP_TX5, WHICH IS ALSO ROUTED TO THE EXPANSION CONNECTOR

J31 (PINS 9 AND 11). IF YOU USE THESE TWO SIGNALS VIA THE EXPANSION

CONNECTOR THEY WILL NOT ALSO BE AVAILABLE FOR THIS DISPLAYPORT

INTERFACE.

DISPLAYPORT CONNECTOR

J2


RS232 INTERFACE

Mulldonoch 3 has an RS232 serial port (J8) which connects via a transceiver device to the

Cyclone™ V HPS. The Cyclone™ V. The RS232 transceiver on Mulldonoch 3 is the TI

MAX3232E device (U23). Further details and the device datasheet can be obtained from

www.ti.com. The connections between J8 and the Cyclone™ V are shown below:

J8 PIN SIGNAL

NAME

U23 PIN SIGNAL

NAME

U23 PIN Cyclone™ V

PIN

2 RS232_RXD 13 RS232BUS0 11 C17

7 RS232_RTS 14 RS232BUS1 10 C16

3 RS232_TXD 7 RS232BUS2 12 B19

8 RS232_CTS 8 RS232BUS3 9 A18

J8

http://www.ti.com/


REAL TIME CLOCK

Mulldonoch 3 has an NXP PCF8523TK Real Time Clock device fitted (U24), which connects to

the Cyclone™ V HPS via an I2C interface. The Real Time Clock has a battery to sustain settings

when the Mulldonoch 3 is powered down. See the section entitled “Battery Backup”. The

connections between the Real Time Clock device and the Cyclone™ V are shown below:

U23PIN SIGNAL NAME Cyclone™ V PIN

5 RTC_SDA/I2C0_SDA* A19

6 RTC_SCL/I2C0_SCL* C18

7 RTC_INT# B12

*This I2C bus is shared with the I2C control interface for the PEX8615 PCIe switch.

FRONT PANEL CONNECTOR

Mulldonoch 3 has a 2x4 2mm pitch header (J11, type Samtec THD-04-R) to enable two LEDs and

two switches to be wired to the front panel of an enclosure so that the system can be switched on

and off, reset, and monitored via LEDs.

J11 PIN SIGNAL NAME CONNECTED TO

1 LED_GR1 GREEN LED, FPGA PIN Y5*

2 LED_R1 RED LED, 3.3V SUPPLY*

5 RESET_SWITCH J34 PIN 1, Cyclone™ V PIN B18

6 POWER_SWITCH ATX CONNECTOR J4 PIN 16**

* via 470ohm series resistor.

** via 'debouncing' circuit.

J11

J34

J4


POWER CONNECTIONS Mulldonoch 3 is powered principally from the 12V supply on the ATX connector J4.

Mulldonoch 3 is protected by a 5A miniature automotive blade type fuse in series with the 12V

supply. It is also protected from surges from an ATX power supply by 100R 3W resistors on the

12V, 5V and 3.3V ATX supply rails.

Alternatively, you can power Mulldonoch 3 via the standard 2.5mm jack socket (max 5A), using a

mains adapter power supply, or via the Phoenix Contact 1757268 12A rated box header (mating

plug Phoenix Contact 1757035).

Mulldonoch 3 will operate from a power supply in the range 7V to 24V DC. This is to allow

operation from a variety of power sources including solar power, wind turbine or battery. The

current consumed will depend upon your application and the IP implemented in the FPGA, along

with any peripherals you connect to the system e.g. USB devices (keyboard, mouse etc) and

displays.

ATX POWER

CONNECTOR

FUSE


THERMAL MANAGEMENT

For many applications, particularly where a high speed or demanding design is implemented in the

Cyclone™ V device, it will be necessary to install a system of thermal management to dissipate

heat generated in the FPGA. The design of the thermal management system will depend upon the

design implemented in the FPGAs, any enclosure the customer may be using for the Mulldonoch 3

board, and the mechanical arrangement of the system into which the Mulldonoch 3 board is to

integrated.


POWER REGULATORS

Mulldonoch 3 has 15 regulators supplying 5V (2), 3.3V (2), 2.5V, 1.5V, 1.35V, 1.2V, 1V1(4), 1V

(2) and 0.675V power rails.

WARNING – REGULATORS CAN BECOME HOT IN NORMAL OPERATION ALONG

WITH THE BOARDS THERMAL RELIEF. PLEASE DO NOT TOUCH OR PLACE

HIGHLY FLAMABLE MATERIALS NEAR THESE DEVICES WHILST THE

MULLDONOCH 3 BOARD IS IN OPERATION.

1. A Fairchild MC78M05CDTX regulator supplies 5V for the control circuitry of the

MIC26950 device.

2. A Micrel MIC26950 regulator supplies 5V with a maximum current available of 12A. This

is used to supply all the MIC22700 regulators, the Expansion connector, and the bias voltage

for the USB and Cyclone 5 1.1V rails.

3. A Micrel MIC22700 regulator supplies 3.3V with a maximum current of 7A for the

Cyclone™ V, SD card holder, SPI flash, DDR power regulator TPS51200, CAN

transceiver, Ethernet devices, PCIe sockets, Clock Generator, OptoCouplers and LEDs.

7

6 1 2

3

5

8

9

4

10

11

12

13

14

15


4. A Diodes Inc. AP7173 linear regulator supplies 3.3V at a maximum current of 3A for the

UBS3 controllers.


Cyclone™ V HPS.

6. A TI TPS54240 regulator provides 1.5V with a maximum current of 2.5A for the mini PCIe

sockets.

7. A Micrel MIC22700 regulator supplies 1.35V with a maximum current of 7A for the DDR3

and to supply the 1.1V linear regulators for the USB3 controllers, Cyclone™ V and PCIE

switch VD1VA supply.


KSZ9021 Ethernet Controllers.


Cyclone™ V cores.


UBS3 controller U17.


UBS3 controller U39.


Cyclone™ V transceivers.

13. A Micrel MIC22700 regulator supplies 1V with a maximum current of 7A for the PCIe

switch main core supply.

14. A Diodes Inc. AP7173 linear regulator supplies 1V at a maximum current of 3A for the

PCIe switch secondary core supply (VD1VA).

15. A TPS51200 push-pull regulator produces up to 3A at 0.675V. This provides the reference

and termination voltage for the DDR3 SODIMM Memory and related FPGA I/O.

.


CONFIGURING MULLDONOCH 3

The JTAG connectors on Mulldonoch 3 are located as shown in the picture above. The Cyclone™

V SOC can be configured in a variety of ways. The FPGA can be configured first and then used to

boot the HPS, or the HPS can be booted and used to configure the FPGA, or the two parts of the

Cyclone™ V can be configured independently. See the Booting and Configuration section of the

Cyclone™ V SOC reference manual available from www.altera.com.

Before attempting to boot the HPS it is necessary to set some (2mm) jumpers to select the clock and

boot sources.

1. Setting the CSEL (Clock select) jumpers:

Header J24 is used to set CSEL0 and CSEL1 to select the range of the clock provided to the HPS on

the CLK1 pin.

CSEL0 CSEL1 OSC1_CLK RANGE PLL MODE

0 0 10-50MHz BYPASSED

1 0 10-12.5MHz LOCKED

0 1 12.5-25MHz LOCKED

1 1 25-50MHz LOCKED

J23 Header for

programming Cyclone 5

HPS (requires adapter)

J20 Socket for

Enterpoint PROG4

cable

J19 Socket for Altera

USB Blaster cable

J25 J24

http://www.altera.com/


The frequency of the oscillator connected to the HPS clock is 25MHz, so any setting of the

CSEL(1:0) pins except for 0,1 should be acceptable.

2. Setting the BSEL jumpers

There are three BSEL (Boot Select) inputs to the HPS.

BSEL0 BSEL1 BSEL2* BOOT DEVICE

0 0 0 RESERVED

1 0 0 FPGA (HPS TO FPGA BRIDGE)

0 1 0 1.8V NAND FLASH MEMORY

1 1 0 3.3V NAND FLASH MEMORY

0 0 1 1.8V SD/MMC FLASH MEMORY WITH EXTERNAL TRANSCEIVER

1 0 1 3.3V SD/MMC FLASH MEMORY WITH INTERNAL TRANSCEIVER

0 1 1 1.8V SPI OR QUAD SPI FLASH MEMORY

1 1 1 3.3V SPI OR QUAD SPI FLASH MEMORY

*BSEL0 is fixed at '1'. Mulldonoch 3 has no 1.8V devices.

The BSEL values are selected using 2mm jumpers on header J25:

3. JTAG CONNECTORS

There are 3 JTAG connectors on the Mulldonoch 3 board that can be used for configuring the

Cyclone™ V. J23 is used for the HPS and J19/J20 are used to configure the FPGA.

The arrangements of the signals on each of these connectors are shown below:

CSEL0

CSEL1

1 0

BSEL2

BSEL1 1 0


Pins 6,7 and 8 of J19 and pins 12 and 14 of J20 are not connected. All pins not defined above are

connected to GND.

J23 (3d model) J23 (showing signal names)

Pins 6,8,10 and 12 are not connected.

Fit the JTAG adapter as shown below:

SHOW PICTURE HERE

In order to configure the 5CSXF6C6C6U23C8N Cyclone™ V you will need Quartus II

version 13.1 or later.

TMS

TDI

TCK

TDO

3.3V

TMS

TDI

TCK

TDO

3.3V


Open the Quartus II programmer (found under the Tools Menu of Quartus II). Select your

programming cable using the Hardware Setup feature. The Enterpoint PROG4 cable is detected as

an Altera USB Blaster. Use an adapter if necessary to convert from the 10 Pin Altera connector to

the RS4 14 Pin connector. See below for correct orientation of adapter:

1. Configuring the HPS.

Mulldonoch 3 is shipped with a default configuration in the HPS which will enable the peripherals

connected to the HPS to be accessed. It is necessary to load a configuration into the HPS before the

FPGA can be configured.

If you wish to change the default configuration you will need use the Altera SoC EDS Command

shell, found in your Altera Directory:

Figure 19 Locating the Altera SoC EDS Command Shell

Open the command shell and change directory to the location of your files.

The following files will be required (your file names may differ) :

Preloader-mkpimage.bin, Uboot.bin

From the command prompt program the 2 files as follows: quartus_hps –c usb-blaster –o p –a0x00000 preloader-mkpimage.bin

You should verify the file as follows: quartus_hps –c usb-blaster –o v –a0x00000 preloader-mkpimage.bin

Program the second file as follows: quartus_hps –c usb-blaster –o p –a0x60000 uboot.bin

And verify it: quartus_hps –c usb-blaster –o v –a0x60000 uboot.bin

It should now be possible to boot the Muldonnoch3 to Linux.

2. Configuring the FPGA and the SPI Flash memory

It is necessary to configure the FPGA before the SPI flash memory device can be detected. Plug

your programming cable into the JTAG connector J20/J19. Open the Quartus II programmer, check

that your programming cable has been detected correctly, then choose Auto Detect. The screen

below should appear:


Double click the FPGA File and select your sof file. Tick the Program/Configure check box to

enable the Start Button and press Start to program the FPGA.

Once Complete (Should only take a few seconds) press the Auto Detect button.

The SPI flash device should now be shown attached to the FPGA:

Double click on the EPCQ256 File and select your programming file (.jic). Tick the box in the

'Program/Configure' column for the Flash memory. Select the icon representing the flash memory

and choose ‘Start’ to load your program into the device. A green bar in the top left of the

programmer screen shows the progress. The programming operation will take some time (at least 3

or 4 minutes).


MECHANICAL ARRANGEMENT

The Mulldonoch 3 PCB is a standard size mini-ITX PCB.

The Dimensions on the drawing below are millimetres (mm). All sizes quoted are subject to

manufacturing tolerances and should only be used as a general guide.

The PCB is 1.6mm thick. The maximum component height is 32mm above the top surface of the

board (i.e. J18 height).

J18


Medical and Safety Critical Use

Mulldonoch 3 boards are not authorised for the use in, or use in the design of, medical or other

safety critical systems without the express written person of the Board of Enterpoint. If such use is

allowed the said use will be entirely the responsibility of the user. Enterpoint Ltd will accept no

liability for any failure or defect of the Mulldonoch 3 board, or its design, when it is used in any

medical or safety critical application.

Warranty

Mulldonoch 3 comes with a 90 day return to base warranty. Do not attempt to solder connections to

the Mulldonoch 3. Enterpoint reserves the right not honour a warranty if the failure is due to

soldering or other maltreatment of the Mulldonoch 3 board.

Outside warranty Enterpoint offers a fixed price repair or replacement service. We reserve the right

not to offer this service where a Mulldonoch 3 has been maltreated or otherwise deliberately

damaged. Please contact support if you need to use this service.

Other specialised warranty programs can be offered to users of multiple Enterpoint products. Please

contact sales on [email protected] if you are interested in these types of warranty,

Support

Please check our website page for this product first before contacting support. The page is located at

https://www.enterpoint.co.uk/products/altera-soc/mulldonoch-3/. Telephone and email support is

offered during normal United Kingdom working hours (GMT or GMT + 1) 9.00am to 5.00pm.

Telephone - +44 (0) 121 288 3945

Email - [email protected]


https://www.enterpoint.co.uk/products/altera-soc/mulldonoch-3/

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Authorized Distributor

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mulldonoch 3 user manual issue 2 - mouser.com

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