msc thesis - delft university of...

Computer EngineeringMekelweg 4,

2628 CD DelftThe Netherlands

http://ce.et.tudelft.nl/

2008

MSc THESIS

Testing of Deep-Submicron Embedded Memoriesin FPGAs

Chuanyou Li

Abstract

Faculty of Electrical Engineering, Mathematics and Computer Science

CE-MS-2008-10

The fast development of memory devices, the more and more areaoccupation of memory in a chip and the strong market competitionhave increased the standards of the produced memories; memoryproducts should nowadays be more reliable than ever. The increaseddemand on reliability has, in turn, stressed the importance of failureanalysis and device testing techniques. More and more effort andthought is being dedicated to the study of testing memory deviceswith regards to new fault models, fault diagnosis and new memoryarchitectures. This thesis describes one such study as a joint projectbetween Delft University of Technology and Altera Corporation, SanJose, CA, USA. Whereby this thesis work outputs a framework ofall possible fault models together with their test patterns for SRAM.Based on this, a test program is designed for Altera to achieve highfault coverage of advanced fault models, to structurize fault diagnosisand to detect special faults involved in embedded memories in theirFPGAs (both 45nm and 65nm technology). The fault diagnosis ishighlighted and incorporates several innovative idea and algorithms.In addition, the work within Altera has validated 20 tests on realsilicon, the volume test of which expect to take place in late 2008.Consequently, the test result will be available in Quarter 1 of 2009.


THESIS

submitted in partial fulfillment of therequirements for the degree of

MASTER OF SCIENCE

in

Microelectronics

by

Chuanyou Liborn in Hubei, P.R. China

MicroelectronicsDepartment of Electrical EngineeringFaculty of Electrical Engineering, Mathematics and Computer ScienceDelft University of Technology


by Chuanyou Li

Abstract

The fast development of memory devices, the more and more area occupation of memory ina chip and the strong market competition have increased the standards of the producedmemories; memory products should nowadays be more reliable than ever. The increased

demand on reliability has, in turn, stressed the importance of failure analysis and device testingtechniques. More and more effort and thought is being dedicated to the study of testing memorydevices with regards to new fault models, fault diagnosis and new memory architectures. Thisthesis describes one such study as a joint project between Delft University of Technology andAltera Corporation, San Jose, CA, USA. Whereby this thesis work outputs a framework of allpossible fault models together with their test patterns for SRAM. Based on this, a test programis designed for Altera to achieve high fault coverage of advanced fault models, to structurize faultdiagnosis and to detect special faults involved in embedded memories in their FPGAs (both 45nmand 65nm technology). The fault diagnosis is highlighted and incorporates several innovative ideaand algorithms. In addition, the work within Altera has validated 20 tests on real silicon, thevolume test of which expect to take place in late 2008. Consequently, the test result will beavailable in Quarter 1 of 2009.

Laboratory : Computer EngineeringCodenumber : CE-MS-2008-10

Committee Members :

Advisor: Said Hamdioui, CE, TU Delft

Advisor: Zaid Al-Ars, CE, TU Delft

Chairperson: C.I.M. Beenakker, ECTM, TU Delft

Member: Georgi Nedeltchev Gaydadjiev, CE, TU Delft

Member: Nick van der Meijs, CAS, TU Delft

i

For memory

iii

Contents

List of Figures x

List of Tables xii

1 Introduction 11.1 Memory testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Importance of memory testing . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1 Importance of testing . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.2 Importance of memory . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Contribution of this thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3.1 Challenges in memory testing . . . . . . . . . . . . . . . . . . . . . 61.3.2 Contributions of this thesis . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Outline of this thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 SRAM structure 92.1 Bistable structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.2 Functional structure of SRAM . . . . . . . . . . . . . . . . . . . . . . . . 132.3 Electrical circuitry of SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.1 The circuitry of an SRAM cell . . . . . . . . . . . . . . . . . . . . 162.3.2 The reading process . . . . . . . . . . . . . . . . . . . . . . . . . . 172.3.3 Precharge of BLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.4 Connection of BLs and the cell . . . . . . . . . . . . . . . . . . . . 182.3.5 Bit line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.6 Sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.3.7 Data output latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.3.8 Writing process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.3.9 Data input latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.3.10 Write driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.3.11 Write into the cell . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.3.12 Address decoding circuitry . . . . . . . . . . . . . . . . . . . . . . 23

2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 Memory fault models 273.1 Definition of fault primitive and fault model . . . . . . . . . . . . . . . . . 283.2 Classification of fault primitives . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.1 Static versus dynamic faults . . . . . . . . . . . . . . . . . . . . . . 293.2.2 Simple versus linked faults . . . . . . . . . . . . . . . . . . . . . . . 303.2.3 Single-cell versus multi-cell faults . . . . . . . . . . . . . . . . . . . 313.2.4 Single-port versus multi-port faults . . . . . . . . . . . . . . . . . . 31

v

3.3 Reduced functional memory model . . . . . . . . . . . . . . . . . . . . . . 323.4 Memory cell array faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4.1 Static faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.2 Dynamic faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.5 Address decoder faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.5.1 Static address decoder faults . . . . . . . . . . . . . . . . . . . . . 433.5.2 Dynamic address decoder faults . . . . . . . . . . . . . . . . . . . . 45

3.6 Peripheral circuit faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.6.1 Static peripheral circuit faults . . . . . . . . . . . . . . . . . . . . . 463.6.2 Dynamic peripheral circuit faults . . . . . . . . . . . . . . . . . . . 46

3.7 Faults related to memory architecture . . . . . . . . . . . . . . . . . . . . 473.7.1 Word-oriented memory(WOM) faults . . . . . . . . . . . . . . . . 473.7.2 Bit/Byte-write-enable faults . . . . . . . . . . . . . . . . . . . . . . 48

3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4 Test Primitive Generation 534.1 Concept of Test Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.1.1 March test notation . . . . . . . . . . . . . . . . . . . . . . . . . . 544.1.2 Philosophy of TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.1.3 Importance and Purpose of TP . . . . . . . . . . . . . . . . . . . . 59

4.2 Test primitive generation procedure . . . . . . . . . . . . . . . . . . . . . 604.2.1 Create TP for each targeted FP . . . . . . . . . . . . . . . . . . . 604.2.2 Create FPs×TPs table with fail/pass information . . . . . . . . . . 614.2.3 Perform faults classification . . . . . . . . . . . . . . . . . . . . . . 624.2.4 Optimize the table into the terminal dictionary . . . . . . . . . . . 63

4.3 Test primitives for single-cell static faults . . . . . . . . . . . . . . . . . . 644.4 Test primitives for single-cell dynamic faults . . . . . . . . . . . . . . . . . 65

4.4.1 Original TPs for single-cell dynamic faults . . . . . . . . . . . . . . 654.4.2 Concept of combined TP . . . . . . . . . . . . . . . . . . . . . . . 654.4.3 Modified TPs for single-cell dynamic faults . . . . . . . . . . . . . 66

4.5 Diagnostic dictionary for single-cell faults . . . . . . . . . . . . . . . . . . 674.5.1 Create FPs×TPs table with fail/pass information . . . . . . . . . . 684.5.2 FPs classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.5.3 Table Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5 Advanced Memory test solutions 735.1 Overview of targeted faults . . . . . . . . . . . . . . . . . . . . . . . . . . 745.2 Stress combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.3 Tests for memory cell array faults . . . . . . . . . . . . . . . . . . . . . . . 75

5.3.1 Test for static MCAFs . . . . . . . . . . . . . . . . . . . . . . . . . 765.3.2 Test for dynamic MCAFs . . . . . . . . . . . . . . . . . . . . . . . 76

5.4 Test for address decoder faults . . . . . . . . . . . . . . . . . . . . . . . . 775.4.1 Test for sADFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.4.2 Test for dADFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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5.5 Tests for Peripheral Circuits Faults . . . . . . . . . . . . . . . . . . . . . . 785.5.1 Tests for sPCFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.5.2 Tests for dPCFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.6 Tests for memory architecture faults . . . . . . . . . . . . . . . . . . . . . 795.6.1 Tests for Word-oriented memory (WOM) faults . . . . . . . . . . . 795.6.2 Tests for Bit/Byte Write Enable (BWE) Faults . . . . . . . . . . . 81

5.7 Test for faults within dynamic address decoders . . . . . . . . . . . . . . . 815.7.1 Dynamic address decoder . . . . . . . . . . . . . . . . . . . . . . . 825.7.2 Address transition and addressing method . . . . . . . . . . . . . . 845.7.3 March test operations . . . . . . . . . . . . . . . . . . . . . . . . . 885.7.4 Address generating circuitry of the BIST . . . . . . . . . . . . . . 91

5.8 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6 Setup of memory test program 956.1 TP-based tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966.2 Advanced tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.2.1 Tests for dynamic faults . . . . . . . . . . . . . . . . . . . . . . . . 976.2.2 Tests for memory architecture faults . . . . . . . . . . . . . . . . . 996.2.3 Tests for two-port faults (2PFs) . . . . . . . . . . . . . . . . . . . . 100

6.3 Special tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7 Work in Altera 1077.1 Plan of the JDP with Altera . . . . . . . . . . . . . . . . . . . . . . . . . . 1087.2 Test implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087.3 Additional achievements of the JDP . . . . . . . . . . . . . . . . . . . . . 1097.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

8 Conclusion and recommendations 115

Bibliography 123

Appendices 123

vii

List of Figures

1.1 General classification of semiconductor memory . . . . . . . . . . . . . . . 21.2 Influence of test quality on total cost of produced ICs . . . . . . . . . . . 51.3 The future of embedded memory . . . . . . . . . . . . . . . . . . . . . . . 51.4 Memory sizes versus yield . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 An inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.2 A bistable structure in SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 112.3 The I/O characteristic of the left inverter . . . . . . . . . . . . . . . . . . 122.4 The inner I/O characteristic of a bistable structure . . . . . . . . . . . . . 122.5 The mechanism of the bistable structure . . . . . . . . . . . . . . . . . . . 132.6 The black box diagram of an SRAM . . . . . . . . . . . . . . . . . . . . . 142.7 The functional diagram of an SRAM . . . . . . . . . . . . . . . . . . . . . 152.8 The 6T SRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.9 The read path of an SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 172.10 A precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.11 The memory cell under external force when read . . . . . . . . . . . . . . 192.12 Bit line multiplexer where BL(1) is selected . . . . . . . . . . . . . . . . . 192.13 An opamp sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.14 Data output latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.15 Write path of SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.16 Data input latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.17 Write driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.18 The memory cell under external force when written . . . . . . . . . . . . . 232.19 A row decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 Summary of fault primitive classification . . . . . . . . . . . . . . . . . . . 303.2 The reduced functional memory model . . . . . . . . . . . . . . . . . . . . 323.3 The coupling faults(CFs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.4 Static address decoder faults . . . . . . . . . . . . . . . . . . . . . . . . . 443.5 Combinations of static address decoder faults . . . . . . . . . . . . . . . . 443.6 Activation and deactivation delay faults . . . . . . . . . . . . . . . . . . . 463.7 Typical bit write enable circuitry . . . . . . . . . . . . . . . . . . . . . . . 49

4.1 Tree graph of equation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.2 Tree graph of equation 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.1 Overview of targeted faults . . . . . . . . . . . . . . . . . . . . . . . . . . 745.2 The three common address sequences . . . . . . . . . . . . . . . . . . . . . 755.3 The common data-backgrounds . . . . . . . . . . . . . . . . . . . . . . . . 765.4 Definition of Test BWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.5 A static address decoder circuitry on transistor level . . . . . . . . . . . . 835.6 A dynamic address decoder circuitry on transistor level . . . . . . . . . . 835.7 Intergate resistive open in a dynamic address decoder . . . . . . . . . . . 84

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5.8 Intragate resistive open in a dynamic address decoder . . . . . . . . . . . 865.9 Address generating circuitry in the BIST . . . . . . . . . . . . . . . . . . 915.10 Final address generating circuitry in the BIST . . . . . . . . . . . . . . . 93

6.1 Test BWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

x

List of Tables

3.1 The complete set of 1PF1 FPs . . . . . . . . . . . . . . . . . . . . . . . . 343.2 The complete set of CFs FPs; x ∈ {0, 1} . . . . . . . . . . . . . . . . . . . 373.3 The complete set of single-cell dynamic FPs . . . . . . . . . . . . . . . . . 39

4.1 TPs for FPs of Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.2 FPs versus TPs with pass/fail information . . . . . . . . . . . . . . . . . . 624.3 FPs versus TPs after faults classification . . . . . . . . . . . . . . . . . . . 624.4 Table of classified FPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.5 Terminal dictionary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.6 The TPs targeting single-cell static FPs . . . . . . . . . . . . . . . . . . . 644.7 FPs versus TPs with fail/pass information of single-cell static faults . . . 644.8 Classified single-cell static FPs . . . . . . . . . . . . . . . . . . . . . . . . 654.9 Terminal dictionary for single-cell static FPs . . . . . . . . . . . . . . . . 654.10 Original TPs for single-cell dynamic FPs . . . . . . . . . . . . . . . . . . . 664.11 Modified TPs including CTPs for single-cell dynamic FPs . . . . . . . . . 674.12 Arabian numbers denotation of TPs . . . . . . . . . . . . . . . . . . . . . 684.13 FPs versus TPs with fail/pass information of all single-cell faults . . . . . 694.14 Classified single-cell FPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.15 Terminal dictionary for single-cell FPs . . . . . . . . . . . . . . . . . . . . 71

5.1 March MSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2 March MRAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.3 Tests for dADFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.4 Test set for dPCFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795.5 The DBs and OSs for intra-word static faults . . . . . . . . . . . . . . . . 805.6 Address transitions sensitizing all dADFs . . . . . . . . . . . . . . . . . . 875.7 Addressing method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875.8 Addressing method for n-bit dynamic address decoders . . . . . . . . . . . 885.9 Tests for dADFs in dynamic address decoders . . . . . . . . . . . . . . . . 895.10 Initial states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925.11 States of A, B and address lines as clock changes . . . . . . . . . . . . . . 92

6.1 TPs for single-cell static and 2-operation dynamic MCAFs . . . . . . . . . 966.2 March MRAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.3 March AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.4 March BLIWD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986.5 March SAPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986.6 March SAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996.7 March SZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996.8 March s2PF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016.9 March d2PF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016.10 Gal9R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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6.11 Gal9RW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.12 HammerWRh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.13 HammerWhRh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.14 March DRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046.15 ConDRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046.16 Summary of all tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7.1 Time plan of JDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087.2 Test implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

xii

Introduction 1The fast development of memory devices, the more and more area occupation ofmemory in a chip and the strong market competition have increased the standards ofthe produced memories; memory products should nowadays be more reliable than ever.The increased demand on reliability has, in turn, stressed the importance of failureanalysis and device testing techniques. More and more effort and thought is beingdedicated to the study of testing memory devices with regards to new fault models,fault diagnosis and new memory architectures. This thesis describes one such study as ajoint project between Delft University of Technology and Altera Corporation, wherebythis chapter presents an introduction to the whole thesis.

This chapter is organized as follows. In Section 1.1, the concept and developmentof memory testing are addressed. In Section 1.2, the importance of memory testingis discussed. In Section 1.3, the challenge of memory testing and the correspondingcontribution of this thesis is presented. In Section 1.4, the contents of this thesis isoutlined.

1.1 Memory testing1.2 Importance of memory testing1.3 Contribution of this thesis1.4 Outline of this thesis

1

2 CHAPTER 1. INTRODUCTION

1.1 Memory testing

Semiconductor industry has seen a great development in terms of device, design andtechnology, a significant symbol of which is the emergence and evolution of Very LargeScale Integrated (VLSI) circuits. VLSI circuits are an integral part of any modernelectronic system. Such circuits consist of thousands to millions of transistors, diodesand other components such as capacitors and resistors, together with interconnections,within a very small area. They can be divided into two classes: combinational circuits(without memory) and sequential circuits (with memory). The manufacturing of suchcircuits is a complicated and time-consuming process and defects in them are inevitable.From both economic and technological point of view, it is very important to carry outtesting in any VLSI manufacturing process, whereby memory testing is an essential topic.

Figure 1.1: General classification of semiconductor memory

Semiconductor memory devices diversify in function and designs, which can begenerally classified into Random Access Memory (RAM) and read Only Memory(ROM). Both of them are composed of different branches, as is shown in Figure 1.1 [7],where Static RAM (SRAM) is again divided into Single-Port SRAM (SP SRAM) andMulti-Port SRAM, and SP SRAM is of concern through the whole thesis work. Thuswe focus on the drive and development of SP SRAM testing in the following discussion.

Tests for SP SRAMs have experienced a long development process. Before 1980,tests had very long test times for a given fault coverage (i.e., the number of detectedfaults divided by the number of total faults); typically of order O(n2), where n is thesize of the memory. Such tests can be classified as the ad-hoc tests because of theabsence of fault models and proofs. Tests like the Zero-One test, the GALPAT and theWalking 1/0 tests belong to this class [13].

To reduce the test time and improve the fault coverage, test development has beenfocused on the possible faults which probably can appear in the memory. For thatreason, functional fault models, which are abstract fault models, have been introducedduring the early 1980’s. The advantage of these models is that the fault coverage could

1.1. MEMORY TESTING 3

be proven while the test time usually was of order O(n); i.e., linear with the size of thememory. Some important functional fault models introduced in that time period werethe Stuck-At Fault (SAF), the Address decoder Fault (AF) [21], the Coupling Fault(CF) [47, 61, 43], and the Neighborhood Pattern Sensitive Fault (NPSF) model [14, 48].March tests became the dominant type of tests for SAFs, AFs and CFs [61, 49, 17];while special linear tests were designed for NPSFs [44, 17].

After the above functional fault models, which were abstract fault models not basedon real memory design and/or real defects, Inductive Fault Analysis (IFA) [42, 58]was introduced. IFA is a systematic procedure to predict the faults in an integratedcircuit by injecting spot defects in the simulated geometric representation of the circuit.It allows for the establishment of the fault models based on simulated defects in realdesigns. In addition, IFA is capable of determining the occurrence probability of eachfault model. The result was that new functional fault models were introduced [49]:the State Coupling Fault (CFst), the Data Retention Fault (DRF) and the Stuck OpenFault (SOF).

In the early 1990’s memories experienced an impressive increase in size, and as aconsequence linear tests became not always acceptable. In addition, the use of embeddedmemories had made the testability problem very hard because of the lack of the control-lability of their inputs and the observability of their outputs. Therefore, built-in-self-test(BIST) was proposed in order to overcome this problem [38, 24, 45, 50, 37]. BIST hasthe advantage of solving the access problem of embedded memories and reducing testrequirements in terms of test speed and the number of input/output (I/O) pins. Theadditional advantage of BIST is that at-speed testing (i.e., testing at the maximal clockperiod) is facilitated allowing for a higher fault coverage, especially for the dynamic(i.e., speed related) faults, which are becoming more important with the current highspeed memories. The current status of dynamic faults is comparable with the statusof functional faults in the early 1980’s; i.e., their existence and occurrence probabilityhave not been verified with IFA, or other techniques, while industrial data on theiroccurrence frequency and on the effectiveness of tests to detect them is not available.Design For Testability (DFT) (i.e., make the design manageable) techniques are beingimplemented to reduce test time and/or to allow for active, rather than passive, testsfor cell stability faults such as DRFs [46].

Beside the functional testing, parametric testing has been also developed. A widelyused test is the IDDQtest, which measures the quiescent power supply current while thecircuit is not switching [33, 41, 35]. If for example, a short is present in the circuit, thecurrent may be higher than usual and the fault will be detected. With the IDDQtestdefects can be traced which cause no functional faults and which thus can not bedetected with functional tests.


1.2 Importance of memory testing

Referring to the importance of memory testing, two phases can be taken into account,which are the importance of testing and the importance of memory.

1.2.1 Importance of testing

Nowadays, it has become common place to produce complex electrical devices in theform of small integrated circuits (ICs). A single IC with a surface area of no more than1 cm2 is capable of holding as much as 25 million transistors, resistors, capacitors andother electrical components on its surface. During IC production, small variations in theparameters of the fabrication process are tolerated since reducing the tolerance resultsin a rapid increase in the fabrication costs. As a result, a considerable number of theresulting ICs are produced with deviations that may prevent proper operation. Besidethese parametric deviations, there are also many defects that cause hard faults. Suchdefects may be due to several deficiencies in the original silicon and in the manufacturingprocess. Examples of the former are impurities and dislocations, and examples of thelatter are temperature fluctuations during the processing, open interconnections, opencircuits, short circuits, bridges, cross talks and extra or missing transistors.

In order to ensure that the end consumer receives a properly operational product, itis important to test the fabricated ICs thoroughly. If defective ICs are not detected andreplaced early in their life cycle, it becomes increasingly difficult and expensive to detectthem as they become components of larger systems. Yet, performing an elaborated teston each produced IC would take excessive amounts of time and increase the price of ICssignificantly. Therefore, an optimization should always be made between the losses ofprocessing and selling defective ICs, and the losses resulting from testing the producedICs. This relation between costs and test quality is depicted in Figure 1.2 [6]. The figureshows that starting from a very low test quality (no testing) the total cost of the productdecreases as the test quality increases. This behavior continues until a minimum totalcost is reached, after which the gains expected as a result of testing become less thanthe costs of the testing process itself. Therefore, from economic point of view, testing isquite essential for reducing total cost.

1.2.2 Importance of memory

According to the 2001 ITRS, today’s system on chips (SoCs) are moving from logicdominant chips to memory dominant devices in order to deal with today’s and futureapplication requirements. Figure 1.3 [ITRS2000] shows how the dominating logic (about64% in 1999) is changing in dominating memory (more than 52% today). In addition,SoCs are expected to embed memories of increasing sizes; e.g., 3Gbits and more. Asa result, the overall SoC yield will be dominated by the memory yield. In addition,Figure 1.4 [ITRS] demonstrates that memory yield decreases with the increasing size ofmemory, which leads to the great need of testing memories before sale in the future.

1.3. CONTRIBUTION OF THIS THESIS 5

Cost

Test quality

Figure 1.2: Influence of test quality on total cost of produced ICs

Figure 1.3: The future of embedded memory

1.3 Contribution of this thesis

Prior to describing the contribution of this thesis, I would like to introduce the currentor future challenge in memory testing. VLSI circuits can be generally categorized aslogic devices and memory devices, the testing of which two are with different challenges.


Figure 1.4: Memory sizes versus yield

1.3.1 Challenges in memory testing

Logic devices are usually reckoned as a transfer function which converts a number ofinputs into a number of outputs, whose operation and function is quite limited, andthus its functional fault models are comparatively limited. On the other hand, thecircuitry of logic devices are often quite complicated and huge. On account of this,testing logic devices is mainly focusing on fault collapse, DFT and output compact. Incomparison, the memory circuitry consists an array of regular cells; i.e., its circuitry issimpler. However, memory involves a limitless of operations and thus infinite functionalfault models. Since the development of memory testing is driven by the establishmentof new fault models, the first challenge of memory testing is to discover, validate andestablish new fault models, based on which new testing algorithms can be designed.In addition, previous testing is highlighting the fault detection, while fault diagnosisis becoming an increasingly important topic for memory devices to reduce the timein yield improvement. On the one hand, fault diagnosis can specify those faults withhigh occurrence probability, which is helpful to optimize former tests and thus reducethe test cost. On the other hand, the on-going fragmentation of the IC productionprocess forces memory designers, memory manufacturers and test-service providers touse standardized, easy-to-implement test methods that enables effective transfer of testinformation between different companies [12]. Moreover, different memory structures fordifferent companies and utilities bring forth huge impact to memory testing, includingdifferent limitations for operation and different possibility of fault models; hence, todevelop specific test algorithms for specific memories is an upcoming topic. Finally,

1.3. CONTRIBUTION OF THIS THESIS 7

unlike tests for logic devices, majority of the tests for memories are implemented with acertain stress combination. However, there is no systematic analysis with respect to theinfluence and effect of different stress combinations; as a result, to figure out the exactstress brought by a stress combination and to find out new stress combinations is a newchallenge. In conclusion, the challenges of memory testing can be outlined as follows.

• Fault model: Establish new fault models for deep-submicron technology

• Fault diagnosis: Diagnose faults in an extensible, platform-independent and effi-cient way

• Design of test algorithm: Suit specific test algorithms to specific memory structures

• Impact of stress: Study the influence of stress combinations in a systematic way

1.3.2 Contributions of this thesis

Corresponding to the challenges presented above, this thesis has contributed to severalof them to different extent.

1. Design of a test program to realize high fault coverage for embedded memoriesused in Altera

• Selection of a series of test algorithms for SRAMs with conventional structure

• Fault diagnosis: Based on the concept of test primitive (TP) come up withby Zaid Al-Ars and Said Hamdioui, this thesis work has designed a largeamount of TPs for memory cell array faults, developed several principles, likeTP Evaluator, to regulate the generation of TPs to satisfy the criterion ofTP, created the concept of Combined TP, and structurized the procedure ofgenerating the diagnostic dictionary using TPs.

• Design of specific test algorithms for specific memory structures: A new testalgorithms for faults within dynamic address decoders used in Altera has beendeveloped, where the address transitions, test operations and stress combina-tions are all changed to suit Altera’s specific structure.

2. Implementation at Altera

• Validation of 20 test algorithms: 3 tests with different stress combinationsconstituting 20 tests are validated on real silicon (Stratix III family of FPGAchips fabricated with 65nm technology)

• Volume test: It will be done in December 2008. This deference is due to theircorporation plan and the temporary incompetency of the BIST in Altera.

• Development of new test for CRAM. CRAM is a confidential memory em-bedded in Altera’s FPGA, which bears substantial different structure andoperation limitations from conventional SRAM. Therefore, a series of newfault models and new test algorithms were designed for CRAM.


• Soft BIST: One specific part of address generating circuitry has been createdto test dynamic address decoder faults.

• Stress combination study: The stress brought by the output latch has beenput forward, which proves to bring impact to tests for address decoder faultsand peripheral circuits faults.

1.4 Outline of this thesis

This thesis is organized as follows. Chapter 2 describes the basic architecture of SRAMson electrical level and functional level, including its electrical characteristics and func-tions of each functional modules. Chapter 3 introduces the fault models of SRAMs, com-prising of fault models within each functional modules discussed in Chapter 2. Chapter4 puts efforts on developing TPs for a part of memory cell array faults, followed bystreamlining the diagnostic method based on TPs; Chapter 4 also dives into many de-tails for creating TPs, such as handling the contradiction of different criterion, creatingnew TP concepts and inventing TP optimum evaluating equations. Chapter 5 discussesa set of advanced test solutions that target different classes of memory faults. Chapter 6sets up a test program composed of 3 groups of tests to realize fault diagnosis, cover newemerging faults and detect special faults in SRAMs. Chapter 7 generally presents thework done in my internship with Altera. Chapter 8 ends the thesis with some conclusionand recommendations.

SRAM structure 2As is introduced in Chapter 1, semiconductor memories are divided into RAMs andROMs, where RAMs are categorized as SRAMs and DRAMs. SRAM is the initial ofStatic Random Access Memory where the word “static” indicates that it, unlike dynamicRAM (DRAM), does not need to be periodically refreshed. SRAM is expansively usedin industry where high frequent operations are not needed, testing which is a veryimportant and tricky issue. As far as Chapter 1 introduces, the first problem of memorytesting is to establish fault models. Thereby it is necessary to understand the SRAMstructure on both electrical level and functional level, as well as the mechanism of readand write operations. Based on such understanding we can build up fault models anddevelop corresponding test algorithms.

This Chapter is organized as follows. In Section 2.1, we introduce the bistablestructure that realizes the function of SRAM. In Section 2.2 the SRAM is depicted asa combination of different functional modules. In Section 2.3 the electrical circuitryof different modules are presented in detail, in addition to which, the read and writeoperations are also explained. In Section 2.4 a summary is given.

2.1 Bistable structure2.2 Functional structure of SRAM2.3 Electrical circuitry of SRAM2.4 Summary

9

10 CHAPTER 2. SRAM STRUCTURE

2.1 Bistable structure

Memory, in terms of its macro meaning, is a function or device that can store a writteninformation for a certain time. If a memory can not be rewritten, then we say it is aRead Only Memory (ROM), otherwise, it is called Random Access Memory (RAM). Itseems RAM is more versatile since its written information can be changed. However,just because of its character of changeability, the written information of RAM canalso be affected by environment; i.e., it is, to different extent, volatile. If it is stronglyvolatile then it is called Dynamic RAM (DRAM), which means its information leaks ina short time and thus requires refreshing periodically. Be it weakly volatile then it isdefined as Static RAM (SRAM), which means its information lasts long and does notrequires refreshing periodically . A series of examples can be applied to explain thedistinct of those three memories. For instance, if we carve the blackboard to recordsome information, such a blackboard is a ROM; if we write on the blackboard withwater, then it becomes a DRAM; if we write on the blackboard using a chalk, thenit evolves to be an SRAM. The SRAM character is realized by the so called bistablestructure.

To understand the mechanism of the bistable structure as the core of SRAM, wefirstly look into a kind of non-bistable structure, an inverter, shown in Figure 2.1.Whereby we try to testify whether this device can serve as an SRAM kernel.

B

VDD

VSS

A

Figure 2.1: An inverter

If we feed A with logic 0, then B will see 1. After removing the input of A, thevalue of B will be stored for a certain time since B has a certain capacitance to theground. Whereas it will inevitably experience a leakage or ambient disturbance withoutself refreshment, which means the value of B will fade away as time passes by. Sucha structure can serve as a DRAM but not an SRAM. Then we explore the bistablestructure, which is commonly used in industry. The basic electronic bistable structureis organized by two cross-coupled inverters, as is shown in Figure 2.2.

2.1. BISTABLE STRUCTURE 11

VSS

DDV

A

B

C

D

Figure 2.2: A bistable structure in SRAM

We feed 1 to B and D, yielding that A=C=0. Suppose A=0 is the memorizedvalue, we will verify whether this value is tenable after a time interval’s leakage.Given that the VA is the output voltage of left inverter and VB is the input voltage.Firstly, we plot the VB × VA characteristic chart, which is indicated in Figure 2.3.It’s necessary to point out this smooth curve is approaching the reality that inpractical case the charge on capacitors are always varying even the voltage acrossthe MOS gate and source is below VTH . Notice A, as the output of left inverter,also directly connects with the input C of right inverter through a conduction linewhile B and D are in the symmetric situation. If we put VB and VD to the Xaxis and assign Y axis with VA and VC , which means both two I/O characteristics ofleft and right inverters are combined together, a new chart will be exported in Figure 2.4.

It is clear that only three point satisfying the cross-coupling of two inverters, namelyL, M and N, which means the voltages of port A,B,C and D only can be 0, VM andVDD when the system lies in steady state. Since A=0 is the stored value, the systemnow is located at point N.

Next we will investigate on which point will the system be located, when there is adisturbance or impact to node B or C. Concerning Figure 2.5, suppose port B sees aleakage and the corresponding voltage VB decreases by ∆X1, so the working point ofleft inverter moves up to point H where VA increases by ∆Y 1 indicated by the point Jlying on X axis. Notice although VB=VD is set up in a transient period, D won’t affectC since D is the output of the right inverter. C, only affected by A which connectsC through a metal line, will also undergoes an increment of ∆Y 1, which makes theworking point of the right inverter moves to I. At this point, the determination fromC will give rise to a new D voltage indicated by point K on the X axis. It is definitethat K is closer to VDD than J, resulting in a increase of VB, which means the decreaseof VB will automatically be ‘dragged’ back by the intrinsic force in the system. This


Figure 2.3: The I/O characteristic of the left inverter

Figure 2.4: The inner I/O characteristic of a bistable structure

dragging back trend, happening to both L and N, will act on until the changed valuerecovers to its original state, and it is done by the recharge or discharge to the accordingleaked or charged capacitor within the system spontaneously. In this way, the value ismemorized with a self-refreshment to compensate the leakage or revoke the externalchange in a right way. However, if the system lies at the steady point M, this point iscalled the middle stable state since any little disturbance will push the working pointto either L or N. More attention should be paid to that if the initial change of a storedvalue exceeds the point M, the further changing trend will move on but not come back,so the system will flip to a complement value, which can be derived with the similaranalysis. Thus, we can come to the conclusion that the bistable structure can memorizethe previous information as long as the external disturbance does not excel a certainvoltage, which we define to be Vflip.

2.2. FUNCTIONAL STRUCTURE OF SRAM 13

Figure 2.5: The mechanism of the bistable structure

Therefore, the bistable structure illustrated above can be adopted as an SRAM unit;i.e., it can store previous information with self-refreshing ability and be written intoanother value, where the critical voltage is Vflip.

2.2 Functional structure of SRAM

The functional structure of SRAM is represented by partitioning an SRAM chip intodifferent functional modules, where the inner circuitry that constitutes them is out ofinterest. In order to develop a general profile of different SRAMs, we firstly turn toa kind of diagram called black-box which is more abstract than the functional modelbecause only different data pins and their functions are included; see Figure 2.6 [59].

The SRAM has an address input of N bits, A(0) through A(N-1), and a data inputof B bits, Din(0) through Din(B-1). The only SRAM output is a data output, alsoconsisting of B bits: Dout(0) through Dout(B-1). It is also possible to implement anSRAM with a common data input and output. The SRAM often has four control inputswhich are also shown in Figure 2.6. With the write enable signal a write operation canbe selected. The chip select signal allows the user to deselect the device when desired.The clock enable signal allows the operation of the SRAM to be suspended as long asnecessary and the output enable controls the data output of the memory.

Figure 2.6 can be instantiated into a functional block diagram. This diagramconsists of several functional blocks which are the subsystems of the SRAM. Thefunctional block diagram of the SRAM is shown in Figure 2.7 [59]; it applies to mostsynchronous SRAMs. The kernel of the SRAM is the memory cell array comprising


Figure 2.6: The black box diagram of an SRAM

of many thousands of memory cells. These memory cells are addressed by an N-bitaddress. The row decoder uses a number of address bits to select the desired row ofthe array. The column decoder uses the remaining address bits to address the correctcolumn. The column decoder is connected to bit line multiplexers, which route theaddressed data from the write drivers or to the sense amplifers.

The SRAM has two basic operations: read and write. When data must be read outof the memory array, the correct address must be set and stored in the address latch.After the address is set the row and column decoder select the desired part of the array.The data in the cells is put on the bit lines and is fed through the bit line multiplexersto the sense amplifiers. The senseamplifiers amplify the data voltages to the correctlevel and the data is fed into a data output latch. Writing data is very much like readingdata. The input data is supplied to the data input latch which feeds it to the writedrivers. After the desired array part is selected by the row and column decoder, thewrite drivers force the desired bit lines to their correct level and the memory cells whichare connected to these bit lines by the word lines receive the written data. A bit lineprecharge circuit is added to the SRAM to increase the speed of reading the cell. Beforethe cells are connected to the bit lines, the bit lines are charged to a given voltage.The bit lines in the SRAM appear in pairs, because the memory operation is based ona technique, called differential signaling. With this technique, data is represented bysmall voltage differences across both bit lines. The use of small voltage differences isvery advantageous for the speed of the SRAM.

Data often is stored in an SRAM in words at once. These words are a given numberof data bits belonging together. The number of bits in a word is mostly 8 or 16 formemory chips. However, for application specific memories the number of bits in a wordis variable. The size of the memory cell array is always expressed with two numbers.

2.2. FUNCTIONAL STRUCTURE OF SRAM 15

Figure 2.7: The functional diagram of an SRAM

The first number defines how many words can be stored in the array and the secondnumber defines the number of bits in a word. For example, in a 32k× 8 SRAM arethere 32k words, each consisting of 8 bits, can be stored. The experssion of these twonumbers is called the memory organization. In this thesis the following symbols are used.

• ‘W’ denotes the number of words which can be stored in the array

• ‘B’ denotes the number of bits in a word

It is clear that the memory cell array consists of W×B memory cells. For the inputand output of data the SRAM contains B pins, because data is read and written inthe unit of one word each time. Thus, it’s normal to design a memory cell array tobe with W rows and B columns. Because most SRAMs can store many thousands ofwords, the height W is much larger than the width B. For that reason, the bit lines are


very long and the word lines are rather short. So the bit lines, which are connectedto many thousands of cells, have a very large capacitance which will cause a decreasein speed. More substantially, this is due to that each node on the bit line breeds acapacitance to ground; the longer the bit line is, the more capacitors will be, andespecially because there are resistances between adjacent capacitors, there will be a timeinterval between the charge or discharge of neighbor capacitors; i.e., without the resis-tance, a whole bit line will attain a voltage level at the same level no matter how long it is.

To decrease this delay, there are two methods: change materials with smallerresistance; organize the array to be roughly square. In design perspective, we choose thelatter. In that case the bit lines and the word lines have roughly the same length andno line is extremely long. The technique to resize the array is called array folding.With this technique the bit lines are ‘cut’ in parts and these parts are placed side byside. The “bit line parts” form a segment and a multiplexer is added to select one of theparts from the segment. In this way the height of the array can be decreased and thewidth can be increased until the array is square. In this thesis the following symbolsare used.

• ‘S’ denotes the number of segments

• ‘R’ denotes the number of rows in a segment

• ‘C’ denotes the number of columns in a segment

To make the array square, it should satisfy S×C=R. As C=B and S×R=W, wecome to the following equations.

• S =√

W/B

• R =√

W ×B

• C = B

2.3 Electrical circuitry of SRAM

An SRAM chip can be generally divided into four parts, which are the memory cell, theread circuitry, the writing circuitry and the address decoding circuitry. They will berespectively discussed on concerns of their basic working principle but not details in thefollowing sections.

2.3.1 The circuitry of an SRAM cell

The memory cell is the key part where the data is stored for read and write. There’reseveral kinds of cell circuitries while the 6T cell, depicted in Figure 2.8, is commonlyused because of its speed advantage, where 6T stands for 6 transistors. In this cell is abistable structure plays the role of storage, which is in depth probed in Section 1.1.

2.3. ELECTRICAL CIRCUITRY OF SRAM 17

T6

VSS

DDV

T3 T4

T5

A

B

C

D

BL BL

WL

T1

T2

Figure 2.8: The 6T SRAM cell

2.3.2 The reading process

Reading a memory is a series of processes happening consecutively in different parts,which can be reckoned as a reading path indicated in Figure 2.9 [59].

Figure 2.9: The read path of an SRAM

Firstly, every precharge signal is turned high, making BL and BL attain logic 1;meanwhile the two pMOS transistors of the sense amplifier are working in the saturationregion with the same VGS . Then the word line is set high, attributing to which, the datastored in the cell is copied to the bit lines. Next, the word line is turned down to 0 andthe EN is set high, insulating the cell and selecting one path between bit lines and datalines to be activated by the multiplexer. Once the bit lines and data lines are connected,one of the high potential data line will be pulled down to some value, leading to avoltage difference between two data lines, which will be amplified to a certain level bythe sense amplifier. The amplifier will assign the amplified value to DL and then turn onCK1 in order to send the amplified value to the data output latch, waiting for inspection.

Next, the different procedures in the reading process will be examined in detail.


2.3.3 Precharge of BLs

There are two reasons accounting for precharge other than pre-discharge of twoBLs. Referring to Figure 2.8, firstly, because the pMOS has a higher impedancethan nMOS with the same geometry, to increase the speed, we’d like to use nMOSto be the pass transistor denoted by T1 and T6, so without the precharge to VDD

of BL and BL, the bit line connecting to the stored 1 can only be pulled up toVDD-VTH by the pass nMOS transistor, resulting in the infidelity. Secondly, no matterwhich bit line is to be pulled up by the stored data, the current has to go througheither T3 or T4, both of which are pMOS; as is claimed, pMOS has a low pullingspeed, so we should precharge two bit lines, leaving only pulling down task to T2 and T5.

A typical precharge circuit is shown in Figure 2.10 [59], where the top pMOS tran-sistor is exploited to equalize two lines voltage, which means as long as one line can becharged to 1 the other will surely obtain that value.

Figure 2.10: A precharge circuit

2.3.4 Connection of BLs and the cell

After precharge of the bit lines, the word line will be set to 1 to make T1 and T6conductive, connecting both bit lines to the cell data nodes, indicated in Figure 2.11.

To be consistent to Section 1.1, we still suppose A stores value 0 and D stores 1,and then nothing will happen to the conduction path organized by T4, D, T6 and BL,while T1 and T2 will constitute a voltage division case where R1 and R2 are their initialtransient resistance, bring forth a voltage at A; i.e., VA. As discussed in Section 1.1, thecell will flip as long as VA > Vflip. Therefore, to make the reading feasible, we have toensure R2

R1+R2 < Vflip, where R1 and R2 are the corresponding resistance of T1 and T2at the beginning of connection since their resistance change as time varies.

2.3.5 Bit line multiplexer

Because SRAM stores datas in the unit of words while there are B bits in each word.As there are only one data line pair and one sense amplifier so during each reading


i

VSS

DDV

T6

(R1)

(R2)

A

B

C

D

BL BL

WL

T1

T2

T3 T4

T5

Figure 2.11: The memory cell under external force when read

process we need a bit line multiplexer to select one through B bit line pairs to connectthe data line pair. The structure of a bit line multiplexer is simple that it just containsB transmission gates; see Figure 2.12 [59]. Because there are both pMOS and nMOSin a transmission gate, it’s capable to carry out both pull up to 1 and pull down to 0function. Choosing ENX to be 1 means selecting BL(X).

write driver

DL

sense amplifier

BL(0) BL(1) BL(B−1)

EN(0)EN(1) EN(B−1) EN(B−1)EN(0) EN(1)=1

Figure 2.12: Bit line multiplexer where BL(1) is selected

2.3.6 Sense amplifier

Sense amplifier is a differential amplifier which is exerting its effort to diminish the noisedisturbance because noise basically affect the double input, forming a common mode


signal, whose variation will experience a very small gain compared with the differentialsignal. One of the popular sense amplifier is called the opamp exploiting the currentmirror theory. See Figure 2.13 [59].

Figure 2.13: An opamp sense amplifier

The two sided prech are used to precharge the drain of two pMOS, making VDS=-VTH , and thus the current will go downwards. The middle prech functions to equalizetwo drains of top pMOS and the rectangle line connecting the gate and drain of theright pMOS actualizes two pMOS’ working in the saturation region. In this way, twopMOS are under the same condition so i4=i5=i2, and this is the current mirror theory. Inaddition, i1+i2=i3 while i3 is exclusively determined by the sense signal, so it’s constant.Thus, if the tiny variation of data line brings in a change 4i to i1, then i2 will face achange of -4i. Consequently, 4iout=24i.

2.3.7 Data output latch

Normally, the data output can be directly read through the output line of sense amplifier,but to avoid the glitch caused by noise after the correct output has been established andto make inspector see the output as a fixed value but not a gradual changing value, wewould like to use a box to latch the final value and read it in the following clock period.This is the reason we use a data output latch shown in Figure 2.14 [59].

When CK=1, the data in DL2 will be fed to Dout; when CK=0, the right part willform a cross-coupled invertors which is known as a bistable structure. Therefore, thisdevice forms a high potential transparent D latch.

2.3.8 Writing process

The write path of an SRAM can be defined as the route of the write data from the datainput to the memory cell array. The write path is shown in Figure 2.15 [59]. In thisdiagram also the control inputs of the different subcircuits are shown as dashed arrows.As a counter part of the read cycle, the write cycle consists of two phases: the precharge


Figure 2.14: Data output latch

phase and the write phase. The write cycle starts with the precharge phase in whichBL, BL, DL1 and DL1 are precharged by setting Prech high. During this prechargephase the input data is stored in the data input latch by pulsing Cki. The write phasestarts with writing the data to DL1 and DL1 by the write driver. For that reason thewrite enable signal WE is set high. During this write operation EN is set high, so thatthe data lines DL1 and DL1 are connected to the bit lines BL and BL. Consequently,the bit lines contain also the write data and it is written into the cell by setting WLhigh. The write cycle is finished by setting WE, EN and WL low.

Figure 2.15: Write path of SRAM

In the next sections the data output latch and the write driver will be instantiatedsince the rest of the blocks have been explored before.

2.3.9 Data input latch

The data input latch is of the same type as the data output latch. It is also a D typelatch as shown in Figure 2.16 [59]. With the symmetric working principle as the outputlatch, when Cki is set high, the data input latch obtains the Din value; while it forms across-coupled structure when CKi is set low.


Figure 2.16: Data input latch

2.3.10 Write driver

The write driver is a circuit that has to put the correct write data on DL1 and DL1during a write cycle. For each write data bit, the SRAM contains one write driver, sothere are B write drivers in the memory (B is the number of columns). Since the datalines are also precharged before a write operation, the purpose of the write driver is topull one data line low, and the write driver needs only a pull down circuit. The sizeof the transistors must be chosen so that the write driver is capable to over drive thedesired memory cell.

Usually the write driver has two inputs: a data input DL3 which contains the datato be written into a cell, and a write enable signal WE that controls the write operation.Figure 2.17 [59]illustrates the basic structure of a write driver. With the WE set high,the write driver output is connected to the DL1 and DL1 and vice versa. With the DL3set high, DL1 is pull down and vice versa.

Figure 2.17: Write driver


2.3.11 Write into the cell

As is illustrated previously, writing is nearly an inversed process of reading. However,there is a key difference between writing and reading, which is the mechanism for a cellto flip its value during writing. To discuss about this, some modification on Figure 2.11is modified, yielding Figure 2.18.

(R6)

VSS

DDV

1

i2(R4)

A

B

C

D

BL BL

WL

T1

T2

T3 T4

T5

T6

(R1)

(R2)

10

1 0

i

Figure 2.18: The memory cell under external force when written

During the writing process, the bit lines are respectively precharged with an oppositevalue to the nodes in cell waiting to be connected; i.e., BL=1, A=0, D=1, BL=0. ThenWL is set high to realize the connection. According to the deduction in Section 2.3.4,node A will see a voltage ascendence while this initial ascendence is ensured belowVflip, which is incapable of flipping the cell. However, T4 and T6, with their initialresistance R4 and R6, also form a conduction path where the voltage at D is conformingto the voltage division’s law. Thus, VD= R6

R4+R6VDD. According to the conclusionmade in Section 1.1, choosing a certain line width for top two pMOS will guarantee

R6R4+R6VDD>Vflip, and this will initiate the chain reaction for the voltage changing untilthe cell is totally flipped.

Therefore, as long as the pMOS and nMOS in a cell are appropriately chosen, bothread and write can be fulfilled.

2.3.12 Address decoding circuitry

Previously what we have discussed is the mechanism running in an appointed cell whilein an SRAM chip are a large number of cells, so before any execution in a cell we mustchoose that cell first. The circuits making this effort is Address decoding circuitry.Because it’s not as important as the inner world of a cell, we just present a row decoderand give simple introduction. See Figure 2.19 [59].


Figure 2.19: A row decoder

In this decoder are there 3 inputs which means there are 23 options reflecting 8 wordlines. The CK signal is set to activate or insulate decoder to inner cells. When Ck is sethigh the decoder is activated and can choose different word lines to be charged; when CKis 0 the decoder is insulated so as not to affect the inner process of a cell. For instance,when CK=1, and a(1), a(2) and a(0) are all equal to 1, then WL(7) is selected to becharged while others are kept their original state.

2.4. SUMMARY 25

2.4 Summary

This Chapter describes the SRAM in three phases, which are the methodology of bistablestructure to enable the key function of SRAM, the functional modules that constitutethe SRAM, and the electrical circuitry of SRAM as well as the operational principles.Understanding such knowledge is the first step in memory testing, based on which thefault models and testing algorithms can be developed. Also ascribing to such under-standing, we can optimize our testing algorithms and set up the most appropriate stresscombinations when implementing a test. In addition, the design of BIST is also relyingon such understandings.

Memory fault models 3In Chapter 2, the functional SRAM model has been discussed, which is the collectionof the functional specifications of the memory together with the internal structure ofits subsystems. In general, the functional model of a memory depends on its specificimplementation. However, for test purposes a so called ‘reduced functional memorymodel’ is used that only consists of three subsystems: the address decoder, the memorycell array and the read/write logic. Since the vast majority of mainstream memorydevices contains these three subsystems, the reduced functional fault model is, to alarge extent, independent of specific memory implementations. Thus, the fault modelsbased on the functional model will be valid for most cases.

This chapter is concerned with defining the functional fault models , which isorganized as follows. In Section 3.1, the concept of fault primitives and fault model isgiven. In Section 3.2 the fault primitive is classified according to different standards.In Section 3.3 the SRAM is instantiated with a functional model. In Section 3.4 thememory cell array faults are presented. In Section 3.5 the address decoder faults arediscussed. In Section 3.6 the peripheral circuit faults are explored. In Section 3.7 thefaults related to memory architecture are probed. In Section 3.8 a summary is providedto end the chapter.

3.1 Definition of fault primitive and fault model3.2 Classification of fault primitives3.3 Reduced functional memory model3.4 Memory cell array faults3.5 Address decoder faults3.6 Peripheral circuit faults3.7 Faults related to memory architecture3.8 Summary

27

28 CHAPTER 3. MEMORY FAULT MODELS

3.1 Definition of fault primitive and fault model

Intuitively, a functional fault model is defined as a description of the failure of thememory to fulfill its functional specifications. According to [25], this definition of afault model is not a precise one since it does not indicate which functional specificationsshould be taken into account. Still, the definition specifies the intuitive meaning of afault model and the way it should be viewed. The term ‘functional specifications’ shouldbe understood in a rather general sense. They should be detailed enough to describe thecontents of individual memory cells.

By performing a number of memory operations and observing the behavior of anycomponent functionally modeled in the memory, functional faults can be defined asthe deviation of the observed behavior from the specified one under the performedoperation(s). Therefore, the two basic ingredients to any fault model are:

1. A list of performed memory operations.

2. A list of corresponding deviations in the observed behavior from the expected one.

Any list of performed operations on the memory is called an operation sequence.An operation sequence that results in a difference between the observed and the expectedmemory behavior is called a sensitizing operation sequence (SOS). The observedmemory behavior that deviates from the expected one is called a faulty behavior. Wheninspecting the memory for possible faulty behavior, not all the functional specificationsare taken into account and compared with the actual memory behavior. Rather, a verylimited subset of functional parameters is selected as most relevant to describe the faultybehavior of the memory. Throughout the 1980s and during the first half of the 1990s,the only functional parameter considered relevant to the faulty behavior was the storedlogic value in the cell. Recently, another functional parameter, the output value of aread operation, was also considered to be relevant to describe the faulty behavior [25].

Thus in order to specify a certain fault, one has to specify the SOS, together withthe corresponding faulty behavior. This combination for a single fault behavior is calleda Fault Primitive(FP), and is denoted as <S/F/R> [18]. S describes the SOS thatsensitizes the fault, F describes the value or the behavior of the faulty cell(e.g., thecell keeps sticking at a faulty value), while R describes the logic output level of a readoperation if the final operation of SOS is read. It should be highlighted that the faultprimitive is a description of a fault other than its test pattern which is produced accordingto the fault primitive. More important, Since different faults may bring in the same errorafter experiencing the same SOS, we should define that only the final operation in anSOS will conflict with the actual situation of a faulty cell, otherwise a fault primitivemay stand for different faults, which will be explained in a declaration within section3.4.1.1.

The concept of an FP allows for establishing a complete framework of all memoryfaults, since for all allowed operation sequences in the memory, one can derive allpossible faulty behaviors. In addition, the concept of an FP makes it possible to givea precise definition of a functional fault model (FFM) as it has to be understood for

3.2. CLASSIFICATION OF FAULT PRIMITIVES 29

memory devices:

A functional fault model is a non-empty set of fault primitives [65].

This definition of an FFM still depends on the selected functional parametersto be observed in the FPs. Yet, this dependence is now precisely known once theFPs are defined. Since a fault model is defined as as set of FPs, it is expectedthat FFMs would inherit the properties of FPs. For example, if an FFM is definedas a collection of single cell FPs, then the FFM is a single cell fault. If an FFM isdefined as a collection of 2-operation FPs, then the FFM is also called a 2-operation fault.

3.2 Classification of fault primitives

According to the characters of FPs, four kinds of classifications can be presented whereeach classification categorizes the FPs into two groups, which will be further concernedin later subsections [25].

1. The number of sequential operations required in the SOS, into static and dynamicfaults.

2. The way the FPs manifest themselves, into simple and linked faults.

3. The number of different cells the FPs do involve, into single-cell and multi-cellfaults.

4. The number of simultaneous operations required in the SOS, into single-port andmulti-port faults.

It is important to note that the four ways of classifying fault primitives are inde-pendent since their definition is based on independent factors of the SOS. As a result,a dynamic fault primitive can be single-port or multi-port, single-cell or multi-cell. Thesame is true for linked faults; they can be static or dynamic, and each of them can besingle-port or multi-port, single-cell or multi-cell. In scope of this chapter, we will focuson faults confined in the spotted lines plotted in Figure 3.1.

3.2.1 Static versus dynamic faults

Let #O be defined as the number of different operations performed sequentially in anSOS. For example, if a single read operation applied to a certain cell causes the samecell to flip, then #O=1. Depending on #O, FPs can be divided into static and dynamicfaults [25]:

• Static faults: These are FPs sensitized by performing at most one operation;that is #O≤1. For example, that the state of the cell is always stuck at one will


Single−cell

Fault Primitives

Static Dynamic

Simple Linked Simple

Single−cell Multi−cell

Single−port Single−portMulti−port

Multi−cell

Figure 3.1: Summary of fault primitive classification

just ask for a state to sensitize the fault other than an operation, so #O=0; whileanother fault requires a read operation to manifest itself, in which case #O=1.Attention should be paid to the glossary “sensitizing operation” because in generalVLSI system testing references any action or state that makes difference between acorrect system and a faulty system is called a sensitizing operation, but in memorytesting only functional operations belong to this category while a stationary state isnot reckoned as an ‘operation’. E.g., if a stuck-at-1 fault in an input of a logic gateis sensitized by a state that the input=0, this state 0 is deemed as a sensitizingoperation but in memory testing it is not since it’s not belonging to a memorymodule’s function [25].

• Dynamic faults: These are FPs that can only be sensitized by performing morethan one operation sequentially; that is #O>1. Depending on #O, a furtherclassification can be made between 2-operation dynamic FPs where #O=2, 3-operation dynamic FPs where #O=3, etc. For example, a memory cell will flip itsvalue only when three sequential read operations are applied, which is a 3-operationdynamic fault [25].

3.2.2 Simple versus linked faults

Depending on the way FPs manifest themselves, they can be divided into simple faultsand linked faults [25].

• Simple faults: These are faults that can not influence the behavior of each other;therefore masking can not occur. Naturally, a single fault must be a simple faultsince no more fault will affect it but a simple fault is not necessarily a single fault.However, in scope of this book, only the single fault is of interest [25].

3.2. CLASSIFICATION OF FAULT PRIMITIVES 31

• Linked faults: These are faults that do influence the behavior of each other. Thatmeans that the behavior of a certain fault can change the behavior of another onesuch that masking may occur [48, 17]. That is to say, ‘influence’ is not necessarily‘mask’. Naturally, linked faults must be multiple faults that coexist in a system.

Above we mentioned a glossary of ‘mask’, a direct definition of which is provided foran explicit understanding. If a system suffering two or more faults will export correctvalues under a certain operation, then we say those faults mask each other since no faultybehavior is observed. For instance, a fault leading to a wrong value in the read output ofa memory cell and a fault causing the inner value of a cell flip will be mutually masked,since from external point of view, the cell outputs a correct value as expected.

3.2.3 Single-cell versus multi-cell faults

Let #C be defined as the number of different cells accessed during an SOS. For example,if the operation sequence consists only of a single read operation applied to a single cell,then #C=1; if the operation sequence consists of two single read operations appliedsequentially to two different cells, then #C=2; etc. Depending on #C, FPs can bedivided into single cell faults and multi-cell faults (i.e., coupling faults) [25].

• Single-cell faults: These are FPs involving only a single cell. They have theproperty that the cell used for sensitizing the fault(by applying the SOS) is thesame as where the fault appears [25].

• Coupling faults: These are FPs that involve more than one cell; they have theproperty that the cell(s) which sensitizes or contribute for sensitizing the fault(e.g.,by applying the SOS) is different from the cell where the fault appears. Dependingon #C, this class can be further divided into two-coupling fault primitives in whichcase #C=2, 3-coupling fault primitives where #C=3, etc. In most cases #C=2 istaken into account, the reason for which will be presented in later sections [25].

3.2.4 Single-port versus multi-port faults

Let #P be defined as the number of ports required simultaneously to apply an SOS.For example, if a single read operation applied to cell c1 causes the same cell to flip,then #P=1; if two simultaneous read operations applied to the cell c1 cause the samecell to flip, then #P=2. Depending on #P, FPs can be divided into single-port faults,and multi-port faults [25].

• Single-port faults(1PFs): These are FPs that require at the most one port inorder to be sensitized; that is #P≤1. Note that single-port faults can be sensitizedin single-port memories as well as in multi-port memories [25].

• multi-port faults(pPFs): These are FPs that can be only sensitized byperforming two or more simulaneous operations via the different ports. Depending


on #P, the multi-port faults can be further divided into [25]:

1. Two-port faults(2PFs): These are FPs that can be only sensitized byperforming two simulaneous operations via two different ports; that is #P=2.Note that 2PFs can be sensitized in any multi-port memory with p≥2(pdenotes the number of ports) [25].

2. Three-port faults(3PFs): These are FPs that can only be sensitized byperforming three simultaneous operations via three different ports; that is#P=3. Note that 3PFs can be sensitized in any multi-port memory with#P≥3 [25].

3. etc.

3.3 Reduced functional memory model

Different memories compose of different functional modules consisting of various of sub-systems or circuits. If building up fault models respectively on all those memory struc-tures, we will come to a prohibitively large number of faults, which greatly contributeto the difficulty of testing. Thus, we would like to reduce the memory into three basicfunctional blocks that are common in majority of the memories ever exhibited. This, toa great extent, simplified our fault models construction and in turn the testing methods.In Figure 3.2 is a reduced functional memory model [17]:

Address

Memory cell array

Address decoder

Read/write logic

Data

Figure 3.2: The reduced functional memory model

3.4. MEMORY CELL ARRAY FAULTS 33

Corresponding to this model, faults in a memory are distributed in three parts dueto the historical division concerning modules of a memory chip:

1. memory cell array faults

2. address decoder faults

3. peripheral circuit faults

In the following sections we will respectively probe the faults in a memory based onthe distribution of faults defined above, embedded with the four classifications raisedbefore.

3.4 Memory cell array faults

This is the most important and common faults both in historical and current view, sowe will in depth explore their origin and behavior.

3.4.1 Static faults

These are faults requiring at most 1 operation to be sensitized.

3.4.1.1 Single-cell static faults

Ascribing to the order we introduced FFMs, we will firstly present the possible FPs andthen group them into different FFMs. Before listing the possible single-cell FPs (1PF1s),a precise compact notation, which will prevent ambiguities and misunderstandings, willbe introduced [25].

<S/F/R> (or<S/F/R>v): denotes an FP involving a single-cell (i.e., 1PF1s); thecell cv (victim cell) used to sensitize a fault is the same cell as where the fault appears.

S describes the value(a stationary state)/operation sensitizing the fault;S∈{0,1,0w0,1w1,0w1,1w0,0r0,1r1}, whereby 0(1) denotes a zero(one) value, 0w0(1w1)denotes a write 0(1) operation to a cell which contains a 0(1), 0w1(1w0) denotes anup(down) transition write operation, and 0r0(1r1) denotes a read 0(1) operation. If thefault effect of S appears after a time T, then the sensitizing operation is given as ST .

F describes the value of the faulty cell(v-cell); F∈{0,1}, where 1(0) denotes that thestate of the victim cell becomes 1(0)(or remains in 1(0)) due to a certain sensitizingoperation/value.

R describes the logical value which appears at the output of the SRAM if thesensitizing operation applied to the v-cell is a read operation: R∈{0,1,-}. A randomlogic value can occur if the voltage difference between the bit lines(used by the senseamplifier) is very small, but this is beyond our concern. A ‘-’ in R means that theoutput data is not applicable; e.g., if S=w0, then no data will appear at the memoryoutput, and for that reason R is replaced by a ‘-’.


Two declarations for the ‘S’ in each FP:

• No matter what fault exists in a cell, the cell can be initialized as a desired valuethough its life may be ephemeral. This is due to the initialization is realized by acoercive force, which is in depth discussed in last chapter.

• When an FP is written as <S/F/R>, no matter the S contains how many statesand operations, it is pre-assumed that only the final operation or state is differentfrom a correct behavior; otherwise an FP can represent too many faults. E.g., in<0w0/1/-> the first 0 is supposed to take place in the faulty cell; otherwise thisFP may stand for a transition fault.

Now that the possible values for S, F and R are defined for 1PF1s, it is possible tolist all FPs using this notation. Table 3.1 lists all possible combinations of the values, inthe <S/F/R> notation, that result in FPs. The remaining combinations of the S, F andR values do not represent a faulty behavior. For example, <1w0/0/-> corresponds to acorrect w0 operation after which the cell contains a 0, as expected. The column ‘FFM’in the table presents the FFM to which the corresponding FP belongs; such FFMs willbe discussed in detail in the next section.

Table 3.1: The complete set of 1PF1 FPs# S F R <S/F/R> FFM # S F R <S/F/R> FFM

1 0 1 - <0/1/-> SF 2 1 0 - <1/0/-> SF

3 1w1 0 - <1w1/0/-> WDF 4 0w0 1 - <0w0/1/-> WDF

5 0w1 0 - <0w1/0/-> TF 6 1w0 1 - <1w0/1/-> TF

7 0r0 0 1 <0r0/0/1> IRF 8 1r1 1 0 <1r1/1/0> IRF

9 0r0 1 0 <0r0/1/0> DRDF 10 1r1 0 1 <1r1/0/1> DRDF

11 0r0 1 1 <0r0/1/1> RDF 12 1r1 0 0 <1r1/0/0> RDF

It is clear from the table that there are 12 single-cell FPs, compiling which willexport a set of FFMs. The FFMs are given names, and each consists of a number ofFPs. Selecting which FP should belong to a given generic FFM is rather arbitrary andis mainly determined by historical arguments; see also the columns FFM in Table 3.1,which show the FFM to which each FP belongs; besides those indicated in Table 3.1,there is one more FM used to depict a time related fault, which is added in the end.Below is the detailed explanation of each FFM [25].

1. State Fault(SF): A cell is said to have a state fault if the logic value of the cellflips before it is accessed, even if no operation is performed on it. This fault isspecial in the sense that no operation is needed to sensitize it and, therefore, itonly depends on the initial stored value in the cell. The SF consists of two FPs:<0/1/-> and <1/0/->.


2. Transition Fault(TF): A cell is said to have a transition fault if it fails toundergo a transition(0 → 1or1 → 0) when it is written. This FFM is sensitized bya write operation and depends on both the initial stored logic value and the typeof the write operation. The TF consists of two FPs: <0w1/0/-> and <1w0/1/->.

3. Write Destructive Fault(WDF): A cell is said to have a write destructivefault if a non-transition write operation(0w0 or 1w1) causes a transition in thecell. The WDF consists of two FPs:<0w0/1/-> and <1w1/0/->.

4. Read Destructive Fault(RDF): A cell is said to have a read destructive faultif a read operation performed on the cell changes the data in the cell, and returnsan incorrect value on the output. The RDF consists of two FPs:<0r0/1/1> and<1r1/0/0>.

5. Deceptive Read Destructive Fault(DRDF): A cell is said to have a deceptiveread destructive fault if a read operation performed on the cell returns the correctlogic value, while it results in changing the contents of the cell. The DRDFconsists of two FPs:<0r0/1/0> and <1r1/0/1>.

6. Incorrect Read Fault(IRF): A cell is said to have an incorrect read fault if aread operation performed on the cell returns the incorrect logic value while keepingthe correct stored value in the cell. The IRF consists of two FPs:<0r0/0/1> and<1r1/1/0>.

7. Data Retention Fault(DRF): A cell is said to have a data retention fault ifthe state of the cell changes after a certain time T, and without accessing the cell.T should be longer than the duration of the precharge cycle in SRAMs, because ifthe cell flips within the precharge cycle then the sensitized fault would be a statefault. The DRF consists of two FPs: (a) the cell fails to retain the logic value 1and flips to 0 after certain time T: < 1T /0/− >, (b) the cell fails to retain thelogic value 0 and flips to 1 after certain time T: < 0T /1/− >.

Historically, several additional FFMs, such as UWF shown in table 3.1, which involveundefined values in its FPs were introduced. As they can be grouped to above faultsand make testing complicated, we exclude them in this chapter.

3.4.1.2 Two-cell static faults

Single-port fault primitives involving two cells CFs(Coupling Faults) are divided intothree types, as is shown in Figure 3.3 [25]:


v

Cv Cv CvCa CaCa

CFs CFa CF

Figure 3.3: The coupling faults(CFs)

1. The CFs: It has the property that the state of the aggressor cell(a-cell ca), ratherthan an operation applied to ca, sensitizes a fault in the victim cell(v-cell cv. Notethat no operation is required in that case; the subscript ‘s’ in the notation 1PF2s

stands for ‘state’ [25].

2. The CFa: It has the property that the application of a single-port operation(solidarrow in the figure) to the a-cell sensitizes a fault in the v-cell [25].

3. The CFv: It has the property that the application of a single-port operation to thev-cell, with the a-cell in a certain state, sensitizes a fault in the v-cell [25].

Before listing the CFs (different from CFs, notice the footnote symbol), a precisecompact notation for CFs, will be introduced.

< Sa;Sv/F/R > (or< Sa;Sv/F/R >a,v [25]: denotes an FP involving two cells;Sa describes the sensitizing operation or state of the aggressor cell(a-cell); while Sv

describes the sensitizing operation or state of the victim cell(v-cell). The a-cell(ca) isthe cell sensitizing a fault in another cell cell called the v-cell(cv). The set Si is definedas: Si ∈ {0, 1, 0w0, 1w1, 0w1, 1w0, 0r0, 1r1}(i ∈ {a, v}), F∈ {0, 1}, and R ∈ {0, 1,−}.

Table 3.2 lists all possible combinations of the values, in the < Sa; Sv/F/R >notation, that result in FPs. The column ‘FFM’ in the table shows the FFM each FPbelongs to; such FFMs will be discussed in more detail in the remained part of thissection.

The list of 36 possible CFs FPs will be compiled into a set of FFMs . Selecting whichFP should belong to a given generic FFM is rather arbitrary and is mainly determinedhistorically; see also the columns ‘FFM’ in Table 3.2, indicating the FFM to which eachFP belongs, which, as grouped in three categories, is to be probed in the following.

The CFs FFMs

This type has the property that the state of the a-cell, rather than an operation appliedto the a-cell, sensitizes a fault in the v-cell. Previously, it consists of two FFMs whilethe one contains undefined states is beyond our scope, yielding a single FM, which isthe State coupling fault (CFst) [25]: Two cells are said to have a state couplingfault if the v-cell is forced into a given logic state only if the a-cell is in a given state,without performing any operation on the v-cell or on the a-cell. This fault is special


Table 3.2: The complete set of CFs FPs; x ∈ {0, 1}# Sa Sv F R < Sa, Sv/F/R > FFM # Sa Sv F R < Sa, Sv/F/R > FFM

1 x 0 1 - <x;0/1/-> CFst 2 x 1 0 - <x;1/0/-> CFst

3 x 0w0 1 - <x;0w0/1/-> CFwd 4 x 1w1 0 - <x;1w1/0/-> CFwd

5 x 0w1 0 - <x;0w1/0/-> CFtr 6 x 1w0 1 - <x;1w0/1/-> CFtr

7 x 0r0 0 1 <x;0r0/0/1> CFir 8 x 1r1 1 0 <x;1r1/1/0> CFir

9 x 0r0 1 1 <x;0r0/1/1> CFrd 10 x 1r1 0 0 <x;1r1/0/0> CFrd

11 x 0r0 1 0 <x;0r0/1/0> CFdrd 12 x 1r1 0 1 <x;1r1/0/1> CFdrd

13 0w0 0 1 - < 0w0; 0/1/− > CFds 14 1w1 0 1 - < 1w1; 0/1/− > CFds

15 0w1 0 1 - < 0w1; 0/1/− > CFds 16 1w0 0 1 - < 1w0; 0/1/− > CFds

17 0r0 0 1 - < 0r0; 0/1/− > CFds 18 1r1 0 1 - < 1r1; 0/1/− > CFds

19 0w0 1 0 - < 0w0; 1/0/− > CFds 20 1w1 1 0 - < 1w1; 1/0/− > CFds

21 0w1 1 0 - < 0w1; 1/0/− > CFds 22 1w0 1 0 - < 1w0; 1/0/− > CFds

23 0r0 1 0 - < 0r0; 1/0/− > CFds 24 1r1 1 0 - < 1r1; 1/0/− > CFds

in the sense that no operation is needed to sensitize it and, therefore, it only dependson the initial stored values in the cells. The CFst consists of four FPs: < 0; 0/1/− >,< 0; 1/0/− >, < 1; 0/1/− > and < 1; 1/0/− >.

The CFa FFMs

This type has the property that the application of a single-port operation to the a-cellsensitizes a fault in the v-cell; it consists of one FFM:

Disturb coupling fault(CFds) [25]: Two cells are said to have a disturb couplingfault if an operation(write or read) performed on the a-cell causes the v-cell to flip. Here,any operation performed on the a-cell is accepted as a sensitizing operation for the fault,be it a read, a transition write or a non-transition write operation. The CFds consistsof 12 FPs: < 0w0; 0/1/− >, < 1w1; 0/1/− >, < 0w1; 0/1/− >, < 1w0; 0/1/− >,< 0r0; 0/1/− >, < 1r1; 0/1/− >, < 0w0; 1/0/− >, < 1w1; 1/0/− >, < 0w1; 1/0/− >,< 1w0; 1/0/− >, < 0r0; 1/0/− >, and < 1r1; 1/0/− >.

The CFv FFMs

This type has the property that the application of a single-port operation to thev-cell(with the a-cell in certain state) sensitizes a fault in the v-cell. It consists of thefollowing FFMs [25]:

1. Transition coupling fault(CFtr): Two cells are said to have a transitioncoupling fault if a given logic value in the aggressor results in a failing transitionwrite operation performed on the victim. This fault is sensitized by first setting thea-cell in a given state, and thereafter applying a write operation on the v-cell. TheCFtr consists of four FPs: < 0; 0w1/0/− >, < 1; 0w1/0/− >, < 0; 1w0/1/− >


and < 1; 1w0/1/− >.

2. Write Destructive coupling fault(CFwd): Two cells are said to have a writedestructive coupling fault if a non-transition write operation performed on thev-cell results in a transition when the a-cell is in a given logic state. The CFwdconsists of four FPs: < 0; 0w0/1/− >, < 1; 0w0/1/− >, < 0; 1w1/0/− > and< 1; 1w1/0/− >.

3. Read Destructive coupling fault(CFrd): Two cells are said to have a readdestructive coupling fault when a read operation performed on the v-cell changesthe data in the v-cell and returns an incorrect value on the output, if the a-cell isin a given state. The CFrd consists of four FPs: < 0; 0r0/1/1 >, < 1; 0r0/1/1 >,< 0; 1r1/0/0 > and < 1; 1r1/0/0 >.

4. Deceptive Read Destructive coupling faut(CFdrd): Two cells are said tohave a deceptive read destructive coupling fault when a read operation performedon the v-cell changes the data in the v-cell and returns a correct value onthe output, if the a-cell is in a given state. The CFdrd consists of four FPs:< 0; 0r0/1/0 >, < 1; 0r0/1/0 >, < 0; 1r1/0/1 > and < 1; 1r1/0/1 >.

5. Incorrect Read coupling fault(CFir): Two cells are said to have an incorrectread coupling fault if a read operation performed on the v-cell returns the incorrectlogic value when the a-cell is in a given state. Note here that the state of the v-cellis not changed. The CFir consists of four FPs: < 0; 0r0/0/1 >, < 1; 0r0/0/1 >,< 0; 1r1/1/0 > and < 1; 1r1/1/0 >.

3.4.2 Dynamic faults

These are faults requiring at least 2 operations in order to be sensitized while only 2operations are of interest here since the probability of dynamic faults decreases as thenumber of operations increases [68].

3.4.2.1 Single-cell dynamic faults

Single-cell dynamic faults consist of FPs sensitized by applying more than one operationto a single cell sequentially.

The exact compact notation for this fault will be presented prior to listing all the FMs.

The notation for single-cell dynamic fault is in the same form of single-cell staticfault, which is < S/F/R >; whereas the S involves two consecutive operations, whereby


S ∈ {xwyry, xrxwy, xwywz, xrxrx}(x, yandz ∈ {0, 1}), F∈ {0, 1}, and R ∈ {0, 1,−}.

Table 3.3 exhibits all possible combinations of < S/F/R > comprising the FPs andthe corresponding FFMs.

Table 3.3: The complete set of single-cell dynamic FPs

# S F R <S/F/R> FFM # S F R <S/F/R> FFM

1 0w0r0 1 1 <0w0r0/1/1> dRDF 2 1w0r0 1 1 <1w0r0/1/1> dRDF

3 0r0r0 1 1 <0r0r0/1/1> dRDF 4 1w1r1 0 0 <1w1r1/0/0> dRDF

5 0w1r1 0 0 <0w1r1/0/0> dRDF 6 1r1r1 0 0 <1r1r1/0/0> dRDF

7 0r0r0 1 0 <0r0r0/1/0> dDRDF 8 1r1r1 0 1 <1r1r1/0/1> dDRDF

9 0w0r0 1 0 <0w0r0/1/0> dDRDF 10 1w1r1 0 1 <1w1r1/0/1> dDRDF

11 0w1r1 0 1 <0w1r1/0/1> dDRDF 12 1w0r0 1 0 <1w0r0/1/0> dDRDF

13 0r0r0 0 1 <0r0r0/0/1> dIRF 14 1r1r1 1 0 <1r1r1/1/0> dIRF

15 0w0r0 0 0 <0w0r0/0/0> dIRF 16 1w1r1 1 0 <1w1r1/1/0> dIRF

17 0w1r1 1 0 <0w1r1/1/0> dIRF 18 1w0r0 0 1 <1w0r0/0/1> dIRF

19 0w0w1 0 - <0w0w1/0/-> dTF 20 1w1w0 1 - <1w1w0/1/-> dTF

21 0w1w0 1 - <0w1w0/1/-> dTF 22 1w0w1 0 - <1w0w1/0/-> dTF

23 0r0w1 0 - <0r0w1/0/-> dTF 24 1r1w0 1 - <1r1w0/1/-> dTF

25 0w0w0 1 - <0w0w0/1/-> dWDF 26 1w1w1 0 - <1w1w1/0/-> dWDF

27 0w1w1 0 - <0w1w1/0/-> dWDF 28 1w0w0 1 - <1w0w0/1/-> dWDF

29 0r0w0 1 - <0r0w0/1/-> dWDF 30 1r1w1 0 - <1r1w1/0/-> dWDF

Compiling all the 30 possible FPs will export a series of FMs, which are given below[53].

1. Dynamic Read Destructive Fault(dRDF): a write or a read operationfollowed immediately by a read operation performed on a cell changes the datain the cell, and returns an incorrect value on the output. The dRDF consistsof six FPs: < 0w0r0/1/1 >, < 1w0r0/1/1 >, < 0r0r0/1/1 >, < 1w1r1/0/0 >,< 0w1r1/0/0 > and < 1r1r1/0/0 >.

2. Dynamic Deceptive Read Destructive Fault(dDRDF): a write or aread operation followed immediately by a read operation performed on a cellchanges the data in the cell, and returns a correct value on the output. ThedDRDF consists of six FPs: < 0r0r0/1/0 >, < 1r1r1/0/1 >, < 0w0r0/1/0 >,< 1w1r1/0/1 >, < 0w1r1/0/1 > and < 1w0r0/1/0 >.

3. Dynamic Incorrect Read Fault(dIRF): a read operation performed immedi-ately after a write or after a read operation on a cell returns an incorrect valueon the output, while the cell remains in its correct state. The dIRF consists ofsix FPs: < 0r0r0/0/1 >, < 1r1r1/1/0 >, < 0w0r0/0/1 >, < 1w1r1/1/0 >,


< 0w1r1/1/0 > and < 1w0r0/0/1 >.

4. Dynamic Transition Fault(dTF): a transition write operation performedimmediately after a read or after a write operation fails. The dTF consists of sixFPs: < 0w0w1/0/− >, < 1w1w0/1/− >, < 0w1w0/1/− >, < 1w0w1/0/− >,< 0r0w1/0/− > and < 1r1w0/1/− >.

5. Dynamic Write Destructive Fault(dWDF): a non-transition write opera-tion applied immediately after a read or after a write operation causes the cellto flip. The dWDF consists of six FPs: < 0w0w0/1/− >, < 1w1w1/0/− >,< 0w1w1/0/− >, < 1w0w0/1/− >, < 0r0w0/1/− > and < 1r1w1/0/− >.

3.4.2.2 Two-cell dynamic faults

Two-cell dynamic faults consist of FPs sensitized by applying more than one operationsequentially to two cells: the aggressor(a-cell) and the v-cell. The a-cell is the cellto which the sensitizing operation(or state) should be a applied in order to sensitizethe fault, while the v-cell is the cell where the fault occurs. In a similar way asit has been done for single-cell faults, we restrict ourself to two-operation dynamicfaults. Depending on how many operations are applied to the a-cell and to the v-cell, and on the order in which they are applied, four types of S can be distinguished [53]:

1. Saa: the two sequential operations are applied to the a-cell; while the v-cell isrequired to be initialized in a certain state.

2. Svv: the two sequential operations are applied to the v-cell; while the a-cell isrequired to be in a certain state.

3. Sav: the first operation is applied to the a-cell, followed immediately with a secondone to the v-cell.

4. Sva: the first operation is applied to the v-cell, followed immediately with a secondone to the a-cell.

As the categorization of this kind of fault is complicated that no unique form ofnotation can be derived, we respectively probe above four situations regarding all thepossible FPs and their derivative FMs. Since the number of FPs are tremendous, onlythe notation characters, instead of the FPs table, will be provided.

Faults caused by Saa [53]

All the FPs conforming to Saa will be compiled into a single FFM called Dynamic Dis-turb Coupling Faults(dCFds), which means applying two successive operations to thea-cell causes the v-cell to flip. The FP is following the form of < vOvOv; v/v/− >, wherev is the logic value and O symbolizes an operation(here v can differ from each other).


Thus, FPs include 16 < awbwc;x/x/− >, 4 < arara; x/x/− >, 8 < arawb; x/x/− >and 8< awbrb; x/x/− >, where a,b and c∈ {0, 1}. Together of them yields 36 FPs,which are divided into four branch types:

1. dCFdsww: the two operations consist of a write followed with a write. The CFdsww

consists of 16 FPs: < 0w0w0;x/x/− >, < 1w1w1;x/x/− >, < 0w0w1;x/x/− >,< 1w1w0;x/x/− >, < 0w1w0;x/x/− >, < 1w0w1;x/x/− >, < 0w1w1;x/x/− >and < 1w0w0;x/x/− >, where x=0/1.

2. dCFdswr: the two operations consist of a write followed by a read. The CFdswr

consists of 8 FPs: < 0w0r0;x/x/− >, < 1w1r1;x/x/− >, < 0w1r1;x/x/− >,< 1w0r0;x/x/− >, where x=0/1.

3. dCFdsrw: the two operations consists of a read followed with a write. The CFdsrw

consists of 8 FPs: < 0r0w0;x/x/− >, < 0r0w1;x/x/− >, < 1r1w0;x/x/− > and< 1r1w1;x/x/− >, where x=0/1.

4. dCFdsrr: the two operations consist of a read followed with a read, which contains4 FPs: < 0r0r0;x/x/− >, < 1r1r1;x/x/− >, where x=0/1.

Faults caused by Svv [53]

All the FPs sensitized by Svv comprise of 16 < a; bwcwd/d/− >, 8 < a; brbwc/c/− >,4 < a; brbrb/b/b >, 4 < a; brbrb/b/b >, 4 < a; brbrb/b/b >, 8 < a; bwcrc/c/c >, 8< a; bwcrc/c/c > and 8 < a; bwcrc/c/c >, where a/b/c/d∈ {0, 1}. Together of themyields 60 FPs, which are divided into four branch types: are compiled into a set of fiveFFMs, in which x∈{0,1}.

1. Dynamic Read Destructive Coupling Fault(dCFrd): a write or a read fol-lowed immediately by a read operation performed on the v-cell changes the data inthe v-cell and returns an incorrect value on the output, if the a-cell is in a certainspecific state. The dCFrd consists of 12 FPs: < x; 0r0r0/1/1 >, < x; 1r1r1/0/0 >,< x; 0w0r0/1/1 >, < x; 1w1r1/0/0 >, < x; 0w1r1/0/0 > and < x; 1w0r0/1/1 >.

2. Dynamic Deceptive Read Destructive Coupling Fault(dCFdrd): a writeor a read followed immediately by a read operation performed on the v-cell changesthe data in the v-cell and returns a correct value on the output, if the a-cell isin a certain specific state. The dCFdrd consists of 12 FPs: < x; 0r0r0/1/0 >,< x; 1r1r1/0/1 >, < x; 0w0r0/1/0 >, < x; 1w1r1/0/1 >, < x; 0w1r1/0/1 > and< x; 1w0r0/1/0 >.

3. Dynamic Incorrect Read Coupling Fault(dCFir): a write or a read followedimmediately by a read operation performed on the v-cell returns an incorrect value


on the output, while the v-cell remains in its correct state, if the a-cell is in a certainspecific state. The dCFir consists of 12 FPs: < x; 0r0r0/0/1 >, < x; 1r1r1/1/0 >,< x; 0w0r0/0/1 >, < x; 1w1r1/1/0 >, < x; 0w1r1/1/0 > and < x; 1w0r0/0/1 >.

4. Dynamic Transition Coupling Fault(dCFtr): a write or a read followed im-mediately by a transition write operation performed on the v-cell results in afailing write operation if the a-cell is in a certain specific state. The dCFtr con-sists of 12 FPs: < x; 0w0w1/0/− >, < x; 1w1w0/1/− >, < x; 0w1w0/1/− >,< x; 1w0w1/0/− >, < x; 0r0w1/0/− > and < x; 1r1w0/1/− >.

5. Dynamic Write Destructive Coupling Fault(dCFwd): a write or a readfollowed immediately by a non transition write operation performed on the v-cellcause that cell to flip, if the a-cell is in a certain specific state. The dCFwdconsists of 12 FPs: < x; 0w0w0/1/− >, < x; 1w1w1/0/− >, < x; 0w1w1/0/− >,< x; 1w0w0/1/− >, < x; 0r0w0/1/− > and < x; 1r1w1/0/− >.

Faults caused by Sav [53]

In this mechanisms because two operations take place sequentially in different cells, weneed to clarify that the sensitizing operation involved in FPs are placed according totheir time order. In other words, we use < Sa;Sv/F/R > to represent an FP where Sa

happens before Sv.

The FPs consist of 4 < ara; brb/b/b >, 4 < ara; brb/b/b >, 4 < ara; brb/b/b >, 8< awb; crc/c/c >, 8 < awb; crc/c/c >, 8 < awb; crc/c/c >, 8 < ara; bwc/c/− >, 16< awb; cwd/d/− >, where a/b/c/d∈ {0, 1}. Together of them yields 60 FPs, which aredivided into four branch types: are compiled into a set of five FFMs, in which we adoptxOy(x/y ∈{0,1}) to denote all possible static operations.

1. Dynamic Read Destructive Coupling Fault(dCFrd): The dCFrd consists of12 FPs: < xOy; 0r0/1/1 > and < xOy; 1r1/0/0 >.

2. Dynamic Deceptive Read Destructive Coupling Fault(dCFdrd): ThedCFrd consists of 12 FPs: < xOy; 0r0/1/0 > and < xOy; 1r1/0/1 >.

3. Dynamic Incorrect Read Coupling Fault(dCFir): The dCFrd consists of 12FPs: < xOy; 0r0/0/1 > and < xOy; 1r1/1/0 >.

4. Dynamic Transition Coupling Fault(dCFtr): The dCFrd consists of 12 FPs:< xOy; 0w1/0/− > and < xOy; 1w0/1/− >.

5. Dynamic Write Destructive Coupling Fault(dCFwd): The dCFrd consistsof 12 FPs: < xOy; 0w0/1/− > and < xOy; 1w1/0/− >.

3.5. ADDRESS DECODER FAULTS 43

Faults caused by Sva [53]

This is the symmetric case for that of Sav where only the sensitizing operations areperformed in an inversed order, which means a basic FP is like < Sv;Sa/F/R >, butwithout the footnote we can’t distinguish the first element is Sv or Sa, so we modify itinto a format as < Sv/F/R;Sa >.

The FPs consist of 4 < brb/b/b; ara >, 4 < brb/b/b; ara >, 4 < brb/b/b; ara >, 8< crc/c/c; awb >, 8 < crc/c/c; awb >, 8 < crc/c/c; awb >, 8 < bwc/c/−; ara >, 16< cwd/d/−; awb >, where a/b/c/d∈ {0, 1}. Together of them yields 60 FPs, which aredivided into four branch types: are compiled into a set of five FFMs, in which we adoptxOy(x/y ∈{0,1}) to denote all possible static operations.:

1. Dynamic Read Destructive Coupling Fault(dCFrd): The dCFrd consists of12 FPs: < 0r0/1/1;xOy > and < xOy/0/0; 1r1 >.

2. Dynamic Deceptive Read Destructive Coupling Fault(dCFdrd): ThedCFrd consists of 12 FPs: < 0r0/1/0;xOy > and < 1r1/0/1;xOy >.

3. Dynamic Incorrect Read Coupling Fault(dCFir): The dCFrd consists of 12FPs: < 0r0/0/1; xOy > and < 1r1/1/0;xOy >.

4. Dynamic Transition Coupling Fault(dCFtr): The dCFrd consists of 12 FPs:< 0w1/0/−;xOy > and < 1w0/1/−; xOy >.

5. Dynamic Write Destructive Coupling Fault(dCFwd): The dCFrd consistsof 12 FPs: < 0w0/1/−;xOy > and < 1w1/0/−; xOy >.

Till now, all the FFMs of interest in memory cell array are presented and we restrictour scope to static/dynamic-simple-(single port)-(single/multi cell)-faults where the‘multi-’ is simplified as 2.

3.5 Address decoder faults

Address decoder faults are faults that take place in the decoding circuitry of therow and the column address decoders in the memory. Two different classes of addressdecoder faults(ADFs) can be identified: Static ADFs and Dynamic ADFs. Both ofthese classes are discussed in the successive two sections.

3.5.1 Static address decoder faults

Static ADFs take place when an open defect (increased line resistance) along anaddress decoder line causes a fully broken connection to the cell and/or a short causes


multiple lines to be connected to each other. In the following are the only staticADFs traditionally considered to occur in address decoders, defined in [17], which isillustrated by Figure 3.4 [17]:

xx

Cy

Ax

Ay

C

Fault1 Fault2 Fault3 Fault4

Ax CxAy

C

Figure 3.4: Static address decoder faults

1. Fault1: With a certain address, no cell will be accessed.

2. Fault2: There is no address with which this cell can be accessed. That is to say,a certain cell is never accessed.

3. Fault3: With a certain address, multiple cells are accessed simultaneously.

4. Fault4: A certain cell can be accessed with multiple addresses.

Because there are as many cells as addresses, none of the above faults can standalone. They can occur in one of the following combinations [31]; see Figure 3.5:

xCx x

AyCy

CxAx

AyCy

CAx

AF nca AF nmc AF nma AF mca

Ay

Cx

yC

Ax A

Figure 3.5: Combinations of static address decoder faults

1. Fault AFnca: It is a combination of Fault 1 and 2, called a no cell and no addressfault.

2. Fault AFnmc: It is a combination of Fault 1 and 3, called a no cell and multiplecell fault.

3. Fault AFnma: It is a combination of Fault 2 and 4, called a no address and multipleaddress fault.

3.5. ADDRESS DECODER FAULTS 45

4. Fault AFmca: It is a combination of Fault 3 and 4, called a multiple cell andmultiple address fault.

To describe AFs, the following notation can be used [31]:

< S/F > denotes an AF fault where S describes the condition for sensitizing thefault; i.e., which address has to be selected in order to sensitize the fault. The capital let-ters of the alphabet (i.e., A through Z) denote memory addresses. Thus S ∈ {A,B, ..., Z}.

F describes the fault effect; e.g., a cell which is erroneously accessed or not accessed.The lower case letters of the alphabet (i.e., a through z) denote memory cells when theyare accessed and their inversions (i.e., a through z) denote memory cells when they arenot accessed. Thus F ∈ {a, b, ..., z}⋃{a, b, ..., z}.

When both two addresses breed faults, then it will be given as follows:< S1/F > # < S2/F >, whereby S1 is one address and S2 is the other.

Based on the above introduced notation, the faults of Figure 3.5 are represented asfollows [31]:

• AFnca :< X/x >.

• AFnmc :< X/x > # < Y/x >.

• AFnma :< Y/x, y >.

• AFmca :< Y/x >.

3.5.2 Dynamic address decoder faults

Dynamic address decoder faults are also referred to as Dynamic ADFs, where ‘Dy-namic’ means the fault is a delay fault and thus timing related [52, 5, 39, 56]. They arecaused by partial (resistive) opens along the lines of the address decoder that are notstrong enough to break the line, but merely cause the signal traveling along the line tobe delayed. This phenomenon has been deeply probed in chapter 2 where we say anyvoltage variation is due to the charge/discharge of node capacitor and the working timeof this is, to great extent, affected by the resistance along the line.

Reflecting both charge and discharge process of a word line, this delay fault can becategorized into two classes, shown in Figure 3.6 [56]:

1. Activation delay faults: This is the fault that the rising edge of the voltage online lags behind where it is supposed to be.

2. Deactivation delay faults: This is the fault that the falling edge of the voltageon line lags behind where it is supposed to be.


Figure 3.6: Activation and deactivation delay faults

3.6 Peripheral circuit faults

Peripheral circuit faults(PCFs) are those faults that take place in memory circuitryother than the memory cell array and the address decoders. These faults can be eitherstatic or dynamic.

3.6.1 Static peripheral circuit faults

Static peripheral circuit faults are non-speed-related faults in the periphery circuits,which means write drivers, sense amplifiers or precharge circuits do not exert itsfunction. Such faults can be totally mapped to static memory cell array faults, thus notto be repeated with details.

3.6.2 Dynamic peripheral circuit faults

Dynamic peripheral circuits faults are speed related faults in the periphery, due to theslow operation of write drivers, sense amplifiers and precharge circuits. The four maintypes of dynamic PCFs are the following fault models:

1. Slow Write Driver Fault(SWDF) [66]: The write driver may be too slow dueto a defect in the driver circuit and/or due to resistive defects(such as partial openvias) in its path to the cells. This results in reducing the differential voltage on thebit lines(BLs) during the write operation, which may cause the write operation tofail.

2. Slow Sense Amplifier Fault(SSAF) [66]: The sense amplifier may be tooslow, or is asymmetric(because of some offset voltage) due to a defect in thesense amplifier circuits and/or due to resistive defects in the path from the cellto the sense amplifier. This may cause read operations to produce incorrect results.

3.7. FAULTS RELATED TO MEMORY ARCHITECTURE 47

3. Slow PRecharge circuit Fault(SPRF) [3, 58]: The precharge circuit maybe too slow, or it may not precharge both BLs to the same voltage level, dueto defects in the precharge circuitry and/or due to resistive defects in the BLs.The result may be that especially read operations will produce incorrect results,because they are most sensitive to BL voltage offset errors.

4. Bit Line Imbalance Fault(BLIF) [66]: With decreasing feature widths, thetransistors increasingly draw more current in the off-state. This also applies to thepass transistors, which means(for NMOS pass transistors) even if the WLs(wordlines) are set to 0, the pass transistors are still in a semi-conduction state underwhich current may pass between BL(bit lines) and cells; this kind of current iscalled leaky current. This may impact the possibility of reading the correctvalue of a cell(write operations are less sensitive). The worst case situation occurswhen a ‘rx’ operation is applied to a cell, which is the only cell in that columncontaining the value ‘x’. Then, while reading the cell storing ‘x’, the cells storing‘x’ will ‘feel’ the variation of voltage on BLs and transport currents to compensatethe change through the leaky pass transistors. As the number of cells containing‘x’ are overwhelming, the incorrect ‘x’ value may be read out. This fault is calledbit line imbalance fault.

3.7 Faults related to memory architecture

Faults related to memory architecture may and may not occur in the memory, dependingon its architecture. Such faults can be divided into:

• Word-oriented memory faults [63, 67]

• Byte-write-enable faults [4, 54]

Below each of the above fault classes is discussed separately.

3.7.1 Word-oriented memory(WOM) faults

SRAMs can be organized as bit-oriented memories (BOMs) or as word-orientedmemories (WOMs). WOMs contain more than one bit per addressable word; i.e., B>2,whereby B represents the number of bits per word, and B usually is a power of 2.Read operations read B bits simultaneously, while write operations write B data bitssimultaneously; where the data to be written in each cell can be specified independentlyfrom the data for the other cells in the same word [55]. Fault models for WOMs canbe divided into the single-cell faults and multi-cell faults where ‘multi’ is restricted to 2and both faults are referring to static faults in space of this section.


3.7.1.1 Single-cell faults

The single-cell-static faults discussed before are all addressed inWOMs [2] [8] [49] [28] [17], which we enumerate below and won’t repeat the de-tails:

1. State Fault(SF)2. Transition Fault(TF)3. Write Destructive Fault(WDF)4. Read Destructive Fault(RDF)5. Deceptive Read Destructive Fault(DRDF)6. Incorrect Read Fault(IRF)7. Data Retention Fault(DRF)

3.7.1.2 Two-cell faults

This class of faults involve the “two-cell static faults” explored in section 1 [8] [28] [25],which are presented below:

1. State coupling fault(CFst)2. Disturb coupling fault(CFds)3. Transition coupling fault(CFtr)4. Write Destructive coupling fault(CFwd)5. Read Destructive coupling fault(CFrd)6. Deceptive Read Destructive coupling faut(CFdrd)7. Incorrect Read coupling fault(CFir)

The above CFs can be further partitioned into two groups:.

1. Inter-word faults: These are faults where the a-cell and the v-cell belong todifferent words.

2. Intra-word faults: These are faults where the a-cell and the v-cell belong to thesame word.

The necessity of above division ascribes to that classical BOM tests with commonlyadopted DBs(data backgrounds)are based on inter-word faults while can not fully coverintra-word faults, which will be probed in next chapter.

3.7.2 Bit/Byte-write-enable faults

Today ASICs and SoCs have become increasingly embedded memory intensive. It isvery common to have tens if not hundreds of embedded SRAMs with different sizesand types(e.g., single-port, multi-port), performing different functions on a single chip.The wide use of SRAMs in different applications means that new functionalities have

3.7. FAULTS RELATED TO MEMORY ARCHITECTURE 49

to be added to such memories in order to satisfy the design requirements. One of suchfunctionalities is the ability of the SRAM to perform bit and byte write operations. Inaddition, words may be arranged as groups of bits having different number of data bitsthan a standard byte. The memory may also have the ability to write such groups ofdata. This is realized by using specific enable control circuitry that enables or disablesthe writing circuitry of the associated bits in the data words. Such circuitry needsto be tested for different kinds of defects as compared with the memory array, andusing specific test sequences. Thus, we will in turn introduce the bit/byte write enablecircuitry with Fig 3.7, based on which the FMs will be discussed.

3.7.2.1 Bit/Byte write enable circuitry

Data bit B−1

BWE

BWE 1

BWE B−1

Column

Column address

decoder

GWE

0

Data bit 1

Data bit 0

Figure 3.7: Typical bit write enable circuitry

There are two possible locations to implement the bit/byte write enable circuits,either in the beginning of input data path or at its end [51]. Figure 3.7 [54]shows atypical implementation of bit/byte write circuits when implemented at the beginningof input of data path; i.e., the circuit is implemented before the column decoder.The data word to be written is controlled by (a) a global write enable GWE, whichenables or disables the word to be written, and (b) bit write enables BWEi whichare associated one-to-one with each data bit of the word and therefore control-ling whether the data bit i (i∈ {0, 1, ...B − 1}; B is the word size) to be written. Adata bit is written into memory if both GWE and its corresponding BWEi are both high.


3.7.2.2 Bit/Byte write enable circuitry

The BWE controls/mask signals are often routed close to each other and thereforesubject to manufacturing defects, which is the case for the memory cell array. Examplesare shorts to Vdd and GND, and bridges between neighboring lines. In the presence ofopens in such circuits, the whole writing path will be impacted and therefore detectablewith the test of address decoder (delay) faults [36] [52] [11] [40] [56]. Therefore, we onlyconfine our sight to shorts and bridges.

Let us define a short as undesired resistive path between a control line (e.g., BWE)and Vdd or GND, denoted as BWE+ and BWE− respectively. On the other hand,let us define a bridge as an undesired resistive path between two control lines bothdifferent from Vdd and GND (e.g., BWE0 bridged with BWE1; see Figure 3.7). Onlybridges involving two lines will be considered since their occurrence probability is veryhigh compared with bridges involving more than two lines; Moreover, a test targeting abridge involving two lines also covers some multi-line bridges.

Consider a BWE control circuit with B BWE control signals. As the topologyof the circuit and the position of the lines are usually not known, all possible faultmodels(shorts and bridges) have to be considered for testing. These are [54]:

• Wired-AND BWE bridges: there are CB2 = B!

2!(B−2)! possibilities of such bridges.

• Wired-OR BWE bridges: there are CB2 = B!

2!(B−2)! possibilities of such bridges.

• BWE+(BWE shorted to Vdd): there are B possibilities of such shorts.

• BWE−(BWE shorted to GND): there are B possibilities of such shorts.

In total there are 2CB2 + 2B = B(B + 1) possible functional faults.

3.8. SUMMARY 51

3.8 Summary

Other than testing logic systems, memory testing relies on the establish and developmentof fault models to a great extent. Therefore, this chapter serves the base to proceedfurther discussion of memory testing.

The division into different functional modules of a memory greatly simplify the rela-tionship of different functional fault models, with which it becomes convenient to studyone class of fault models that occur in one functional module. In addition, the develop-ment of the concept of fault primitives contributes significantly to memory testing, sinceit systemize the definition of specific faults; also ascribing to which, the development ofa test algorithm targeting one fault becomes a structurized process. Consequently, withthe background of this chapter, one begins to step into the key world of memory testing.

Test Primitive Generation 4Fault diagnosis is becoming an increasingly important topic for memory devices toreduce the time in yield improvement. On the one hand, fault diagnosis can specifythose faults with high occurrence probability, which is helpful to optimize former testsand thus reduce the test cost. On the other hand, the on-going fragmentation of theIC production process forces memory designers, memory manufacturers and test-serviceproviders to use standardized, easy-to-implement test methods that enables effectivetransfer of test information between different companies [12].

Diagnostic testing for memory devices has been studied by many researchers in thepast. David proposed a fault diagnosis method based on running pseudo-random testexperiments and comparing pass/fail data with statistically generated fault probabilities[16]. This method is not deterministic and rather time consuming in terms of testtime. Yarmolik presented a diagnostic memory test that is able to distinguish betweena number of specific fault models by recording the read operation that resulted infirst memory fail [64]. Niggemeyer [15] and then Li [34] introduced the idea of faultdiagnosis using output tracing, which involves keeping track of the pass/fail informationof every read operation in the diagnostic test, thereby generating a signature for eachfault. These tests are hard to implement in normal test platforms. More recently, basedon the concept of fault primitives [9], a plenty of diagnostic methods were introduced insuch as [22, 60], whereas these methods are hardwired to a specific predefined diagnostictest and any modifications to the set of targeted tests needs a new diagnostic test alongwith a new set of fault signatures.

In this chapter, we adopt a new developed concept of Test Primitive (TP) fordiagnosis. This chapter is organized as follows: Section 4.1 introduces the concept oftest primitive; Section 4.2 focuses on the generation procedure of test primitives; Section4.3 presents the diagnostic dictionary of test primitives for single-cell static faults;Section 4.4, by introducing the concept of combined test primitive (CTP), explores theTPs for single-cell dynamic faults; Section 4.5 presents the diagnostic dictionary forsingle-cell static and dynamic faults; Section 4.6 ends the chapter with a summary.

Section 4.1 Concept of Test PrimitiveSection 4.2 Test primitive generation procedureSection 4.3 Test primitives for single-cell static faultsSection 4.4 Test primitives for single-cell dynamic faultsSection 4.5 Diagnostic dictionary for single-cell faultsSection 4.6 Summary

53

54 CHAPTER 4. TEST PRIMITIVE GENERATION

4.1 Concept of Test Primitive

Prior to discussing TP, the march test notation will be introduced, since the TP sharesthe same notation method with the march test. In addition, the advantages of TP arealso provided within this section.

4.1.1 March test notation

A march test consists of a finite sequence of march elements [61]. A march elementis a finite sequence of operations applied to every cell in the memory before proceedingto the next cell. The way one proceeds to the next cell is determined by the addressorder which can be an increasing address order (e.g., increasing address from the cell0 to the cell n-1), denoted by ⇑ symbol, or a decreasing address order, denoted by ⇓symbol, which is the exact inverse of the ⇑ address order. When the address order isirrelevant, the symbol m (i.e.,⇑ or ⇓) will be used.

An operation can consist of:

• w0: write 0 into a cell.

• w1: write 1 into a cell.

• r0: read a cell with expected value 0.

• r1: read a cell with expected value 1.

A complete march test is delimited by the ‘{· · · }′ bracket pair; while a march elementis delimited by the ‘(· · · )′ bracket pair. The march elements are separated by semicolons,and the operations within a march element are separated by commas. For instance, theMATS+ march test [1] {m (w0);⇑ (r0, w1);⇓ (r1, w0)} consists of three march elementsm (w0),⇑ (r0, w1) and ⇓ (r1, w0); i.e. the first march element initiates all the memorycells to 0; the second march element reads 0 followed by writing 1 to each cell and thethird march element is similar to the second march element, but it uses a complementarydata and a decreasing address order.

4.1.2 Philosophy of TP

A TP is the march test designed, when possible, to target two criterias. The first is thatthe TP should detect a targeted single fault primitive (SFP), and the second is thatthe TP should contain the minimum number of operations to detect the targeted faultprimitive (FP) and therefore has a minimum test length (MTL). SFP is to facilitatefurther diagnostic purpose and MTL is to save test cost. Bear in mind that SFP is notalways imperative since it is not practical in some cases; i.e. when two FPs share thesame detection condition, a TP for one FP will surely detect another one. For example,given an FP1 = < 0w1/0/− > (i.e., one of the single-cell transition fault (TF)), theTP targeting FP1 is TP1 {m (w0);m (w1);m (r1)}. However, TP1 also detects otherFPs such as the read destructive fault < 1r1/0/0 >. Hence, the SFP criteria is not

4.1. CONCEPT OF TEST PRIMITIVE 55

satisfied. In addition, in some cases targeting the SFP criteria will require additionaltest operations to be able to insulate the FP from other FPs, which makes MTLimpractical. In this case, we recommend to endue the SFP with the priority to MTLbecause the purpose of TP concept is diagnosis while not detection. An example willbe shown in Section 4.4.3, where an additional read 0 operation is required to diagnoseTdRDF1.

The second requirement that should sink into our mind is to generate a TP as shortas possible, since the length of a TP directly determines our testing cost, which is theterminal interest we are engaged in. Nevertheless, there are hundreds, if not thousandsin the future, of FPs with potential existence; thus to tell whether a TP is short enoughfor an FP, by estimating them one by one without a regularity, is quite time consumingand may lead to inaccurate results. To crack this problem, a systematic methodcalled TP Evaluator is created. TP Evaluator is a group of formulas to manifestexactly the minimum number of operations required to constitute a TP for a targeted FP.

Prior to presenting the content of TP Evaluator, we should have a review of thenotation of FPs. Notice that the following notations are general forms which symbolizeboth static and dynamic FPs and the detailed meaning won’t be repeated, in additionto which, for dynamic faults the operations distributed respectively in a-cell and v-cellare not in our scope. For a single-cell FP, it is denoted by < S/F/R >; for a two-cellFP, it is represented as < Sa; Sv/F/R >, whereby Sa and Sv stand for global conditionsthat both static and dynamic cases are included. Two-cell FPs are again divided intotwo classes: if all operations only exist in Sa while Sv merely contains a state, thecorresponding FP is viewed as < Sa; Svs/F/R > where the ‘vs’ means ‘victim-state’;reciprocally the FP is reckoned as < Sas;Sv/F/R >. Based on such a classification andthen denoting the smallest number of a TP to be N, the TP Evaluator is presented below:

1. For < S/F/R >:

N= The number of values in ‘S’ +1 -1(if the final operation in ‘S’ is rx) +1(if R=x)

2. For < Sa; Svs/F/R >:

N= The number of values in “Sa + Svs” +1 -1(if the value of ‘Svs’ equals the firstor last value in ‘Sa’) -1(if the first operation in ‘Sa’ is rx and x is the value of ‘Svs’)

3. For < Sas; Sv/F/R >:

N= The number of values in “Sas + Sv” +1 -1(if the value of ‘Sas’ equals the firstor last value in ‘Sv’) -1(if the final operation in ‘Sv’ is rx) +1(if R=x)

This evaluator is applicable concerning both single-cell and two-cell cases and bothstatic and dynamic faults, more global than which is that the number of operations of a


dynamic fault are limitless; i.e., not restricted to be 2. Next, a couple of examples areprovided for instantiation:

1. For < S/F/R >, given an FP as < 0w1r1/0/1 >, which is the FP of a single-cell dynamic(deceptive read destructive) fault, the number of its values in ‘S’ is3(0,1,1), the final operation in ‘S’ is r1 and R=1, so N= 3+1-1+1=4. That is tosay, we need at least 4 operations in a TP to detect such a fault; a typical one is{m (w0);m (w1, r1);m (r1)}. In comparison, if an FP like < 0w1w0/1/− > is given,where the final operation in ‘S’ is not rx, then its N=3+1=4, whose correspondingTP should be {m (w0);m (w1, w0);m (r0)}.

2. For < Sa; Svs/F/R >, given an FP as ↓< 1r1w0; 1/0/− >, which is the FP of adynamic disturb coupling fault, the number of its values in “Sa +Svs” is 4(1,1,0,1),the value of ‘Svs’ equals the first value in ‘Sa’, the first operation in ‘Sa’ is r1and 1 is the value of ‘Svs’, so N=4+1-1-1=3. I.e., only 3 operations are requiredto detect this fault, the TP of which can be {m (w1);⇓ (r1, w0)}. Unlike suchan extreme situation, another FP of ↓< 1w0w1r1; 0/1/− > is taken into account,whose number of values in “Sa + Svs” is 5(1,0,1,1,0); though the value of ‘Svs’ isincluded in ‘Sa’, it’s neither the first nor the last value of ‘Sa’; in addition, there is aread operation in ‘Sa’ while it’s not the first operation; consequently, its N=5+1=6,reflecting that we will fail to find a TP shorter than 6 operations length, and theTP can be {m (w0);⇓ (r0, w1, w0, w1, r1)} or {m (w1);⇑ (w0, w1, r1, w0);m (r0)},both are comprising of 6 operations, and these are the shortest TPs one can derive.

3. For < Sas; Sv/F/R >, given an FP as ↑< 1; 0w1r1/0/1 >, which is the FP ofa dynamic deceptive read destructive coupling fault, the number of its values in“Sas + Sv” is 4(1,0,1,1), the value of ‘Sas’ equals the last value in ‘Sv’, and thefinal operation in ‘Sv’ is r1 while R=1, so N=4+1-1-1+1=4. In other words, wehave to use no less than 4 operations to detect this fault, the TP of which can be{m (w0);⇑ (w1, r1);m (r1)}. In contrast, one can use another TP to detect it suchas {m (w1);⇓ (w0, w1, r1);m (r1)}, but this one contains 5 operations.

In the following space, we will respectively prove the correctness of equation 1, 2 and3 of TP Evaluator.

1. For < S/F/R >:

Given any single-cell FP of < S/F/R >, it can be detailed as <x1Ox2 · · ·Oxn/F/R >, where xn, F and P are values and ‘O’ stands for an op-eration like r or w. As ‘S’ in an FP symbolizes the sensitizing operations forthis fault, to sensitize it, we should construct a TP by copying all operationsin ‘S’ following the initialization operation of the first value x1; since our de-tection is through external observation, one more read operation is supposed tobe added in the end. Therefore each TP should be constructed in the form of{m (wx1);m (Ox2Ox3 · · ·Oxn);m (rxn)}, which contains n+1 operations, corre-sponding to the item “The number of values in ‘S’ +1” in equation 1. Nevertheless,


if ‘Oxn’ itself is already ‘rxn’, then the m (rxn) in the end is redundant and thuscan be removed, so the item “-1(if the final operation in ‘S’ is rx)’ is incorporatedin equation 1; furthermore, if R = xn, which means the m (rxn) observes a correctvalue while the inner value of the cell is faulty, then we need one more m (rxn) to‘view’ this fault, and this is the reason to add the item “+1(if R=x)” in equation1. No more operations can be further changed, so equation 1 is proved.

2. For < Sa; Svs/F/R >:

Adopting similar denotations above, the < Sa; Svs/F/R > can be detailed as↑< x1Ox2 · · ·Oxn; y/F/R > (the ↓ case is symmetric and thus omitted). Nextwe will obtain the demonstration with the help of a tree graph, which is drawnaccording to following principles. The tree begins with the number of values in“Sa + Svs” +1; i.e., n+1+1=n+2; then the two conditions shown in brackets ofequation 2 are converted to two phases of the tree graph; each phase consistsof different fan outs that correspond to all possible situations; in addition, thecorresponding calculation of operation numbers such as “-1” or “+1” is addedbeside the fan out. Thereby, different branches of the tree are formed by tracingfrom the beginning node to different ends, and each branch represents one possiblecase of < Sa; Svs/F/R >; finally, N (the minimum number of operations) isindicated at the end of each branch. In such a way the tree is completed and allthe possible cases of < Sa;Svs/F/R > are exactly mirrored to all the branches,as is shown in Figure 4.1. For each fan out at each phase, if each calculation canbe carried out and no any other calculation can be carried out, then N can berealized and can not be reduced any further. This guarantees the proof to be bothefficient and necessary.

According to the proof in Equation 1, at the beginning node, n+2 is the basicnumber of operations, and the TP can be {m (wy);⇑ (rywx1Ox2 · · ·Oxn)}. Thenin the first phase the beginning node fans out to be two cases. In the first case,when y=x1; i.e., the value of ‘Svs’ equals the first value in ‘Sa’, the TP can bereduced to {m (wy);⇑ (ryOx2 · · ·Oxn)}, where the wx1 is removed, correspondingto the “(-1)” symbol; when y=xn; i.e., the value of ‘Svs’ equals the last value in‘Sa’, the TP can be reduced to {m (wx1);⇓ (Ox2 · · ·Oxn);m (rxn)}, where the wyis removed, corresponding to the “(-1)” symbol; moreover, when y=x1=xn, eitherone of above reductions can be carried out but can not be carried out both dueto the contradiction of positions in a march element; consequently “(-1)” can becarried out and only can be carried out once if the value of ‘Svs’ equals the firstor the last value in ‘Sa’, which proves the first case in the first phase of the tree.In the second case, when y 6= x1

⋂y 6= xn, above reduction can not be carried out;

meanwhile if y=x2 · · ·xn−1, no reduction can be carried out either, because thosevalues are hidden in the middle of a march operation that can not be utilized to omitthe “wy” operation; therefore no reduction can be carried out if the value of ‘Svs’neither equals the first nor the last value in ‘Sa’. Thereafter we move to the secondphase of the tree. In the first case, when Ox2 = ry; i.e., if the first operation in ‘Sa’


is rx and x is the value of ‘Svs’, the TP can be reduced to {m (wy);⇑ (Ox2 · · ·Oxn)},where one ry is removed, corresponding to the “(-1)” symbol, which proves the firstcase in the second phase. In the second case, when Ox2 6= ry, no reduction can becarried out because any other operations in Ox3 · · ·Oxn are not in the beginningand thus can not serve as the observation operation ry, which proves the secondcase in the second phase. As a result, Equation 2 is proved.

Ox2=ry

n

1

U

n+2

(−1)(−1)

y=x y=xn

Ox2=ry

Ox2=ry

(N=n)

(N=n+1)1

(N=n+2)

y=x U y=x

Figure 4.1: Tree graph of equation 2

3. For < Sas;Sv/F/R >:

Adopting similar denotations above, the < Sas; Sv/F/R > can be detailed as↑< x; y1Oy2 · · ·Oyn/F/R > (the ↓ case is symmetric and thus omitted). Also, weresort to its corresponding tree graph for illustration, which is shown in Figure4.2. The denotation and the utility of the tree is as the same as depicted aboveand will not be repeated.

According to the proof in Equation 1, at the beginning node, n+2 is the basicnumber of operations, and the TP can be {m (wx);⇓ (wy1Oy2 · · ·Oynryn}. Thenin the first phase the beginning node fans out to be two cases. In the first case,when x=y1; i.e., the value of ‘Sas’ equals the first value in ‘Sv’, the TP can bereduced to {m (wx);⇓ (Oy2 · · ·Oynryn}, where the wy1 is removed, correspondingto the “(-1)” symbol; when x=yn; i.e., the value of ‘Sas’ equals the last value in‘Sv’, the TP can be reduced to {m (wy1);⇑ (Oy2 · · ·Oynryn)}, where the wx isremoved, corresponding to the “(-1)” symbol; moreover, when x=y1=yn, eitherone of above reductions can be carried out but can not be carried out both dueto the contradiction of positions in a march element; consequently “(-1)” can becarried out and only can be carried out once if the value of ‘Sas’ equals thefirst or the last value in ‘Sv’, which proves the first case in the first phase of thetree. In the second case, when x 6= y1

⋂x 6= yn, above reduction can not be carried

out; meanwhile if x=y2 · · · yn−1, no reduction can be carried out either, becausethose values are hidden in the middle of a march operation that can not be utilizedto omit the “wx” operation; therefore no reduction can be carried out if the valueof ‘Sas’ neither equals the first nor the last value in ‘Sv’. Thereafter we move tothe second phase of the tree. In the first case, when Oyn = ryn; i.e., if the finaloperation in ‘Sv’ is rx, the TP can be reduced to {m (wx);⇓ (wy1Oy2 · · ·Oyn},where ryn is removed, corresponding to the “(-1)” symbol, which proves the first


case in the second phase. In the second case, when Oyn 6= ryn, no reduction canbe carried out because the observation must be assigned to the end of Oyn, whichproves the second case in the second phase. More important, as the second phase isindependent to the first phase, such proof can also be applied to the third and fourthcase in the second phase. Then we move to the third phase. In the first case, whenyn = R, the TP must be incremented as {m (wx);⇓ (wy1Oy2 · · ·Oynryn;m (ryn)},where one more ryn is added to detect the deceptive fault. In the second case thisis not needed. More important is that the third phase is also independent to phase1 and 2, so such proof can be applied to the third through eighth case of the thirdphase. As a result, Equation 3 is proved.

nOy = ryn

ny = R

ny = R

nOy = ryn

ny = R

ny = R

nOy = ryn

ny = R

ny = R

nOy = ryn

ny = R

ny = R

1 nx=y x=y

U

n+2

(−1)

(−1)(+1)

(+1)

(−1)(+1)

(+1)

(N=n+1)

(N=n)

(N=n+2)

(N=n+1)

(N=n+2)

(N=n+1)

(N=n+3)

1

(N=n+2)

x=y U x=y n

Figure 4.2: Tree graph of equation 3

Consequently, above demonstration has explored all cases of each FP by followingeach branch of the tree graph, and it proved that each reduction is applicable and nomore reduction can be applied for each case. Therefore, Equation 1 through Equation 3are all proved.

4.1.3 Importance and Purpose of TP

The purpose of TP concept mainly lies in the diagnostic realm. Compared with previousdiagnostic methods, TP manifests its advantages in following aspects.

• Extensibility: new FPs can be added to the diagnostic process if desired, withoutaffecting the diagnosis of already existing FPs.

• Platform independence: TPs are applied in the same regular way as any detect-ing memory test is applied to the memory. There is no extra memory needed tostore test signatures, neither the specific read operation failing. This makes themimplementable on any memory test platform irrespective of its capabilities. The


only thing needed is to store pass/fail data of the whole set of test primitives toperform the diagnosis.

• Unknown fault identification: Some combinations of failing TPs might not bedescribed by any known fault. In this case, TPs make it possible to empiricallydefine a fault, and subsequently derive a test for it. This is a very powerful char-acteristic of TPs that can augment the limited theoretical understanding of newfaults [26].

• Customer returns analysis: sometimes a product passing original test in themanufacturer company may be returned from its customers because of some unex-pected faults under practical use. The manufacturer company can easily use TPsto help identify or define exactly what faults their product involves.

• Test program efficiency improvement: after using TPs to diagnose faultsin a product, the manufacturer can obtain the importance of different faults andtheir occurrence probabilities. Therefore, the original test programs can be mod-ified and/or optimized to target most important faults and thus greatly promoteefficiency and reduce test cost.

4.2 Test primitive generation procedure

The TP diagnostic dictionary is produced in four steps.

1. Create TP for each targeted FP.

2. Create FPs×TPs table with fail/pass information.

3. Perform faults classification.

4. Optimize the table into the terminal dictionary.

Next, each step will be explored specifically in a subsection.

4.2.1 Create TP for each targeted FP

For each FP, a detection condition can be created. The latter can be compiled into TPwhile considering the two criteria: SFP and MTL.

1. To meet the SFP requirement, it’s required to generate TPs with march elementscontaining the minimum number of operations to sensitize and detect the targetedFP only. This is in order to prevent the TP from sensitizing any other non-targeted FPs; e.g., the TP for <0w0/1/-> can be {m (w0);m (w0);m (r0)} or{m (w0);m (w0, r0)}, but the latter is not preferred since it may detect the dynamicfault < 0w0r0/1/1 >, which is dRDF3 (see Table 4.10).

4.2. TEST PRIMITIVE GENERATION PROCEDURE 61

2. To meet the MTL requirement is easy for TP generation of single-cell faults. Fora single-cell FP, we just need to refer to the detection condition and consecutivelyconvert each sensitizing operation into march elements and end with a rx. In thisway the MTL is satisfied. For example, provided an FP of <0w1/0/->, it’s easyto derive its TP as {m (w0);m (w1);m (r1)}. However, for coupling-cell faults,meeting MTL is not so direct and needs systematic analysis, which is not probedin this chapter.

3. Denote each FP and TP according to the notation of their corresponding faultmodels (FMs)

Example 1 Consider 3 FPs: SF0 = <0/1/->, WDF0 = <0w0/1/-> and TF1 =<1w0/1/->. Under instructions 1 and 2, their respective TPs are created; they are givenin Table 4.1. Each TP is given a name based on the FP name; e.g., TSF0 is the TP ofSF0.

Table 4.1: TPs for FPs of Example 1FP notation FP description TP description TP notation

SF0 <0/1/-> {m (w0);m (r0)} TSF0

WDF0 <0w0/1/-> {m (w0);m (w0);m (r0)} TWDF0

TF1 <1w0/1/-> {m (w1);m (w0);m (r0)} TTF1

4.2.2 Create FPs×TPs table with fail/pass information

By incorporating all signatures of FPs under the test of all TPs into a table, we caneasily figure out the difference of each two FPs, and thus realize the diagnosis.

This method seems to be the same as the traditional signature diagnosis methodwhile it’s not the case. Using traditional methods, we need to know the value of eachread operation in a march test while this is not practical for plenty of test platforms.This is because normally a test machine will stop running as long as it encountersthe first fail of one read operation without telling which read operation fails. Thus,the traditional way is generally not practical. As TPs are independent or discretemarch tests, we just need to know whether one TP fails or passes and move on toanother TP, irrespective of the reaction of a TP’s inner read operations, which is easilyimplementable for machines.

Next, we will produce FPs×TPs table following two steps.

1. Compare all existing TPs and if there is a group of same TPs, just put one of themin table.

2. Fill all signatures in the table, and then compare the signatures of each two FPs.If two FPs export the same signature, then add new TP(s) to distinguish themif possible, followed by filling other FPs’ signatures under test of this new TP(s).This process should be repeated until no more FPs can be distinguished further.


Continuing this procedure with Example 1, we find TSF0 and TIRF0 are the sameTPs, where TSF0 is selected to be remained (selecting which is completely random).Furthermore, for computer programming convenience, we symbolize the signature ‘fail’as 1 and ‘pass’ as 0. Thus the signatures are incorporated in Table 4.2.

Table 4.2: FPs versus TPs with pass/fail informationTSF0 TWDF0 TTF1

SF0 1 1 1

WDF0 0 1 0

TF1 0 0 1

IRF0 1 1 1

Then we compare each two FPs through their signatures, yielding that SF0 andIRF0 have the same signature and therefore they can not be distinguished. It’s desiredto generate new TP(s) to distinguish them if possible, but it can not be realized in thiscase. Hence the same table will be kept.

4.2.3 Perform faults classification

Firstly, we categorize FPs into three classes:

• (Externally) Indistinguishable FPs

• (Externally) Distinguishable FPs

• Unknown FPs

Indistinguishable FPs are FPs for which the application of different TPs will alwaysresult in the same memory external behavior. Thus, in Table 4.2 SF0 and IRF0 belongto this category, and therefore are put together in one grid in Table 4.3.

Table 4.3: FPs versus TPs after faults classificationTSF0 TWDF0 TTF1

SF0 and IRF0 1 1 1

WDF0 0 1 0

TF1 0 0 1

Distinguishable FPs are FPs that output different values of a memory whendifferent TPs are applied. Evidently, WDF0 and TF1 of Table 4.3 are distinguishable.

Unknown FPs: Owing to human-being’s limited wisdom and experience, theremight be some faults beyond our current imagination or reasoning. Those possiblefaults are unknown FPs. They can describe an un-modeled faulty behavior; they canalso be not realistic faulty behavior [26].

4.2. TEST PRIMITIVE GENERATION PROCEDURE 63

Suppose there are M groups of different signatures exported from N TPs, then therewill be 2N -M-1 possibilities for unknown FPs ( Note: “-1” stands for the case that allTPs pass). The unknown FPs for the considered example are given in Table 4.4. It isimportant to realize that each unknown FP in Table 4.4 can be used to develop newfault models.

Table 4.4: Table of classified FPsTSF0 TWDF0 TTF1

SF0 and IRF0 1 1 1

WDF0 0 1 0

TF1 0 0 1

Unknown FP1 0 1 1

Unknown FP2 1 1 0

Unknown FP3 1 0 0

Unknown FP4 1 0 1

4.2.4 Optimize the table into the terminal dictionary

As its name implies, optimization is to make our table as concise as possible and tolargest extent reduce the testing cost. Prior to optimization, we remove those unknownfaults from Table 4.4. This is because they may not be realistic and no optimization ispossible without removing unknown faults. Next, remove (if possible) some TPs whilesatisfying the following two requirements:

1. The previous distinguished FPs remain distinguished.

2. No FP is left with the signature of “all 0”. The purpose of this is to guaranteeeach FP should be detected at least.

Each of such removable TPs is called a redundant TP.

Still taking Example 1 for illustration, it’s easy to figure out TSF0 is the redundantTP and thus removable. Consequently, Table 4.2 evolves to Table 4.5.

Table 4.5: Terminal dictionaryTWDF0 TTF1

SF0 and IRF0 1 1

WDF0 1 0

TF1 0 1

Put in mind that performing step 3 or step 4 of TP generation procedure is anvoluntary option for test operators. If the operator attach more importance to detectingmore unknown faults and therefore possibly develop some new fault models, then she/heneeds to proceed step 3 only; if the operator highlights the test cost, she/he shoulddirectly jump to step 4 to diagnose existing faults.


4.3 Test primitives for single-cell static faults

By applying the procedure explained in the previous section, the dictionary for single-cellstatic FPs will be generated.

1. Create TP for each targeted FP; the result is given in Table 4.6:

Table 4.6: The TPs targeting single-cell static FPsFP name FP TP TP name

SF0 <0/1/-> {m (w0);m (r0)} TSF0

SF1 <1/0/-> {m (w1);m (r1)} TSF1

TF0 <0w1/0/-> {m (w0);m (w1);m (r1)} TTF0

TF1 <1w0/1/-> {m (w1);m (w0);m (r0)} TTF1

WDF0 <0w0/1/-> {m (w0);m (w0);m (r0)} TWDF0

WDF1 <1w1/0/-> {m (w1);m (w1);m (r1)} TWDF1

RDF0 <0r0/1/1> {m (w0);m (r0)} TRDF0

RDF1 <1r1/0/0> {m (w1);m (r1)} TRDF1

DRDF0 <0r0/1/0> {m (w0);m (r0);m (r0)} TDRDF0

DRDF1 <1r1/0/1> {m (w1);m (r1);m (r1)} TDRDF1

IRF0 <0r0/0/1> {m (w0);m (r0)} TIRF0

IRF1 <1r1/1/0> {m (w1);m (r1)} TIRF1

2. Create FPs×TPs table with fail/pass information; the result is given in Table 4.7,where TRDF0 and TIRF0 are not included in the table as they are the same asTSF0. Similar explanation applies to TRDF1 and TIRF1 which are the same asTSF1.

Table 4.7: FPs versus TPs with fail/pass information of single-cell static faults

TSF0 TSF1 TTF0 TTF1 TWDF0 TWDF1 TDRDF0 TDRDF1

SF0 1 0 0 1 1 0 1 0

SF1 0 1 1 0 0 1 0 1

TF0 0 0 1 0 0 0 0 0

TF1 0 0 0 1 0 0 0 0

WDF0 0 0 0 0 1 0 0 0

WDF1 0 0 0 0 0 1 0 0

RDF0 1 0 0 1 1 0 1 0

RDF1 0 1 1 0 0 1 0 1

DRDF0 0 0 0 0 0 0 1 0

DRDF1 0 0 0 0 0 0 0 1

IRF0 1 0 0 1 1 0 1 0

IRF1 0 1 1 0 0 1 0 1

3. Perform faults classification; the result is shown in Table 4.8 where 247=28-8-1.

4. Optimize above table into the terminal dictionary; the result is depicted in Table4.9. Note that the columns TSF0 and TSF1 are deleted since they are redundant.

4.4. TEST PRIMITIVES FOR SINGLE-CELL DYNAMIC FAULTS 65

Table 4.8: Classified single-cell static FPs

TSF0 TSF1 TTF0 TTF1 TWDF0 TWDF1 TDRDF0 TDRDF1

SF0, RDF0 and IRF0 1 0 0 1 1 0 1 0

SF1, RDF1 and IRF1 0 1 1 0 0 1 0 1

TF0 0 0 1 0 0 0 0 0

TF1 0 0 0 1 0 0 0 0

WDF0 0 0 0 0 1 0 0 0

WDF1 0 0 0 0 0 1 0 0

DRDF0 0 0 0 0 0 0 1 0

DRDF1 0 0 0 0 0 0 0 1

247 unknown FPs

Table 4.9: Terminal dictionary for single-cell static FPs

TTF0 TTF1 TWDF0 TWDF1 TDRDF0 TDRDF1

SF0, RDF0 and IRF0 0 1 1 0 1 0

SF1, RDF1 and IRF1 1 0 0 1 0 1

TF0 1 0 0 0 0 0

TF1 0 1 0 0 0 0

WDF0 0 0 1 0 0 0

WDF1 0 0 0 1 0 0

DRDF0 0 0 0 0 1 0

DRDF1 0 0 0 0 0 1

4.4 Test primitives for single-cell dynamic faults

This section will explore the TPs for single-cell dynamic faults, during which a newconcept of combined test primitive (CTP) will be created.

4.4.1 Original TPs for single-cell dynamic faults

According to the procedures developed in Section 4.2, we can directly produce the TPsfor single-cell dynamic faults; the result is shown in Table 4.10.

4.4.2 Concept of combined TP

Table 4.10 has given a set of TPs for single-cell dynamic faults, which is not satisfactoryfor our diagnostic purpose; i.e., taking FPs dRDF1, dDRDF1 and dIRF1 together withtheir respective TPs TdRDF1, TdDRDF1 and TdIRF1 as an example, we find TdRDF1

is the same as TdIRF1; then when incorporating them into a table, we will randomlychoose one of them (suppose TdRDF1 is chosen), so the TPs in table will be TdRDF1

and TdDRDF1. It’s not difficult to derive that FPs dRDF1 and dIRF1 will fail bothTdRDF1 and TdDRDF1, which means they will output the same signatures of “1,1”,in which case dRDF1 and dIRF1 can not be distinguished under these 2 TPs. More


Table 4.10: Original TPs for single-cell dynamic FPsFP name FP TP TP name

dRDF1 <0r0r0/1/1> {m (w0);m (r0, r0)} TdRDF1

dRDF2 <1r1r1/0/0> {m (w1);m (r1, r1)} TdRDF2

dRDF3 <0w0r0/1/1> {m (w0);m (w0, r0)} TdRDF3




dDRDF1 <0r0r0/1/0> {m (w0);m (r0, r0);m (r0)} TdDRDF1

dDRDF2 <1r1r1/0/1> {m (w1);m (r1, r1);m (r1)} TdDRDF2

dDRDF3 <0w0r0/1/0> {m (w0);m (w0, r0);m (r0)} TdDRDF3




dIRF1 <0r0r0/0/1> {m (w0);m (r0, r0)} TdIRF1

dIRF2 <1r1r1/1/0> {m (w1);m (r1, r1)} TdIRF2

dIRF3 <0w0r0/0/1> {m (w0);m (w0, r0)} TdIRF3




dTF1 <0r0w1/0/-> {m (w0);m (r0, w1);m (r1)} TdTF1


dTF3 <0w0w1/0/-> {m (w0);m (w0, w1);m (r1)} TdTF3




dWDF1 <0r0w0/1/-> {m (w0);m (r0, w0);m (r0)} TdWDF1


dWDF3 <0w0w0/1/-> {m (w0);m (w0, w0);m (r0)} TdWDF3




important, as dRDF1 and dIRF1 share the same detection condition and we assumeinternal read operations in a TP can not be observed, no matter what operations weadd in a single TP, dRDF1 and dIRF1 will always output the same signature, so theyare not distinguishable through our current TP concept. To make all these 3 FPsdistinguishable, a new concept of combined TP is to be created.

Combined TP (CTP) is a combination of 2 or more independent TPs, which areimplemented consecutively without any other operations inserted between them. A CTPis denoted by using the symbol ‘+’ to connect each single TP.

4.4.3 Modified TPs for single-cell dynamic faults

Based on CTP, we generate a set of modified TPs for single-cell dynamic faults in Table4.11, where TPs for all dRDFs, dDRDFs and dIRFs are CTPs.

Returning to the example mentioned in the beginning of this section, we find TPs

4.5. DIAGNOSTIC DICTIONARY FOR SINGLE-CELL FAULTS 67

Table 4.11: Modified TPs including CTPs for single-cell dynamic FPsFP name FP TP/CTP TP name

dRDF1 <0r0r0/1/1> {m (w0);m (r0, r0)}+{m (r0)} TdRDF1

dRDF2 <1r1r1/0/0> {m (w1);m (r1, r1)}+{m (r1)} TdRDF2

dRDF3 <0w0r0/1/1> {m (w0);m (w0, r0)}+{m (r0)} TdRDF3




dDRDF1 <0r0r0/1/0> the same as TdRDF1

dDRDF2 <1r1r1/0/1> the same as TdRDF2

dDRDF3 <0w0r0/1/0> the same as TdRDF3




dIRF1 <0r0r0/0/1> the same as TdRDF1

dIRF2 <1r1r1/1/0> the same as TdRDF2

dIRF3 <0w0r0/0/1> the same as TdRDF3
















for dRDF1, dDRDF1 and dIRF1 are the same as {m (w0);m (r0, r0)}+{m (r0)}. Signif-icantly, as this CTP contains 2 independently implemented TPs, both of their fail/passinformation is observable; as a result, dRDF1 will output signature as ‘1+1’ under thisCTP, dDRDF1 outputs ‘0+1’ and dIRF1 outputs ‘1+0’. Obviously, they bear mutuallydifferent signatures and thus distinguishable. Since one CTP is incorporated in one gridof a table, the signature ‘x+x’ (x=0, 1) can be simplified as ‘xx’ to facilitate computerprocessing. In addition, the test length of TPs for dRDF1, dDRDF1 and dIRF1 arereduced from 7n to 4n.

4.5 Diagnostic dictionary for single-cell faults

Till now TPs for both single-cell static and dynamic FPs have been produced. Thissection is to generate the diagnostic dictionary for all single-cell FPs, since the mostimportant function of TP is to diagnose faults.


4.5.1 Create FPs×TPs table with fail/pass information

As there are totally 26 different TPs to be used to diagnose single-cell faults: 8 TPsfor single-cell static faults (see Table 4.7) and 18 TPs for single-cell dynamic faults (seeTable 4.11). To make FPs×TPs table possible to be indicated in a paper space, were-denote those 26 TPs with arabian numbers so as to shorten their length, which isshown in Table 4.12.

Table 4.12: Arabian numbers denotation of TPsTPs for single-cell static faults TPs for single-cell dynamic faults

Name Number Name Number Name Number Name Number

TSF0 1 TdRDF1 9 TdTF1 15 TdWDF1 21TSF1 2 TdRDF2 10 TdTF2 16 TdWDF2 22TTF0 3 TdRDF3 11 TdTF3 17 TdWDF3 23TTF1 4 TdRDF4 12 TdTF4 18 TdWDF4 24

TWDF0 5 TdRDF5 13 TdTF5 19 TdWDF5 25TWDF1 6 TdRDF6 14 TdTF6 20 TdWDF6 26TDRDF0 7TDRDF1 8

Based on this new denotation, we create the FPs×TPs table, which is shown in Table4.13.


Table 4.13: FPs versus TPs with fail/pass information of all single-cell faults1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

SF0 1 0 0 1 1 0 1 0 11 00 11 00 00 11 1 1 0 1 1 0 1 0 1 0 0 1SF1 0 1 1 0 0 1 0 1 00 11 00 11 11 00 1 1 1 0 0 1 0 1 0 1 1 0TF0 0 0 1 0 0 0 0 0 00 00 00 11 00 00 1 0 1 0 0 1 0 0 0 1 0 0TF1 0 0 0 1 0 0 0 0 00 00 00 00 00 11 0 1 0 1 1 0 0 0 0 0 0 1WDF0 0 0 0 0 1 0 0 0 00 00 11 00 00 00 0 0 0 0 0 0 1 0 0 0 0 1WDF1 0 0 0 0 0 1 0 0 00 00 00 00 11 00 0 0 0 0 0 0 0 1 0 1 0 0RDF0 1 0 0 1 1 0 1 0 11 00 11 00 00 11 1 1 0 1 1 0 1 0 1 0 0 1RDF1 0 1 1 0 0 1 0 1 00 11 00 11 11 00 1 1 1 0 0 1 0 1 0 1 1 0DRDF0 0 0 0 0 0 0 1 0 11 00 01 00 00 01 0 0 0 0 0 0 0 0 0 0 0 0DRDF1 0 0 0 0 0 0 0 1 00 11 00 01 01 00 0 0 0 0 0 0 0 0 0 0 0 0IRF0 1 0 0 1 1 0 1 0 11 00 11 00 00 11 1 1 0 1 1 0 1 0 1 0 0 1IRF1 0 1 1 0 0 1 0 1 00 11 00 11 11 00 1 1 1 0 0 1 0 1 0 1 1 0

dRDF1 0 0 0 0 0 0 0 0 11 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF2 0 0 0 0 0 0 0 0 00 11 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF3 0 0 0 0 0 0 0 0 00 00 11 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF4 0 0 0 0 0 0 0 0 00 00 00 11 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF5 0 0 0 0 0 0 0 0 00 00 00 00 11 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF6 0 0 0 0 0 0 0 0 00 00 00 00 00 11 0 0 0 0 0 0 0 0 0 0 0 0dDRDF1 0 0 0 0 0 0 0 0 01 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF2 0 0 0 0 0 0 0 0 00 01 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF3 0 0 0 0 0 0 0 0 00 00 01 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF4 0 0 0 0 0 0 0 0 00 00 00 01 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF5 0 0 0 0 0 0 0 0 00 00 00 00 01 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF6 0 0 0 0 0 0 0 0 00 00 00 00 00 01 0 0 0 0 0 0 0 0 0 0 0 0dIRF1 0 0 0 0 0 0 0 0 10 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF2 0 0 0 0 0 0 0 0 00 10 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF3 0 0 0 0 0 0 0 0 00 00 10 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF4 0 0 0 0 0 0 0 0 00 00 00 10 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF5 0 0 0 0 0 0 0 0 00 00 00 00 10 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF6 0 0 0 0 0 0 0 0 00 00 00 00 00 10 0 0 0 0 0 0 0 0 0 0 0 0dTF1 0 0 0 0 0 0 0 0 00 00 00 00 00 00 1 0 0 0 0 0 0 0 0 0 0 0dTF2 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 1 0 0 0 0 0 0 0 0 0 0dTF3 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 1 0 0 0 0 0 0 0 0 0dTF4 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 1 0 0 0 0 0 0 0 0dTF5 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 1 0 0 0 0 0 0 0dTF6 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 1 0 0 0 0 0 0dWDF1 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 1 0 0 0 0 0dWDF2 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 1 0 0 0 0dWDF3 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 1 0 0 0dWDF4 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 1 0 0dWDF5 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 1 0dWDF6 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 1

4.5.2 FPs classification

In Table 4.13, FPs SF0, RDF0 and IRF0 share the same signatures, which is the samecase for SF1, RDF1 and IRF1. No TP can distinguish those faults, which means they areexternally undistinguishable FPs. The rest 36 FPs are undergoing different signaturesand thus distinguishable; besides, there may be 232-38-1 = 4294967257 unknown FPsthat may be realistic or unrealistic (32 is the total number of TPs; 38 is the number ofexisting FPs with different signatures; 1 represents one FP with all-0 signature). Puttingall these information into Table 4.14, we obtain the classification of FPs.


Table 4.14: Classified single-cell FPs1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

SF0RDF0 1 0 0 1 1 0 1 0 11 00 11 00 00 11 1 1 0 1 1 0 1 0 1 0 0 1IRF0SF1RDF1 0 1 1 0 0 1 0 1 00 11 00 11 11 00 1 1 1 0 0 1 0 1 0 1 1 0IRF1TF0 0 0 1 0 0 0 0 0 00 00 00 11 00 00 1 0 1 0 0 1 0 0 0 1 0 0TF1 0 0 0 1 0 0 0 0 00 00 00 00 00 11 0 1 0 1 1 0 0 0 0 0 0 1WDF0 0 0 0 0 1 0 0 0 00 00 11 00 00 00 0 0 0 0 0 0 1 0 0 0 0 1WDF1 0 0 0 0 0 1 0 0 00 00 00 00 11 00 0 0 0 0 0 0 0 1 0 1 0 0DRDF0 0 0 0 0 0 0 1 0 11 00 01 00 00 01 0 0 0 0 0 0 0 0 0 0 0 0DRDF1 0 0 0 0 0 0 0 1 00 11 00 01 01 00 0 0 0 0 0 0 0 0 0 0 0 0

dRDF1 0 0 0 0 0 0 0 0 11 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF2 0 0 0 0 0 0 0 0 00 11 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF3 0 0 0 0 0 0 0 0 00 00 11 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF4 0 0 0 0 0 0 0 0 00 00 00 11 00 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF5 0 0 0 0 0 0 0 0 00 00 00 00 11 00 0 0 0 0 0 0 0 0 0 0 0 0dRDF6 0 0 0 0 0 0 0 0 00 00 00 00 00 11 0 0 0 0 0 0 0 0 0 0 0 0dDRDF1 0 0 0 0 0 0 0 0 01 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF2 0 0 0 0 0 0 0 0 00 01 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF3 0 0 0 0 0 0 0 0 00 00 01 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF4 0 0 0 0 0 0 0 0 00 00 00 01 00 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF5 0 0 0 0 0 0 0 0 00 00 00 00 01 00 0 0 0 0 0 0 0 0 0 0 0 0dDRDF6 0 0 0 0 0 0 0 0 00 00 00 00 00 01 0 0 0 0 0 0 0 0 0 0 0 0dIRF1 0 0 0 0 0 0 0 0 10 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF2 0 0 0 0 0 0 0 0 00 10 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF3 0 0 0 0 0 0 0 0 00 00 10 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF4 0 0 0 0 0 0 0 0 00 00 00 10 00 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF5 0 0 0 0 0 0 0 0 00 00 00 00 10 00 0 0 0 0 0 0 0 0 0 0 0 0dIRF6 0 0 0 0 0 0 0 0 00 00 00 00 00 10 0 0 0 0 0 0 0 0 0 0 0 0dTF1 0 0 0 0 0 0 0 0 00 00 00 00 00 00 1 0 0 0 0 0 0 0 0 0 0 0dTF2 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 1 0 0 0 0 0 0 0 0 0 0dTF3 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 1 0 0 0 0 0 0 0 0 0dTF4 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 1 0 0 0 0 0 0 0 0dTF5 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 1 0 0 0 0 0 0 0dTF6 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 1 0 0 0 0 0 0dWDF1 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 1 0 0 0 0 0dWDF2 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 1 0 0 0 0dWDF3 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 1 0 0 0dWDF4 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 1 0 0dWDF5 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 1 0dWDF6 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 14294967257unknownFPs

4.5.3 Table Optimization

By investigating Table 4.14, we find TPs from 9 to 26 are not removable, because withoutanyone of them, one single-cell dynamic FP will output a all-0-signature and thus notdetectable. Fortunately, if we delete all TPs from 1 to 8, the current distinguishable FPsremain distinguishable; in another word, TPs from 1 to 8 are redundant and thus shouldbe deleted to optimize Table 4.14 into terminal Table 4.15.


Table 4.15: Terminal dictionary for single-cell FPs

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

SF0

RDF0 11 00 11 00 00 11 1 1 0 1 1 0 1 0 1 0 0 1IRF0

SF1

RDF1 00 11 00 11 11 00 1 1 1 0 0 1 0 1 0 1 1 0IRF1

TF0 00 00 00 11 00 00 1 0 1 0 0 1 0 0 0 1 0 0

TF1 00 00 00 00 00 11 0 1 0 1 1 0 0 0 0 0 0 1

WDF0 00 00 11 00 00 00 0 0 0 0 0 0 1 0 0 0 0 1

WDF1 00 00 00 00 11 00 0 0 0 0 0 0 0 1 0 1 0 0

DRDF0 11 00 01 00 00 01 0 0 0 0 0 0 0 0 0 0 0 0

DRDF1 00 11 00 01 01 00 0 0 0 0 0 0 0 0 0 0 0 0

dRDF1 11 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dRDF2 00 11 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dRDF3 00 00 11 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dRDF4 00 00 00 11 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dRDF5 00 00 00 00 11 00 0 0 0 0 0 0 0 0 0 0 0 0

dRDF6 00 00 00 00 00 11 0 0 0 0 0 0 0 0 0 0 0 0

dDRDF1 01 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dDRDF2 00 01 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dDRDF3 00 00 01 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dDRDF4 00 00 00 01 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dDRDF5 00 00 00 00 01 00 0 0 0 0 0 0 0 0 0 0 0 0

dDRDF6 00 00 00 00 00 01 0 0 0 0 0 0 0 0 0 0 0 0

dIRF1 10 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dIRF2 00 10 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dIRF3 00 00 10 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dIRF4 00 00 00 10 00 00 0 0 0 0 0 0 0 0 0 0 0 0

dIRF5 00 00 00 00 10 00 0 0 0 0 0 0 0 0 0 0 0 0

dIRF6 00 00 00 00 00 10 0 0 0 0 0 0 0 0 0 0 0 0

dTF1 00 00 00 00 00 00 1 0 0 0 0 0 0 0 0 0 0 0

dTF2 00 00 00 00 00 00 0 1 0 0 0 0 0 0 0 0 0 0

dTF3 00 00 00 00 00 00 0 0 1 0 0 0 0 0 0 0 0 0

dTF4 00 00 00 00 00 00 0 0 0 1 0 0 0 0 0 0 0 0

dTF5 00 00 00 00 00 00 0 0 0 0 1 0 0 0 0 0 0 0

dTF6 00 00 00 00 00 00 0 0 0 0 0 1 0 0 0 0 0 0

dWDF1 00 00 00 00 00 00 0 0 0 0 0 0 1 0 0 0 0 0

dWDF2 00 00 00 00 00 00 0 0 0 0 0 0 0 1 0 0 0 0

dWDF3 00 00 00 00 00 00 0 0 0 0 0 0 0 0 1 0 0 0

dWDF4 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 1 0 0

dWDF5 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 1 0

dWDF6 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 1


4.6 Summary

In this chapter the philosophy of test primitives and its fault diagnostic function areintroduced. Following a description of its unique advantages in diagnostic testing andfurther benefits for industry, a systematic procedure to generate diagnostic dictionarybased on test primitive has been explored. During the procedure to generate diagnosticdictionary, a group of equations defined as the TP Evaluator has been developed withdemonstration, which exerts to facilitate the generation of the most length optimal testprimitive. Finally, the diagnostic dictionary for single-cell static faults and single-celldynamic faults are generated using the presented procedure.

Advanced Memory testsolutions 5Detecting faults in memory was always a heated issue in semiconductor industry, whichhas been explored by a couple of precursors and yielded a series of achievements indiscovering, defining and testing faults. As this is a gradually progressing process,new concepts of faults and test algorithms were introduced as time passed by; thus,a specific test is, in most cases, targeting a specific category of faults. This leaves aproblem to current industrial test implementation because new presented faults andold ones are both of interest for industry, which leads to our new research orientationof finding comprehensive tests with optimal combination that are able to cover most ofthe discovered faults.

This chapter discusses a set of advanced test solutions that target different classesof memory faults: memory cell array faults (MCAFs), address decoder faults (ADFs),peripheral circuits faults (PCFs) and memory architecture faults (MAFs). It is orga-nized as follows; Section 5.1 depicts the scope of faults targeted in this chapter; Section5.2 introduces the stress combinations adopted in a test; Section 5.3 discusses the testsfor memory cell array faults; Section 5.4 describes the tests for address decoder faults;Section 5.5 probes the tests for peripheral circuits faults; Section 5.6 explores the testsfor memory architecture faults; Section 5.7 approaches a systematic development of testfor faults within dynamic address decoders; Section 5.8 ends the chapter with a summary.

5.1 Overview of targeted faults5.2 Stress combinations5.3 Tests for memory cell array faults5.4 Tests for address decoder faults5.5 Tests for peripheral circuits faults5.6 Tests for memory architecture faults5.7 Test for faults within dynamic address decoders5.8 Summary

73

74 CHAPTER 5. ADVANCED MEMORY TEST SOLUTIONS

5.1 Overview of targeted faults

Chapter 3 has put efforts in defining and explaining each fault of interest in this chapter,which are given in Figure 5.1:

1. Memory cell array faults (MCAFs)

2. Address decoder faults (ADFs)

3. Peripheral circuits faults (PCFs)

4. Memory architecture faults (MAFs)

Enable

MCAF

Memory Faults

Static Dynamic Static Dynamic

PCF MAF

Dynamic

ADF

Static WordOriented

Byte Write

Figure 5.1: Overview of targeted faults

5.2 Stress combinations

When testing, each test is applied using several stresses. Such stresses can be dividedinto non-algorithmic stresses and algorithmic stresses [57].

A non-algorithmic stress, also referred to as an environmental stress, specifiesthe environmental values, such as the supply voltage, the temperature, the timing (theclock frequency), etc.; they are effective during the application of the test.

An algorithmic stress specifies the way the test is performed, and therefore itinfluences the sequence and/or the type of the memory operations. The most knownalgorithm stresses are the address direction and data-background.

• Address Direction (AD) is the addressing extension of the one-dimensionaladdress order (AO) to the two dimensional space of the memory cell array. A realmemory consists of a number of rows and columns (and thus also of a number

5.3. TESTS FOR MEMORY CELL ARRAY FAULTS 75

of diagonals). The AD specifies the direction (i.e., rows, columns, or diagonals)in which the address sequence has to be performed. The commonly used ADs inthe industry are described below, which are further depicted in Figure 5.2 with asimple 4 × 4 cell array.

1. Fast X (fX): With fX addressing, each address increment or decrement op-eration causes an adjacent physical row to be accessed.

2. Fast Y (fY): With fY addressing, each address increment or decrement op-eration causes an adjacent physical column to be accessed.

3. Fast D (fD): With fD addressing, each address increment or decrement op-eration causes an adjacent physical diagonal to be accessed. Fast D is usedless frequently in industry.

C D E F

Fast X: 0, 4, 8, C, 1, 5, 9, D, 2, 6, A, E, 3, 7, B, F

Fast Y: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

Fast D: 3, 4, 9, E, 2, 7, 8, D, 1, 6, B, C, 0, 5, A, F

4x4 Memory Address

0 1 2 3

4 5 6 7

8 9 A B

Common addressing sequences (incrementing)

Figure 5.2: The three common address sequences

• Data Background (DB) is the pattern of ones and zeros as seen in an array ofmemory cells. Put in mind that a group of digits between two ‘/’ is in a row. Themost common types of DBs are shown as below; in addition, Figure 5.3 illustratesthese DBs using a simple 4 × 4 array, where each DB is shown with the base andthe complementary values.

Solid (sDB): all 0s (i.e., 0000.../0000...) or all 1s

Checkerboard (bDB): 0101.../1010.../0101.../1010...

Column Stripes (cDB): 0101.../0101.../0101.../0101...

Row Stripes (rDB): 0000.../1111.../0000.../1111...

5.3 Tests for memory cell array faults

Corresponding to Figure 5.1, memory cell array faults (MCAFs) are divided into staticMCAFs and dynamic MCAFs, whereby dynamic MCAFs are restricted to faults sensi-tized by two consecutive operations in this chapter.


Checkerboard Row Stripes

SolidBase Complement Base Complement

Base Complement Base Complement

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 1

0 1 0 1

0 1 0 1

0 1 0 1

0 1 0 1

1 0 1 0

1 0 1 0

1 0 1 0

1 0 1 0

0 1 0 1

0 1 0 1

1 0 1 0

1 0 1 0

0 1 0 1

0 1 0 1

1 0 1 0

1 0 1 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 1

Column Stripes

Figure 5.3: The common data-backgrounds

5.3.1 Test for static MCAFs

The most optimal test targeting all static MCAFs is March MSS with test length of 18nwhere n is the memory size. March MSS is introduced in [23], which is presented inTable 5.1.

Table 5.1: March MSS{m (w0);⇑ (r0, r0, w1, w1);⇑ (r1, r1, w0, w0);⇓ (r0, r0, w1, w1);⇓ (r1, r1, w0, w0);m (r0)}

5.3.2 Test for dynamic MCAFs

Dynamic MCAFs are divided into single-cell and coupling-cell dynamic MCAFs (seechapter 3); in both cases we still restrict ‘dynamic’ to two consecutive operations. Be-sides, for coupling-cell dynamic MCAFs, only two consecutive operations assigned on onecell (either aggressor-cell or victim-cell) are taken into account. In [32], a test namedMarch MRAW targeting realistic dynamic MCAFs was developed, whose test length is22n and is shown in Table 5.2 below.

Table 5.2: March MRAW{m (w0);⇑ (r0, w1, r1, w1, r1); ⇑ (r1, w0, r0, w0, r0);⇓ (r0, w1, r1, w1, r1); ⇓ (r1, w0, r0, w0, r0);m (r0)}

March MRAW is also capable of detecting all static MCAFs, so if March MRAW is

5.4. TEST FOR ADDRESS DECODER FAULTS 77

applied, March MSS is not needed unless specific fault diagnosis is required.

5.4 Test for address decoder faults

According to chapter 3, address decoder faults (ADFs) are also divided into two cate-gories, namely static address decoder faults (sADFs) and dynamic address decoder faults(dADFs). Our tests are based on such a division and will be discussed in following twosubsections.

5.4.1 Test for sADFs

sADFs can be simply explained as three situations, an operation fails to act on itstargeted cell, an operation act on another cell and the coexistence of these two cases.Referring to chapter 3, taking the “no cell and no address fault” (AFnca) as an example,the cell won’t be accessed and will always keep its original logic value (supposed to be0); thus if we write 1 to all cells and read 1, the fault will be detected, which turns outto be the transition fault in MCAFs. In fact, any march test will detect sADFs if itsatisfies Condition AF for h≥1 [17] (h from hammer), therefore they can be covered byMarch MRAW, which we won’t repeat here.

5.4.2 Test for dADFs

Prior to discussing the tests for dADFs, we need to introduce the requirements forsensitizing dADFs [56]:

1. Sensitizing address transitions;

2. Sensitizing operation sequences.

Sensitizing address transitions can be caused by an address pair or an address triplet.A Sensitizing Address Pair (SAP) consists of a sequence of two addresses {Ag,Af}or {Af,Ag}, which have to be applied in sequence because dADFs are sensitized byaddress transitions, whereby Ag denotes a good address and Af stands for a faultyaddress. When the two SAPs, {Ag, Af} and {Af, Ag}, are applied in sequence, the Sen-sitizing Address Triplet (SAT) {Ag, Af,Ag} can be applied instead. This is moreefficient because only three addresses have to be applied, rather than four addresses whenthe two SAPs are applied. SAPs/SATs are generated using an Addressing Method (AM).

To each address of a SAP or a SAT at least one operation has to be applied, resultingin a Sensitizing Operation Sequence (SOS) consisting of at least two operationsfor an SAP and three operations for an SAT since at least one operation has to beapplied to each address of an SAP or SAT. Next, several addressing methods and SOSare about to be presented.

Below three AMs are enumerated, the details of which can be found in [56].


• Address Complement AM

• The 2i Addressing Method

• The H1 Addressing Method

Corresponding to SAP and SAT, the sensitizing operations applied to them will formSOP and SOT, which are indicated below, whose details are also explicitly demonstratedin [56].

• Sensitizing Operation Pairs (SOPs)

• Sensitizing Operation Triplets (SOTs)

Based on the AMs and SOPs/SOTs introduced above, tests for detecting dADFs canbe constructed. The results are given in Table 5.3, whereby n is the memory size and Nis the number of address lines. Both of those tests are capable for detecting all dADFs.

Table 5.3: Tests for dADFsMarch dADF-RaW-H1 {m (w0);mH1 (r0, w1);mH1 (r1, w0)}March dADF-RaR-H1 {m (w0);mH1 (r0, w1, r1);mH1 (r1, w0, r0)}March dADF-RaW-2i {m (w0);⇑2i

(r0, w1);⇑2i

(r1, w0);⇓2i

(r0, w1);⇓2i

(r1, w0)}March dADF-RaR-2i {m (w0);⇑2i

(r0, w1, r1);⇑2i

(r1, w0, r0);⇓2i

(r0, w1, r1);⇓2i

(r1, w0, r0)}

5.5 Tests for Peripheral Circuits Faults

Peripheral circuits faults (PCFs) are classified as static PCFs (sPCFs) and dynamicPCFs (dPCFs), the former of which is non-speed related faults and the latter of whichis speed related faults.

5.5.1 Tests for sPCFs

As was introduced in chapter 3, static peripheral circuits faults are easy to detect andusually get covered while detecting static MCAFs. The primarily used fault modelsare simple logic models such as the Stuck-at-fault. Since static faults in the peripheralcircuits will impact all operation through the defective logic circuits, they will be mappedto static MCAFs [17]; thus March MSS should be able to have 100% fault coverage forthem.

5.5.2 Tests for dPCFs

The test set for dPCFs are manifested in Table 5.4, where one of test 3 and test 2 hasto be used together with test 1 (this is the reason we call it a test set other than a test);besides, each test has to be used with different DBs; e.g., one with sDB and one withcDB because from industrial point of view, it has been shown that using different DBshas a larger impact on the fault coverage and can detect some non-modeled (unknown)faults [19, 20, 57].

5.6. TESTS FOR MEMORY ARCHITECTURE FAULTS 79

Table 5.4: Test set for dPCFs

# Name TL DB Description; D=DB FC

1 March BLIWD 8n sDB or cDB {m (wD);m (wD, rD, wD);m (wD);m (wD, rD, wD)} BLIF, SWDF

2 March SAPR 5n sDB or cDB {m (wD);m (rD, wD);m (rD, wD)} SSAF, SPRF

3 March SAPR 6n bDB or rDB {m (wD);m (rD, wD);m (wD);m (rD, wD)} SSAF, SPRF

5.6 Tests for memory architecture faults

As Chapter 3 has discussed, SRAMs can be organized as word-oriented memories(WOMs). In addition, by using specific enable control circuitry that enables or disablesthe writing circuitry of the associated bits in the data words, SRAM can control itsintended cells to be written. Therefore, this section is to present both tests involved inthese two structures.

5.6.1 Tests for Word-oriented memory (WOM) faults

Corresponding to Chapter 3, WOM faults are divided into single-cell faults and coupling-cell faults where coupling-cell faults are again divided into inter-word faults and intra-word faults; important is that all these cases are restricted to static faults.

5.6.1.1 Tests for single-cell faults and inter-word static faults

Suppose the word contains B bits, it is evident that single-cell faults and inter-wordfaults are bearing the same detection conditions with bit-oriented memory faults; thuswe can easily convert March MSS, the test for static MCAFs, into the test targetingsingle-cell faults and inter-word static faults within a WOM, which is to simultaneouslyapply each operation in every march element of March MSS to each cell of a word.

5.6.1.2 Tests for intra-word static faults

The most essential issue lying in tests for intra-word static faults is the sensitizationof those faults. As a word usually consists of 2n bits while any pair of bits in a wordmay undergoes coupling faults, we need to take every situation into account; besides,since each cell in one word must be fed with operations simultaneously, it’s far morecomplicated to derive a commonly applicable test targeting intra-word faults thaninter-word faults. In [30], a very detailed and systematic approach has been developed;hereby, we present its test March SAM together with necessary interpretation.

Prior to introducing March SAM, a series of data backgrounds (DBs) and theircorresponding operation sequences (OSs) needs to be provided below. According to thedefinition in last section, B is the number of cells constituting a word, and we assumeB=2 for the mentioned DBs and OSs, which are manifested in Table 5.5.

In Table 5.5, the first column is the number of a DB; the second column depictsthe content of DBs; e.g., ‘01’ means the logic values of a word with 2 bits are 0 and 1;


Table 5.5: The DBs and OSs for intra-word static faults# DBs OSs

0 01 wD0 , rD0 , wD0 , rD0 , rD0

1 11 wD1 , rD1 , wD1 , rD1 , rD1

2 10 wD2 , rD2 , wD2 , rD2 , rD2

3 00 wD3 , rD3 , wD3 , rD3 , rD3

4 10 wD4 , rD4

5 11 wD5 , rD5

6 01 wD6 , rD6

7 00 wD7 , rD7

the third column incorporates the corresponding OSs of their DBs; e.g., wD0 equals tow01, which means simultaneously writing 0 to one cell and writing 1 to another in a word.

For a 2-bit word memory, sequentially applying all the OSs in Table 5.5, precededwith one more initiation operation w00, is enough to detect all intra-word static faultswithin one word. However, B varies in a big range and thus requires a structuredtest irrespective of the value of B. Next, we extend the DBs and OSs for B=2 to allsituations with B=2n with following steps:

1. step 0: For each cell-pair (ci, ci+1) (ci means a cell in a word marked with ‘i’; bearin mind that one cell can not be re-selected in another pair in all steps (e.g., i isan even number in this step)), apply the DBs in Table 5.5 01, 11, 10, 00, 10, 11,01, 00; e.g., applying 01 to such cell pairs results in an n-bit DB of 0101...01, 11with result of 1111...11, and 00 with result of 0000...00. Correspondingly, applyall derivative OSs to the whole word; that is, w0101...01, r0101...01, w0101...01,r0101...01, r0101...01 and then w1111...11, r1111...11, ..., r0000...00.

2. step j: (1 ≤ j ≤ [log2B]-1). For each cell-pair (ci, ci+2j), repeatthe applications in step 0. E.g., suppose j=2, the cell-pair will be(ci, ci+4); applying 01 to such cell pairs results in an n-bit DB of00001111...00001111, 11 with result of 11111111...11111111, and 00 with resultof 00000000...00000000. Correspondingly, apply all derivative OSs to the wholeword; that is, w00001111...00001111, r00001111...00001111, w00001111...00001111,r00001111...00001111, r00001111...00001111 and then w11111111...11111111,r11111111...11111111, ..., r00000000..00000000.

With above steps following an initialization operation of w000...000, all intra-wordstatic faults will be detected. As can be deduced from above steps, there will be1+28*log2B (1 for the initiation operation) operations for one word; in case of a m-sizememory, (1+28*log2B)*m

B operations as are needed as a whole.

For instance, when B=4, we will come to following test:

5.7. TEST FOR FAULTS WITHIN DYNAMIC ADDRESS DECODERS 81

{m (w0000);M0

m (w0101, r0101, w0101, r0101, r0101, w1111, r1111, w1111, r1111, r1111);M1

m (w1010, r1010, w1010, r1010, r1010, w0000, r0000, w0000, r0000, r0000);M2

m (w1010, r1010, w1111, r1111, w0101, r0101, w0000, r0000);M3

m (w0011, r0011, w0011, r0011, r0011, w1111, r1111, w1111, r1111, r1111);M4

m (w1100, r1100, w1100, r1100, r1100, w0000, r0000, w0000, r0000, r0000);M5

m (w1100, r1100, w1111, r1111, w0011, r0011, w0000, r0000)}M6

It’s conforming to above deduction that there are 57 operations for each word. Be-sides, sink in mind that the division of those march elements is random because dynamicfaults are out of interest and therefore the organization of march elements won’t influencethe detection.

5.6.2 Tests for Bit/Byte Write Enable (BWE) Faults

BWE faults were categorized as opens, shorts and bridges in Chapter 3. Opens will bediscussed next and then we will present tests for both shorts and bridging together.

5.6.2.1 Tests for BWE open faults

According to [36] [52] [11] [40] [56], the open faults in BWE circuitry shares the samedetection condition with static address decoder faults, and thus able to be detected byMarch MRAW introduced in section 5.1.

5.6.2.2 Test for BWE short/bridging faults

The default way used to test a memory with bit/byte write enable capabilities is toenable all the control/mask signals and apply the memory tests like march tests [4, 62].However, because the action of enabling/disabling all together will disemble the mutualaffect, the bridging faults will not be sensitized. In this section a test named ‘Test BWE’[54] will be adopted to cover both BWE short and bridging faults, which has a non-march test format while manifests high testing efficiency. The structure of ‘Test BWE’is provided in Figure 6.1.

5.7 Test for faults within dynamic address decoders

For dADFs, Said Hamdioui and Zaid Al-Ars, based on the progress of technology andincoming defect mechanism in address decoders, had in depth probed the fault modelsand harvested a series of test algorithms that target dADFs [56]. However, the addressdecoder circuitries differ in industry and can be generally classified as static address


Repeat with complementary data;

Select one row (R) and write 0’s;

for each BWEi { Enable BWEi; write 1’s in R; read from R; write 0’s in R; disable BWEi;}

Figure 5.4: Definition of Test BWE

decoders and dynamic address decoders, which brought more variation in consideringour test algorithm targeting corresponding dADFs. In [56] a general analysis has beenintroduced regarding dynamic address decoders, including the suggested address tran-sitions, march test operations and corresponding BIST implementation on behavioriallevel. This section will put effort to giving more detailed analysis and present some modi-fication to the previous march test operations in [56], expecting to finalize a structurizedmethod in testing dADFs within dynamic address decoders.

5.7.1 Dynamic address decoder

In Chapter 2 we have introduced the functional model of a memory chip, whereby theutility and the basic working principle of an address decoder has been dabbled. To makethings scientific and facilitate the construction of a test algorithm regarding specificaddress decoders, the detailed working theory is to be presented based on the addressdecoder circuitry on transistor level. To begin with, the static address decoder circuitryis depicted in Figure 5.5 [56].

Figure 5.5, instead of giving out a complete structure of an address decoder, showsthe circuitry of only one address bit within a 8-bit static address row decoder. This isenough for our analysis because other bits share the similar circuitry and three addresslines is capable to represent the situation of multiple address lines, in addition to which,column decoder can be dealt with the similar investigation and thus the whole chapterwill only discuss row decoders. As is straightforward, WL0=0 if a1a2a3=111, whichmeans WL0 is selected when a1a2a3=000; while if a1a2a3 equals to any other value, oneof the rest 7 bits will be turned on. In such designs there is no other signals insertedbefore or after the address line signals, which means when a word line is turned on oroff is totally determined by when the address lines are changed with their correspondingvalues. Consequently, both activation delay and deactivation delay can take place incase of a defect for an address line, which has been probed in [56]. However, in dynamicaddress decoders, this conclusion should be modified according to its specific structure,as is shown in Figure 5.6.

As can be seen in Figure 5.6 [56], there are two differences of such a structure from


Figure 5.5: A static address decoder circuitry on transistor level

Figure 5.6: A dynamic address decoder circuitry on transistor level

the static address decoders. Firstly, the pull up path is under control of one independentprecharge signal instead of directly controlled by three address lines. More important,a timing signal is inserted into the circuit. It is not hard to figure out that WL0 willbe activated when Prech=0, Timing=1 and a1a2a3=000; WL0 will be deactivated whenany of these signals are equal to other value(s); e.g., presuming Prech=0, Timing=1but a1a2a3 is changed to be 010, the node between pull up and pull down path willencounter a voltage divide phenomenon and can not attain 1, which makes WL0 stilldeactivated. Other conditions making WL0 deactivated is more straightforward to de-


rive. The advantage of such structures is that the Timing signal is set prior to that ofaddress lines, in which case even there are some defects within address lines that makethem change later than expected, WL0 will be deactivated by the change of the Timingsignal. If the defects involved in the Timing line can be neglected, we will not see thedeactivation delay faults in spite of the possible defects in address lines. To the contrary,the activation of WL0 requires all the states of the Timing, Precharge and address linesto be satisfied simultaneously, so the activation delay faults will still show up as longas there are corresponding defects in address lines, irrespective of the influence of theTiming and the Precharge signal. In following sections, we will explore how to sensitizethe activation delay faults in dynamic address decoders.

5.7.2 Address transition and addressing method

Following the analytical methodology introduced in [56], we will also divide theconstruction of the test algorithm into two phases, whereby the first is to figure out theaddress transitions to sensitize the dADFs, and the second is to develop the march testoperations for each march element. In this section, we will handle the first problem.

5.7.2.1 Intergate defects

In accordance with the definition of defect models built up in [56], we incorporatethe resistive opens in the circuitry of Figure 5.6. Firstly, we look into the situation ofintergate opens, which is shown in Figure 5.7.

Figure 5.7: Intergate resistive open in a dynamic address decoder

An address transition means an address change from an initial address to adestination address. Ascribing to previous analysis, such a defect in Figure 5.7 will


only result in the activation delay for WL0, which means to sensitize the fault thedestination address has been fixed as a0a1a2=000. Therefore, our effort only needs tobe put in finding out the beginning address. We divide the discussion into two cases;i.e., a1 undergoes transition and a1 does not undergo transition.

In the first case, the beginning state of a1 is 1. Due to the Defect 1 in Figure 5.7, thetransition of a1 from 1 to 0 will be delayed. Moreover, no matter what the beginningstates of a0 and a2 are, though they have no delay, WL0 will not be activated unlessa1 completely shut off its corresponding NMOS. Otherwise the parallel connection willallow the path for a1 to connect Vdd and ground, which prevents point A from attaining1 and thus blocks the activation of WL0. In other words, the delay of a1 transition willbe propagated to the delay of the activation of WL0, regardless of whether there aretransitions within a0 and a2. Therefore, the address transition can be formulated asfrom a0a1a2=x1y to a0a1a2=000 (x,y=0 or 1).

In the second case, the beginning state of a1 is 0, which means the NMOS controlledby a1 has already been shut off. Further because Defect 1 can only affect the transitionof a1, then no matter what the beginning states of a0 and a2 are, WL0 will be activatedwithout any delay. Hence in such condition no delay fault can be sensitized.

5.7.2.2 Intragate defects

Besides existing externally, the defects may also reside within a gate, and such transfercould bring in different activation requirements, as is shown in static address decoders.To eliminate our worry of this, such defects are to be probed in the following paragraphs.

In Figure 5.8 a resistive open Defect 2 is incorporated into the gate of a dynamicaddress decoder. The impact of such a defect for our activation delay can be simplifiedin another way, other than directly discussing like before. As is introduced previously,the address lines a0a1a2 should be turned to 000 so as to activate WL0. However, suchstates are exerting a passive function; that is shutting off three NMOS and thus makingthe paths between Vdd and GND open. During this function work, the three NMOStransistors do not need to transport any charge, leaving all the charge transportationaction to the PMOS on the top of the circuitry. Just attributing to that Defect 2has neither influence to the shutting off action of each NMOS, nor any impact to thepull up action of the top PMOS, such a defective address decoder will function cor-rectly. In another word, no address transition needs to be explored for fault sensitization.

5.7.2.3 Overall address transition requirement

To summarize from above discussions in terms of both intergate defects and intragatedefects, the address transition to sensitize the activation delay fault in WL0 can onlybe a0a1a2=x1y → a0a1a2=000 (x,y=0 or 1), given a resistive open defect with a1.Due to the complete symmetry, we come to that in case of a defect with a0 (a2), the


Figure 5.8: Intragate resistive open in a dynamic address decoder

address transition to sensitize activation delay in WL0 only requires the transition ofa0 (a2) with other lines out of care. Next, we need to figure out the address transitionrequirement for any other address bit WLi (0 < i < 8).

As is often the truth, the circuitry topology for any other bit WLi is exactly thesame as WL0 bit in Figure 5.6. The only difference lies in that the type of three parallelMOS transistors varies. Therefore, the activation mechanisms of different bits are thesame; i.e., all parallel MOS transistors should be shut off simultaneously. As a result,all previous analysis is completely applicable to activation delay for WLi.

In addition, it is reasonable that 8-bit address decoders can represent n-bit (n>0)address decoders. Hence, the overall conclusion for the address transition requirementto sensitize the activation delay in any bit dynamic address decoders can be formulatedas follows. Given an n-bit dynamic address decoder, N is the number of its address lines,where n=2N . Denoting WLi (0≤i≤n-1) to be one of the address bits, aq (0≤q≤N-1) tobe one of the address lines and Aiq to be the value of aq when WLi is selected, then theaddress transition to sensitize the activation delay fault in WLi brought by the defectin aq is a0a1...aq...aN−1 = XX...Aiq...X → a0a1...aq...aN−1 = Ai0Ai1...Aiq...AiN−1 (X=0 or 1 and not necessarily equal to each other).

5.7.2.4 Addressing method

In above subsections the overall address transition requirement has been harvested,while in practical testing, we need to finalize an Addressing Method to realize suchaddress transitions, and target two criteria, all faults sensitized and minimum number


of address transitions.

In terms of a 8-bit dynamic address decoder, to sensitize activation delay faults inWL0 brought by defects in all 3 address lines, we need to go through following addresstransitions. 1xy→000, x1y→000 and xy1→000 (x, y=0 or 1). Fortunately, one transitioncan fulfill all of them, which is 111→000. This bit-to-bit complement address transitionrealizes the transition for each address line in one time, which can be directly applied toall other address bits, as is shown in Table 5.6

Table 5.6: Address transitions sensitizing all dADFsActivation delay fault location Sensitizing address transition

WL7 000→111

WL6 001→110

WL5 010→101

WL4 011→100

WL3 100→011

WL2 101→010

WL1 110→001

WL0 111→000

Address transitions in Table 5.6 have achieved one of the criteria for addressingmethod, which is that all faults are sensitized. While we can still develop further sim-plifications and meet the other criteria, minimum number of address transitions. It isstraightforward to find that each transition in Table 5.6 can find its reversed directionaltransition. If grouping each reversed directional transitions as a pair, we can delete oneaddress in each pair, exporting our addressing method, described in Table 5.7

Table 5.7: Addressing method

Activation delay fault location WL7 & WL0 WL6 & WL1 WL5 & WL2 WL4 & WL3

Sensitizing address transitions 000→111→000 001→110→001 010→101→010 011→100→011

According to the addressing method indicated in Table 5.7, there are totally 12addresses needed to be experienced in practical testing, only 3

2 times of all the addresses.This mathematical relationship can be depicted as 12 = 8× 2 × 3

4 , whereby 2 means apair of bit-to-bit complement addresses and 3

4 accounts for 3 addresses from 4 addressesthat constitutes a reversed directional address transition pair.

Proved in previous subsections, n-bit dynamic address decoders share the same ad-dress transition requirement as that of 8-bit decoder. Consequently, suppose Ai standsfor the address value of address bit WLi, the addressing method for an n-bit dynamicaddress decoder can be outlined in Table 5.8, which we name it as C (complement ad-dressing method).


Table 5.8: Addressing method for n-bit dynamic address decodersActivation delay fault location Sensitizing address transitions

WLn-1 & WL0 A0 → A0 → A0

WLn-2 & WL1 A1 → A1 → A1

WLn-3 & WL2 A2 → A2 → A2

... ...

WLn2

& WLn−22

A n−22→ A n−2

2→ A n−2

2

5.7.3 March test operations

Compared with the address transitions discussed above, the march test operationsis more straightforward to derive. An eligible sequence of test operations mustsatisfy the detection condition of a fault; i.e., such operations must be able to detectthe fault. Next we derive the detection condition of dADFs in dynamic address decoders.

Still taking the row decoder for analysis, when moving from a correct row to a faultyrow where the word line suffers an activation delay, the operations applied to the faultyrow will not be accomplished. This indicates that as long as we apply an operation tothe faulty address, the fault will be sensitized. Therefore, all possible test operationscan be divided into two cases; i.e., if the sensitizing operation is a write operation, thenone more read operation should be added to read out the fault, since our test is basedon the external observation; if the sensitizing operation is a read operation, then thefault will be detected directly. Next the stress combination for above two situations willbe introduced respectively.

For the first case, even if the write operation fails, it is required that the cell inthe faulty address should store a complement value previously, so that the followingread operation can read an opposite value and detect the fault. Therefore, it isstraightforward to derive the shortest test with such stress, which is denoted by MarchAD-WaR-C shown in Table 5.9 (since what we discuss till now are all based on the rowdecoders, the tests in Table 5.9 are all using Fast X address direction).

For the second case, even if the read operation fails, it must be guaranteed, to largeextent, that the readout strays away to the complement value. This is because after theread operation is delayed, the sense amplifier and in turn the output latch may still flip toeither correct or wrong directions. Therefore, two categories of stress will be introduced,i.e., Insufficient precharge stress and Output latch inertia stress.

• Insufficient precharge stress: When a read operation is following a write oper-ation which contains a complement value, the insufficient precharge between thesetwo operations will lead to the bit lines fed with a complement value as the expec-tation of the upcoming read. This will cause the sense amplifier prone to flippingto the faulty direction, which realizes the detection of the fault. Such stress isdefined as the Insufficient precharge stress.


• Output latch inertia stress: When the last read operation exports a value X(X=0 or 1), X is stored in the output latch until next read operation with value Xchanges it. It is reasonable that the external force needs a certain energy and timeto change the stored value in output latch; consequently, if the next read operationis too weak (like the activation delay faults exists), it will not have enough energyor time to renew the output latch. As a result, the output latch will still returnsa previously stored value, which is complement with the next read. Such stress isdenoted as the Output latch inertia stress.

Incorporating the Insufficient precharge stress, the shortest test is generated asMarch AD-RaW1-C, which is shown in Table 5.9.

Incorporating the Output latch inertia stress, the shortest test is generated as MarchAD-R-C, which is shown in Table 5.9.

Incorporating both Insufficient precharge stress and Output latch inertia stress, theshortest test is generated as March AD-RaW2-C, which is shown in Table 5.9.

Table 5.9: Tests for dADFs in dynamic address decodersNotation Description Data background

March AD-WR-C {⇑C (w0);⇑C (w1, r1);⇑C (w0, r0)} Solid DB

March AD-RaW1-C {⇑C (w0);⇑C (r0, w1);⇑C (r1, w0)} Special DB

March AD-R-C {⇑C (w0);⇑C (r0);⇑C (w1)};⇑C (r1) Row Stripe

March AD-RaW2-C {⇑C (w0);⇑C (r0, w0);⇑C (w1);⇑C (r1, w1)} Row Stripe

1. March AD-WR-C, as its name implies, means a March test targeting ActivationDelay fault, whose main operations are a Write and a Read, using C addressingmethod.

• Testing mechanism: The first w0 initializes the memory, then as long asthe activation delay exists, the w1 operation will fail at the faulty address,following which, the r1 will actually read the initial state 0 of the cell andexport a complement data as expected; the third march element is designedfor the asymmetric sensitivity regarding 1 and 0.

• Stress extent: Since the previous state of the cell in faulty address is com-plement as the second write, as long as this write fails, the following readoperation will definitely output the faulty information. Thus, this test is verystressful.

• Number of operations: 5

• Data background: Solid DB

2. March AD-RaW1-C means a March test targeting Activation Delay fault, whosemain operation are Read after Write, using C addressing method. “1” means thisis version 1 of such a test.


• Testing mechanism: The first w0 initializes the memory, then as long asthe activation delay exists, the r0 operation will fail at the faulty addressand exports faulty information; the third march element is designed for theasymmetric sensitivity regarding 1 and 0.

• Stress extent: Right before the r0 accesses the faulty address, the w1 will pullthe bit lines in complement state as the following r0 expects to read. As longas the precharge between the w1 and r0 is not sufficient enough, the r0 will beprone to outputting a complement value as expected. However, this kind ofstress is restricted on two aspects: one is that it loses stress when prechargeis sufficient; the other is that it loses stress when going Fast Y direction todetect faults in column decoders. In other words, this test is not stressfulenough.


• Data background: Special DB. This is because in each address triplet the firstand the third address are the same but are written with complement value.Thus, the data background is none of the four regular ones.

3. March AD-R-C means a March test targeting Activation Delay fault, whose mainoperation is a Read operation, using C addressing method.

• Testing mechanism: The first w0 initializes the memory, then as long as theactivation delay exists, the r0 operation will fail at the faulty address andexports faulty information; the third and fourth march elements are designedfor the asymmetric sensitivity regarding 1 and 0.

• Stress extent: As this test adopts the row stripe as its data background, rightbefore the rx (x=0 or 1) accesses the faulty address, the previous rx will storea x in the output latch. Because in each read process it takes time and energyto change the value stored in the output latch, which means the output latchhas the inertia to retain its previous value, a complement value will increasethe difficulty for it to change, especially when rx is quite weak due to theactivation delay. Thereby, this test is very stressful.


• Data background: Row stripe

4. March AD-RaW2-C means a March test targeting Activation Delay fault, whosemain operations are Read after Write, using C addressing method. “2” meansthis is version 2 of such a test.

• Testing mechanism: The first w0 initializes the memory, then as long as theactivation delay exists, the r0 operation will fail at the faulty address andexports faulty information; the third and fourth march elements are designedfor the asymmetric sensitivity regarding 1 and 0.

• Stress extent: As this test adopts the row stripe as its data background,it absorbs both stress methods in March AD-RaW1-C and March AD-R-C.


Thereby, this test is most stressful in testing row decoders, while it is asstressful as March AD-R-C when testing column decoders due to the loss ofread after write stress.


• Data background: Row stripe

Consequently, when implementing our test, we only need to choose one from MarchAD-R-C and March AD-RaW2-C on concern of all factors.

5.7.4 Address generating circuitry of the BIST

During memory testing, we exploit the BIST (built in self test) to implement a test.Normally the flexible BIST can support a general march test with regular stress combi-nations while it may not be able to handle March AD-R-C or March AD-RaW2-C due tothe irregular addressing method. Hence, we just need to design the address generatingcircuitry of the BIST. In [56], a BIST design has been developed on behavioral level,based on which, we will present the design on circuit level. Moreover, one more part forstopping the address generation has been developed. Suppose the dynamic row addressdecoder has 10 address lines, then the circuitry is shown in Figure 5.9.

Figure 5.9: Address generating circuitry in the BIST

In Figure 5.10 there are 12 JK flip-flops that flip on the negative edge. Flip-flop Aand flip-flop B form a modulo-3 counter and flip-flop 0 through flip-flop 9 form a binarycounter, whereby line 0 through line 9 are the address lines and line 9 is on the highest


bit. If the initial states of each node are set as in Table 5.10, then we can obtain thestates of A, B and line 0 through line 9 in different clock periods, which is exported inTable 5.11.

Table 5.10: Initial statesJA B A JB B Node 0 through node 9

1 1 0 0 0 0

Table 5.11: States of A, B and address lines as clock changesB A Line 9 Line 8 Line 7 Line 6 Line 5 Line 4 Line 3 Line 2 Line 1 Line 0

0 0 0 0 0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 1

0 1 1 1 1 1 1 1 1 1 1 0

1 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 1 0

0 1 1 1 1 1 1 1 1 1 0 1

1 0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 1 1

0 1 1 1 1 1 1 1 1 1 0 0

1 0 0 0 0 0 0 0 0 0 1 1

As can be seen in Table 5.11, the addresses generated are 0000000000 →1111111111 → 0000000000 → 0000000001 → 1111111110 → 0000000001 →0000000010 → 1111111101 → 0000000010 → 0000000011 → 1111111100 →0000000011 · · · , which is right what the C addressing method represents.

However, when implementing test with normal addressing method (cell by cell),the flexible BIST “knows” to stop address generation when the whole row or wholecolumn is finished, which is not the case for C addressing method. To inform the BISTto stop address generation, we need one more trick to modify the circuitry in Figure 5.10.

From analysis in previous sections we know that if there are totally n address bits, Caddressing method only needs to generate n

2 address triplets (An−22→ An−2

2→ An−2

2).

If using a counter to count such a number to stop the generation, it is quite hardwareconsuming. Further, we can also find that when the triplet firstly attains An−2

2, it is

always the case that node 0 through node N-2 firstly become all 1 (N is the number ofaddress lines, which is 10 currently). Therefore it is natural to think that if making thosenodes connecting to an NAND gate whose output controls the CLK then the CLK willbe disabled when node 0 through node N-2 firstly become all 1. Problem is that thiswill lead to the last two addresses of the final triplet (An−2

2→ An−2

2) will be missed.

Fortunately, we can see that it is the very time when node B and node 0 through nodeN-2 become all 1, all the triplets will be finished. Therefore, we can connect node B


and node 0 through node N-2 to an NAND gate whose output controls the CLK, thenthe address generation will be stopped as desired. Finally, the schematic of Figure 5.9is changed as displayed in Figure 5.10.

Figure 5.10: Final address generating circuitry in the BIST


5.8 summary

This chapter, based on the previous introduction of faults underlying in memory, hassummarized a series of existing tests with a selection from them. Especially, each testsin this chapter is derived from a systematic and extensive method, which can be directlyapplied or inspiring for further development of new tests. Two typical examples are testsfor dynamic address decoder faults and intra-word faults. The tests for dynamic addressdecoder faults [56] are developed based on a defect modeling method; in addition, suchtests are constituted in two phases of sensitizing addressing and sensitizing operations,which brings in a systematic way for future research. The test for intra-word faultsprovides a structured way of DB sensitization analysis from algorithm point of view [30].

As the majority of tests presented in this chapter are created on strict theoreticaldeduction, some considered faults may hardly exist or some faults may exceed our imag-ination. To solve those questions, practical implementation of them on real silicon is theonly way, which will be further explored in following chapters.

Setup of memory test program 6Memory test in the industry is facing several problems. To begin with, diagnosis amongfaults becomes more and more important since it can benefit in speeding up yield learningand optimizing the test program to target the most important faults. In addition, newmanufacturing technology within the semiconductor industry causes new defect mecha-nisms and therefore new fault models such as dynamic faults. Finally, some unmodeledfaults called special faults such as transient faults and soft faults are seeing practicalappearance, which have not yet been systematically tested. On realizing such problems,Altera, the semiconductor company with leading technology and high requirement ofreliable embedded memory, opened up a Joint Development Project (JDP) with DelftUniversity of Technology, which expects to provide a comprehensive test program. Thistest program is targeting following purposes.

• Diagnose faults using the test primitive concept

• Improve the fault coverage by using advanced tests targeting new faults like dy-namic faults

• Use special tests to detect unique faults that are still not fully understood

This chapter is organized as follows. In Section 6.1, a test set based on the testprimitive (TP) concept is developed to facilitate the diagnosis among faults; therefore,one can figure out the importance of each of the targeted faults. In Section 6.2, a groupof advanced tests are presented to detect dynamic faults, memory architecture faultsand two-port faults. In Section 6.3, a couple of special tests are created to evaluate theimportance of unmodeled faults such as transient faults and soft faults. Section 4 endsthe chapter with a summary.

6.1 TP-based tests6.2 Advanced tests6.3 Special tests6.4 Summary

95

96 CHAPTER 6. SETUP OF MEMORY TEST PROGRAM

6.1 TP-based tests

TPs are a group of march tests that are adopted to detect, and especially practicallydiagnose memory faults. Hereby TPs for diagnosing single-cell static and 2-operationdynamic MCAFs will be presented; as they need to exert their diagnostic functiontogether, all of them are grouped in one table followed by their common explanations.

• Description: see Table 6.1

Table 6.1: TPs for single-cell static and 2-operation dynamic MCAFsTest Primitive Test length Description

TSF0 2n {m (w0);m (r0)}TSF1 2n {m (w1);m (r1)}TTF0 3n {m (w0);m (w1);m (r1)}TTF1 3n {m (w1);m (w0);m (r0)}TWDF0 3n {m (w0);m (w0);m (r0)}TWDF1 3n {m (w1);m (w1);m (r1)}TDRDF0 3n {m (w0);m (r0);m (r0)}TDRDF1 3n {m (w1);m (r1);m (r1)}TdRDF1 4n {m (w0);m (r0, r0)}+{m (r0)}TdRDF2 4n {m (w1);m (r1, r1)}+{m (r1)}TdRDF3 4n {m (w0);m (w0, r0)}+{m (r0)}TdRDF4 4n {m (w0);m (w1, r1)}+{m (r1)}TdRDF5 4n {m (w1);m (w1, r1)}+{m (r1)}TdRDF6 4n {m (w1);m (w0, r0)}+{m (r0)}TdTF1 4n {m (w0);m (r0, w1);m (r1)}TdTF2 4n {m (w1);m (r1, w0);m (r0)}TdTF3 4n {m (w0);m (w0, w1);m (r1)}TdTF4 4n {m (w0);m (w1, w0);m (r0)}TdTF5 4n {m (w1);m (w1, w0);m (r0)}TdTF6 4n {m (w1);m (w0, w1);m (r1)}TdWDF1 4n {m (w0);m (r0, w0);m (r0)}TdWDF2 4n {m (w1);m (r1, w1);m (r1)}TdWDF3 4n {m (w0);m (w0, w0);m (r0)}TdWDF4 4n {m (w0);m (w1, w1);m (r1)}TdWDF5 4n {m (w1);m (w1, w1);m (r1)}TdWDF6 4n {m (w1);m (w0, w0);m (r0)}

• Fault coverage: detects all single-cell static and 2-operational dynamic faults.

• Purpose: experiment with TP concept to diagnose the targeted faults (single-cellstatic & 2-operational dynamic faults) and to evaluate the importance of each ofthem

• Total test length: 94n

• Stress combination:

6.2. ADVANCED TESTS 97

1. Fast Y with solid DB

2. Fast X with solid DB

6.2 Advanced tests

Advanced tests in this section are presented to target dynamic faults, memory architec-ture faults and two-port faults.

6.2.1 Tests for dynamic faults

Dynamic faults are divided into dynamic memory cell array faults, dynamic addressdecoder faults and dynamic peripheral circuit faults.

Test for dynamic memory cell array faults (dMCAFs): March MRAW


Table 6.2: March MRAW{m (w0);⇑ (r0, w1, r1, w1, r1); ⇑ (r1, w0, r0, w0, r0);⇓ (r0, w1, r1, w1, r1); ⇓ (r1, w0, r0, w0, r0);m (r0)}

• Fault coverage: detects a set of realistic dMCAFs; it also covers all static memorycell array faults, static address decoder faults and static peripheral circuits faults.

• Test length: 22n


- Fast X with solid DB

- Fast Y with solid DB

Test for dynamic address decoder faults (dADFs): March dADF

• Description: there are two optional tests for dADFs; see Table 6.3

Table 6.3: March ADMarch AD-R-C {⇑C (w0);⇑C (r0);⇑C (w1)};⇑C (r1)March AD-RaW2-C {⇑C (w0);⇑C (r0, w0);⇑C (w1);⇑C (r1, w1)}

• Explanation: C is the complement addressing method (refer to Chapter 5 for moredetail).

• Fault coverage: detects all faults in dynamic address decoders


• Test length:

- For March AD-R-C: 6n

- For March AD-RaW2-C: 9n


– Fast X with Row Stripe for row address decoder faults

– Fast Y with Column Stripe for column address decoder faults

Tests for dynamic peripheral circuit faults (dPCFs): March BLIWD andMarch SAPR

Dynamic peripheral circuit faults include slow write driver faults, slow sense amplifierfaults, slow precharge circuit faults and bit line imbalance faults. To detect all of thosefaults, both March BLIWD and March SAPR must be applied.

• March BLIWD:

- Description: see Table 6.4

Table 6.4: March BLIWD{m (w0);m (w1, r1, w0);m (w1);m (w0, r0, w1)}

- Fault coverage: detects bit line imbalance faults (BLIFs) and slow write driverfaults (SWDFs).

- Test length: 8n

- Stress combination: Fast X with solid DB.

• March SAPR


Table 6.5: March SAPR{m (w0);m (r0, w1);m (r1, w0)}

- Fault coverage: detects slow sense amplifier faults (SSAFs) and slow prechargecircuits faults (SPRFs).

- Test length: 5n

- Stress combination: Fast X with solid DB.


6.2.2 Tests for memory architecture faults

Memory architecture faults consist of intra-word faults and byte-write enable faults. Inaddition, intra-word faults are again divided into static intra-word faults and dynamicintra-word faults (dynamic means timing related).

Tests for intra-word faults

• Test for static intra-word faults: March SAM

Its data background sequence (DBS) and operation sequence (OS) varies as thesize of the word B extends. Below we will begin with the most basic situationwhere B=2, and the further case can be derived from it.

- Beginning case: March SAM for B=2

* Description: see Table 6.6

Table 6.6: March SAM{⇑(w00);⇑(w01, r01, w01, r01, r01);⇓(w11, r11, w11, r11, r11);⇑(w10, r10, w10, r10, r10);⇓(w00, r00, w00, r00, r00);⇑(w10, r10, w11, r11);⇓ (w01, r01, w00, r00)}

* Fault coverage: detects all intra-word static faults where the word con-tains 2 bits.

* Test length: 28n* Stress combination: Fast X

- March SAM for B>2

* Extend the data-background sequence (see [30] and Chapter 5)* Extend the operation sequence (see [30] and Chapter 5)* Construct the test

• Test for dynamic intra-word faults: March SZ


Table 6.7: March SZ{⇓ (wD);⇑ (rD, wD, rD);⇓ (rD, wD, rD)}

- “D” denotes the data-backgrounds in a word(DBs)

- Repeat the test 1 + log2 B times

- log2 B is the number of DBs


- DBs are generated as follows

* For B=2, there are 2 DBs: 00, 01* For B=4, there are 3 DBs: 0000, 0101, 0011* For B=8, there are 4 DBs: 00000000, 01010101, 00110011, 00001111

- Fault coverage: detects dynamic intra-word faults, interferences between I/Opaths and timing related faults

- Test length: (1 + log2 B) · 7 · nB

- Stress combination: Fast X and Fast Y

Test for byte write enable faults (BWEFs): Test BWE

BWEFs consist of BWE open faults and BWE short/bridging faults. BWE openfaults are covered by March MRAW. BWE short/bridging faults require only one testto detect them: Test BWE.

• Description: see Figure 6.1

Repeat with complementary data;

Select one row (R) and write 0’s;

for each BWEi { Enable BWEi; write 1’s in R; read from R; write 0’s in R; disable BWEi;}

Figure 6.1: Test BWE

• Fault coverage: detects all BWE short/bridging faults

• Test length: θ(#BWE · RB ) (#BWE is the number of BWE, R is the number of

cells in one memory row and B is the word size). It means the test length is linearwith the number of words per row and the the number of BWE.

• Stress combination: Solid DB

6.2.3 Tests for two-port faults (2PFs)

Two-port faults consist of two different groups of faults. First, faults requiring simulta-neous access of two ports on a single address (these need March s2PF [29]). Second,faults requiring simultaneous access of two port to different addresses (these need Marchd2PF [29]).


• March s2PF


Table 6.8: March s2PF{⇑ (w0 : n);⇑ (r0 : r0, r0 : −, w1 : r0);⇑ (r1 : r1, r1 : −, w0 : r1);⇓ (r0 : r0, r0 : −, r0 : w1);⇓ (r1 : r1, r1 : −, r1 : w0);⇑ (r0 : −)}

- Explanation:

* “n” denotes no operation through the second port* “:” denotes that the operations are applied simultaneously through the

two ports* “-” can be either replaced with a read operation or with “n” (meaning

no-operation)

- Fault coverage: the test detect all 2PF1, all 2PF2aa and all 2PF2vv with adeterministic read value [29]

- Test length: 14n

- Stress combination: Fast X with solid DB

• March d2PF


Table 6.9: March d2PF{⇑ (w0 : n);⇑c⇑r (w1r,c : r0r+1,c);⇑c⇑r (w1r,c : r1r+1,c);

⇓c⇑r (w0r,c : r1r+1,c);⇓c⇓r (w0r,c : r0r+1,c);⇑c⇑r (w1r,c : r0r,c+1);⇑c⇑r (w1r,c : r1r,c+1);⇓c⇑r (w0r,c : r1r,c+1);⇓c⇓r (w0r,c : r0r,c+1);

Switch the port and apply the same patterns again}

- Explanation:

* “⇑c⇑r” denotes a nested addressing, where the column c goes from 0 toC-1 (C is the number of columns), and for each c, the row r goes from 0to R-1 (R is the number of rows).

* “:” denotes that the operations are applied simultaneously through thetwo ports

* “w1r,c” denotes applying a write 1 operation to a cell with row r andcolumn c

* “w1r,c : r0r+1,c” denotes performing a write 1 (to the cell with row rand column c) and a read 0 (to the cells with row r+1 and column c)simultaneously. The write operation is performed through port 1 and theread operation is performed through port 2.

* n in the test denotes a no-operation

- Test length: 2 · 9n=18n


- Fault coverage: all 2PF2av faults [29]

- Stress combination: Fast X with solid DB or row stripes

6.3 Special tests

The outgoing quality of the memory can be improved by incorporating a numberof memory tests into the test program that target unknown and unmodeled failuremechanisms. Good tests of this type can only be identified using field experimentsand by experience in the industry. The following tests should be included into the testprogram, which are designed to target faults such as dynamic faults, partial faults,transient faults and soft faults. Those faults are supposed to be caused by unmodeledfailure mechanisms such as process variation.

Gal9R test [17]


Table 6.10: Gal9R{⇑ (w0);⇑b (w1b, ¤(r0, r1b), w0b);⇓ (w1);⇓b (w0b, ¤(r1, r0b), w1b)}

• Explanation: A ¤ denotes the eight neighbor cells of any base cell. The implemen-tation process is as follows. Initialize the memory to 0 (⇑ (w0)), then go in thefast X or Y addressing for each base cell (b) in the memory, do the following

- Select the 8 neighbors of the base cell (b)

- Apply w1 to the base cell

- Apply read 0 to the 8 neighbor cells, and after each read apply read 1 to thebase cell

- Write the base cell back to 0

- Repeat the test with inverse data

• Fault coverage: expected to detect special faults such as cell stability and leakagecurrents faults. As this test is for experimental use, the exact faults covered by itremain to be disclosed by practical implementation.


• Stress combination: Fast X or Fast Y with solid DB

Gal9RW2 test [10]


6.3. SPECIAL TESTS 103

Table 6.11: Gal9RW2{⇑ (w0);⇑b (w1b, ¤(r0, w1, r1b, r1, w0, r1b), w0b);⇓ (w1);⇓b (w0b, ¤(r1, w0, r0b, r0, w1, r0b), w1b)}

• Fault coverage: expected to cover special faults such as coupling-cell dynamicfaults. As this test is for experimental use, the exact faults covered by it remainsto be disclosed by practical implementation.


• Stress combination: Fast X or Fast Y with solid DB

HammerWRh test [10]


Table 6.12: HammerWRh{mb (¤(w0, w1b, r1

hb , r0));

mb (¤(w1, w0b, r0hb , r1))}

• Explanation: “h” stands for hammer, which means the pertaining operation isconsecutively applied to the same cell for h times, whereby h≥5.

• All operations must be applied back-to-back

• Fault coverage: expected to cover transient faults and partial faults. Transientfaults are faults that are only temporarily sensitized. These faults should bedetected right away by a detecting read operation, otherwise the faults will beautomatically corrected. Partial faults need multiple operations to be sensitized;therefore a hammer operation is used. As this test is for experimental use, theexact faults covered by it remains to be disclosed by practical implementation.

• Test length: 48n + 16h · n• Stress combination: Fast X or Fast Y with solid DB

HammerWhRh test [10]


Table 6.13: HammerWhRh{mb (¤(w1h, w0, w1b, r1

hb , r0));

mb (¤(w0h, w1, w0b, r0hb , r1))}

• All operations must be applied back-to-back


• Fault coverage: expected to cover transient faults and partial faults. As this testis an extended version of HammerWRh, their experimental fault coverage shouldbe compared.

• Test length: 48n + 32h · n• Stress combination: Fast X or Fast Y with solid DB

Test for DRFs: March DRF [10]


Table 6.14: March DRF{m (w0); lowerV dd,m (rx); Del, normalV dd,m (r0);m (w1); lowerV dd,m (rx); Del, normalV dd,m (r1)}

• Explanation: “Del” means a time delay (the exact time is design & technologydependent)

• Test length: 6n + 2 ·Del

• Stress combination: Fast X with checkerboard DB

ConDRF test [10]


Table 6.15: ConDRF{m (w0h, r0); Del,m (r0);m (w1h, r1); Del,m (r1);

m (w0h, w1); Del,m (r1);m (w1h, w0); Del,m (r0)}

• h≥5

• Fault coverage: expected to cover conditional data retention faults, which aredata retention faults that only get sensitized when a specific fault is sensitized.

• Test length: 8n + 4h · n + 4 ·Del

• Stress combination: Fast X with checkerboard DB

6.4 Summary

Table 6.16 lists all the tests introduced in this chapter, along with a summary of theirtest length, targeted faults and the minimum of stresses needed for their implementation.In the table, “DB” stands for data background, “n” stands for the size of the memory,#BWE stands for the number of BWE, “B” stands for the word size, “R” stands for thenumber of cells in a memory row, while “h” stands for the number of hammering.

6.4. SUMMARY 105

Table 6.16: Summary of all tests

Test Test length Expected faults Minimum stresses

Test Primitives 94n Single-cell static faults Fast Y with solid DBSingle-cell dynamic faults Fast X with solid DB

March MRAW 22n Realistic dynamic MCAFs Fast X with solid DBStatic MCAFs Fast Y with solid DBStatic ADFsStatic PCFs

March AD-R-C 6n Dynamic ADFs Fast X with Row Stripe DBFast Y with Column Stripe DB

March AD-RaW2-C 9n Dynamic ADFs Fast X with Row Stripe DBFast Y with Column Stripe DB

March BLIWD 8n Dynamic PCFs Fast X with solid DB

March SAPR 5n Dynamic PCFs Fast X with solid DB

March SAM (1 + 28 log2 B) nB

Static intra-word faults Fast X, predefined DB

March SZ (1 + log2 B) · 7 · nB

Dynamic intra-word faults Fast X, predefined DBFast Y, predefined DB

Test BWE θ(#BWE · RB

) BWEN faults Solid DB

March s2PF 14n 2PF1, 2PF2vv and 2PFaa Fast X with solid DB

March d2PF 18n 2PFav Fast X with solid DBFast X with row strip DB

Gal9R 36n Cell stability faults Fast X with solid DBLeakage currents faults Fast Y with solid DB

Gal9RW2 102n Coupling-cell dynamic MCAFs Fast X with solid DBFast Y with solid DB

HammerWRh 48n + 16h · n Transient faults Fast X with solid DBPartial faults Fast Y with solid DB

HammerWhRh 48n + 32h · n Transient faults Fast X with solid DBPartial faults Fast Y with solid DB

March DRF 6n + 2 ·Del Data retention faults Fast X, checkerboard DB

ConDRF 8n + 4h · n + 4 ·Del Conditional data retention faults Fast X, checkerboard DB

Work in Altera 7Previous chapters are all concerned with theoretical research, whereas memory testingis strongly related to the industry. On the one hand, the industry benefits frommemory testing by promoting its product yield and improving its design and fabricationtechnology. On the other hand, memory testing is driven by the industry in terms ofthree aspects. To begin with, the realistic fault models can be developed and validatedby understanding the practical structure of memory chips used in the industry. Inaddition, the test algorithms can be designed based on the realistic fault models andthe operation limitation within the industry. Finally, new fault models and the trendof future faults are able to be figured out by analyzing data collected from the volumetest in the industry. As a result, the cooperation of memory testing with the industry isprofitable and necessary to each other, which gives rise to my work in Altera as a partof my thesis.

This chapter is organized as follows. Section 1 describes the plan of the JointDevelopment Project (JDP). Section 2 presents the information of test implementation.Section 3 provides the additional achievements obtained in Altera. Section 4 ends thechapter with a summary.

7.1 Plan of the JDP with Altera7.2 Test implementation7.3 Additional achievements7.4 Summary

107

108 CHAPTER 7. WORK IN ALTERA

7.1 Plan of the JDP with Altera

Ascribing to the different between theoretical research in Delft and the practicalsituation in Altera, the plan has been modified twice before the final plan was exported.In Table 7.1 the final plan is described, where the right column displays specific workcarried out in Altera and the left column indicates the corresponding time spent onthose work.

Table 7.1: Time plan of JDPTime Work

March 24 ∼ April 18 Explain all the algorithms proposed by TU Delft

April 21 ∼ April 25 Understand Altera BIST and memory architecture

April 28 ∼ May 9 Understand Altera test setup

May 12 ∼ May 16 Verify the selected tests

May 19 ∼ May 21 Research the influence of stress combinations

May 22 ∼ May 30 Structurize the test for dynamic address decoders

June 2 ∼ June 5 Compare March MRAW and March LR

June 6 Compare small memory and big memory

June 9 ∼ June 20 Evaluate CRAM architecture and develop test algorithms

7.2 Test implementation

Ascribing to some restriction of the BIST in Altera and their corporate plan, there area couple of tests unimplemented. All the test information is incorporated in Table 7.2.

Table 7.2: Test implementation

Test Implementation status Explanation

March MRAW Validated on FPGA chip of Stratix III Volume test is deferred by corporate plan

March BLIWD Validated on FPGA chip of Stratix III Volume test is deferred by corporate plan

March SAPR Validated on FPGA chip of Stratix III Volume test is deferred by corporate plan

March s2PF Implemented previously

March d2PF Implemented previously

Test Primitives Not implemented Fault diagnosis is the work of Product Engineering group

March AD-R-C Not implemented Not supported by current BIST

March AD-Raw2-C Not implemented Not supported by current BIST

March SAM Not implemented Not supported by current BIST

March SZ Not implemented Not supported by current BIST

Test BWE Not implemented Not supported by current BIST

Gal9R Not implemented Not supported by current BIST

Gal9RW2 Not implemented Not supported by current BIST

HammerWRh Not implemented Not supported by current BIST

HammerWhRh Not implemented Not supported by current BIST

March DRF Not implemented Not supported by current BIST

ConDRF Not implemented Not supported by current BIST

7.3. ADDITIONAL ACHIEVEMENTS OF THE JDP 109

The design and implementation of new BIST takes a couple of months to be finished,in addition to which, Altera holds the plan of implementing the volume test of all abovetests on 65nm technology in the end of 2008. After the 45nm chips export a volumequantity, the volume test will be done depending on the result from 65nm chips. There-fore, it is expected that the test result can be obtained through the middle or the endof 2009.

7.3 Additional achievements of the JDP

In addition to the test implementation, there are also other achievements obtained inAltera, which are introduced below.

1. Explain all the algorithms proposed by TU Delft

• DescriptionAmong all the test algorithms proposed by TU Delft, only two tests, namelyMarch s2PF and March d2PF, have ever been implemented by Altera. There-fore, other tests are new to Altera and need to be explained. The explanationis given by various of presentations with the help of power point software.During each presentation, the meaning of a test, the way it should be imple-mented, the faults it is targeting and the methodology to design such a testare explained, where the methodology is highlighted.

• AchievementEvery test has been in depth explained so that the engineers in Altera canunderstand the reason behind those tests and their importance, which servesas the base for them to choose necessary tests and develop new tests.

2. Understand Altera BIST and memory architecture

• DescriptionThe BIST for memory testing used in different companies bear different struc-tures and different capabilities to support tests. Meanwhile, the SRAM chips,built on the similar theory though, hold different architectures. Hence in aspecific company like Altera, both these two factors may lead to low prob-ability of a fault and the operation limitation of a test. Consequently, it isnecessary for me to understand their BIST and memory architecture, so as toselect some tests, modify some tests, modify the BIST circuitry and changethe stress combination during test implementation. The understanding ofBIST is based on its functional level, from which I can figure out its dataflow, the function of different modules and pins and the relationship amongDUT, BIST and the tester.

• AchievementIt is found that only three tests, namely March MRAW, March BLIWD andMarch SAPR, are supportable by the Altera BIST. Therefore, we decided to


validate these three applicable tests first. In addition, the Altera memoriesare adopting the inter-leaved structure , having reduced the probability ofthe coupling-cell faults, so March SAM and March SZ are assigned with lowpriority. Moreover, Altera is using dynamic address decoders instead of staticaddress decoders, which also changes the fault behavior that we considered inDelft; thus I need to design a new test whose new march test operations, newstress combinations and new addressing method are all different from MarchdADF that we proposed before.

3. Understand Altera test setup

• DescriptionTo familiarize myself with testing, I attempted to learn the flow chart oftesting, the function of different testing devices and their relationship, andthe testing environment. Besides, I also studied the test setup procedureand TCL, the setup program code, which helps me to verify the three testsmentioned above. Finally I studied Verilog code to prepare myself for newBIST design.

• AchievementObtained the big image of memory test implementation and the specific test-ing environment within Altera. Grasped the basic knowledge of programmingwith TCL and Verilog.

4. Research the influence of stress combinations

• DescriptionStress combination is the way that a test is implemented, which proves to beinfluencial to fault coverage. During the work I have done research regardingthe overall influence of different stress combinations and analyzed the utilityof different stress combinations for a specific test.

• AchievementA systematic conclusion in terms of the impact of environmental stresses andalgorithmic stresses have been obtained, which helps Altera to define stresscombinations for other tests in the future. However, it should be put into mindthat such a systematic conclusion is quite general and may vary concerninga specific test; thus a presentation respecting the utility of different stresscombinations for their corresponding tests was given, which contributes toAltera’s selection of the most stressful combination and the combinationsthey hope to experiment. More important, during the research a new stresscombination is discovered, which I named after “output latch inertia stress”.This stress represents that the previous stored information in the output latchhas a inertia to retain its value and thus affect the state of next read out.Such a stress manifests its utility in the methodology of developing tests forperipheral circuits faults and dynamic address decoder faults.

5. Develop the test for dynamic address decoders

7.3. ADDITIONAL ACHIEVEMENTS OF THE JDP 111

• DescriptionThe address decoder circuitries differ in industry and can be generally classi-fied as static address decoders and dynamic address decoders, which broughtmore variation in considering our test algorithm targeting correspondingdADFs. Our original test program targets the static address decoders whileAltera uses dynamic address decoders, which requires a modification of ourprevious test. The modification is processed through the establishment offault models on transistor level, the test algorithm development and the BISTdesign.

• AchievementThe previous test March dADF is completely modified in three aspects: ad-dressing method, march test operations and stress combinations. In addition,the address generating circuitry in BIST was also designed. All detailed in-formation regarding this can be found in Section 5.7.

6. Compare March MRAW and March LR

• DescriptionAltera has exerted March LR as their main test to target MCAFs (memory cellarray faults); more important is that they modified the March LR into MarchLR2 by adding two read operations in the original version, which is convincingto cover deceptive read destructive faults. Therefore, they hopes to knowwhat added value March MRAW has brought in, based on the comparisonbetween them. The comparison between March LR and March MRAW andthe comparison between March LR2 and March MRAW are both carried out.The fault space is the faults respectively covered by each of them, except thelinked faults since such faults only occupy a fairly limited proportion.

• AchievementThe comparison returns a positive conclusion for March MRAW . All faultscovered by March LR and March LR2 except bit line imbalance faults, canalso be covered by March MRAW. Only a subset of faults covered by MarchMRAW can be covered by March LR, including below:

- 8 out of 12 regarding single-cell static faults- 18 out of 26 regarding coupling-cell static faults- 6 out of 16 regarding single-cell dynamic faults- 14 out of 48 regarding coupling-cell dynamic faults

Only a subset of faults covered by March MRAW can be covered by MarchLR2, including below:

- 10 out of 12 regarding single-cell static faults- 20 out of 26 regarding coupling-cell static faults- 8 out of 16 regarding single-cell dynamic faults- 16 out of 48 regarding coupling-cell dynamic faults

7. Compare small memory and big memory


• DescriptionOther than using a big memory in the FPGA chip, Altera distributes severalsmall memories in one chip so as to obtain higher speed and less faults. Whilethe latter needs to be assured by rational analysis. Said Hamdioui has earlyaddressed such a problem in [27].

• AchievementFrom [27] comes that big memory indeed involves more faults, especiallycoupling-cell faults due to the high possibility of cross talk and time-relatedfaults due to the high resistance of long lines.

8. Evaluate CRAM architecture and develop algorithms

• DescriptionCRAM is the ram used in Altera FPGA to store the data bits, which is re-markably essential for the reliability of its FPGA chips. Due to the specialfunctionality, CRAM differs greatly in cell architecture from ordinary SRAM,so its fault space is different; besides, it incorporates a huge operation limi-tations, for which case normal march tests can not be applied. Therefore itrequires new theoretical approach and new test algorithms for testing.

• AchievementRealistic fault models are validated. New test algorithms are designed.

7.4. SUMMARY 113

7.4 Summary

The JDP program between Delft University of Technology and Altera corporation issuccessful and meaningful.

On the one hand, Altera obtained the deep understanding of memory testing theory,which facilitates their future development and evaluation of new test algorithms; further,the volume test in the coming future expects to grant Altera a high fault coverage andthus enhance product yield to a great extent; moreover, the data analysis of the volumetest will equip Altera with more knowledge of their memory product in terms of thedesign and fabrication, which guides their new design and technology. On the other hand,via this program TU Delft obtained the practical information from industry, convincedAltera to apply most of its proposed tests and will harvest rich volume data in the future.All those achievements will help TU Delft to establish privilege for future collaboration,to suit current research to industrial prospective, and to predict future trend of memorytesting.

Conclusion andrecommendations 8This thesis is an overall study of SRAM testing referring to the history , the currentdevelopment and the future state-of-art of memory testing. In this thesis, the contentcovers a comprehensive perspective in terms of the theory of SRAM structure, establish-ment of fault models, development of test algorithms that target both faults detectionand diagnosis, and test implementation. Through the whole thesis there are severalcontributions mainly regarding the faults diagnosis, development of tests for CRAMand development of tests for dynamic address decoders.

Beginning with the SRAM structure, the thesis describes the SRAM with respectsto its circuitry characteristics, different functional modules and process of read andwrite operations. Based on such illustrations, further studies of memory testing canbe carried out. For instance, the fault model validation and inductive fault analysiscan be processed based on the understanding of SRAM circuitry, which is a significantmethodology in fault analysis before exploiting exhaustive experiments. In addition, thedivision of SRAM into different functional modules also gives rise to the correspondingdivision of fault models, which greatly simplifies the approach of faults space andclassification. Moreover, since the read and write operation involve all the functionalmodules, all the faulty behavior in different modules and different levels can be mappedto a failed read or failed write. This to a large extent reduce the difficulty of definingfunctional fault models, and it also constitutes the base of the concept of march test,the most expansively used memory test. Finally, the understanding of SRAM structureis the fundament to modify SRAM topology with the feedback of memory testing.

Based on the introduction of SRAM structures, the thesis proceeds to the descriptionof its functional fault models. Firstly the concept of fault primitive is introduced,followed by its classification. The functional model of a memory depends on its specificimplementation, for test purposes a so called ‘reduced functional memory model’ isused that only consists of three subsystems: the address decoder, the memory cellarray and the read/write logic. Since the vast majority of mainstream memory devicescontains these three subsystems, the reduced functional fault model is, to a large extent,independent of specific memory implementations. Thus, the fault models based onthe functional model will be valid for most cases. Those fault models are memory cellarray faults, address decoder faults and peripheral circuits faults. In addition, thefaults related to memory architecture are also discussed, i.e., word-oriented faults andbyte-write-enable faults.

Further more, as fault diagnosis is seeing increasing importance, the latest faultdiagnostic methodology of test primitive (TP) is probed. Firstly the concept of march

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116 CHAPTER 8. CONCLUSION AND RECOMMENDATIONS

test is introduced; together with the concept of fault primitive, the philosophy of testprimitive is come up with. It is pointed out that TP has five main advantages, i.e.,extensibility, platform independence, unknown fault identification, customer returnanalysis and test program efficiency improvement. Then a large amount of TPs formemory cell array faults (MCAFs) are generated, during which several innovations arebrought forth; e.g., the principles such as the TP Evaluator to regulate the generationof TPs to meet the criterion of TPs, the concept of Combined TP to enhance thediagnostic ability and the structrized procedure of generating the diagnostic dictionaryusing TPs.

Corresponding to fault models presented in Chapter 3, the thesis moves on tosummarize a series of existing tests. Since each test is derived from a systematic andextensive method, they can not only be applied for current testing, but also for inspiringfurther development of new tests. Two typical examples are tests for dynamic addressdecoder faults and intra-word faults. The tests for dynamic address decoder faults [56]are developed based on a defect injection method, and they are constituted in twophases; i.e., to generate sensitizing address transitions and sensitizing operations. Thismethod brings in a systematic way for future research in dealing with address decoderfaults. Just edified by this, the new tests for dynamic address decoders are designed,where the addressing method, operations and stress combinations are all changed. Incomparison, the test for intra-word faults provides a structured way of data backgrounddevelopment, which is mainly from algorithmic point of view [30].

Then the whole test program for Altera composed of 3 groups of tests are designed,which is to realize fault diagnosis, to cover new emerging faults like dynamic faults andto detect special faults in SRAMs. In the test program every test is fed with detailedinformation like test description, fault coverage, test length and stress combination,which can be directly read and implemented for test engineers.

The last phase of this thesis work is carried out during the direct involvementwith the industry (Altera corporation). The whole work comprises of “explain all thealgorithms proposed by TU Delft”, “understand Altera BIST and memory architecture”,“understand Altera test setup”, “verify the selected tests”, “research the influence ofstress combinations”, “structurize the test for dynamic address decoders”, “compareMarch MRAW and March LR”, “compare small memory and big memory” and“evaluate CRAM architecture and develop corresponding test algorithms”. Whereby“understand Altera test setup” and “verify the selected tests” refer to the practicalimplementation of memory tests in industry, “structurize the test for dynamic addressdecoders” gives rise to a new test and consolidates the methodology raised by Saidhamdioui and Zaid Al-Ars, and “research the influence of stress combinations” leadsto the manifestation of output latch inertia stress. More important, “evaluate CRAMarchitecture and develop corresponding test algorithms” addresses a complete processof test development that it is from fault model establishment to test algorithm definition.

Via the whole thesis work that covers a comprehensive perspective of memory

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testing, the future trend and recommendations for memory testing can also be derivedas below.

• Fault model: Establish new fault models for deep-submicron technology

• Fault diagnosis: Diagnose faults in an extensible, platform-independent and effi-cient way

• Design of test algorithm: Suit specific test algorithms to specific memory structures

• Impact of stress: Study the influence of stress combinations in a systematic way

118 CHAPTER 8. CONCLUSION AND RECOMMENDATIONS

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