mpc885ads powerquicc™ application development system … · mpc885adsug 6/2004 rev. 1 mpc885ads...

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Freescale Semiconductor, Inc.n

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MPC885ADSUG6/2004Rev. 1

MPC885ADS PowerQUICC™Application Development System

User’s Guide

For More Information On This Product,

Go to: www.freescale.com

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ii MPC885ADS User’s Guide MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product, Go to: www.freescale.com

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Contents

Chapter 1 General Information

1.1 Introduction.......................................................................................................... 1-11.2 MPC885ADS Objectives ..................................................................................... 1-11.3 Abbreviations List................................................................................................ 1-11.4 Related Documentation........................................................................................ 1-21.5 Specifications....................................................................................................... 1-21.6 MPC885ADS Features ........................................................................................ 1-2

Chapter 2 Hardware Preparation and Installation

2.1 Introduction.......................................................................................................... 2-12.2 Unpacking Instructions ........................................................................................ 2-12.3 Hardware Preparation .......................................................................................... 2-12.3.1 Replacing the MPC885 Microprocessor.......................................................... 2-32.3.2 MODCKx—Dip Switch 7 ............................................................................... 2-32.3.3 CPM Multiplexing—Dip Switch 2 .................................................................. 2-32.4 Installation Instructions........................................................................................ 2-42.4.1 Standalone Operation....................................................................................... 2-42.4.2 Debug Port Operation ...................................................................................... 2-52.4.3 J14—+5-V Power Supply Connection ............................................................ 2-52.4.4 J15: +12-V Power Supply Connection ............................................................ 2-62.4.5 J21—Debug Port Connector............................................................................ 2-62.4.6 Terminal to MPC885ADS EIA 232 Connection ............................................. 2-72.4.7 Memory Installation......................................................................................... 2-7

Chapter 3 Operating Instructions

3.1 Introduction.......................................................................................................... 3-13.2 Controls and Indicators ........................................................................................ 3-1

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3.2.1 Abort Switch—SW6........................................................................................ 3-13.2.2 Soft Reset Switch—SW5................................................................................. 3-13.2.3 Hard Reset Switches—SW5 and SW6 ............................................................ 3-13.2.4 Software Options Switch—SW4 ..................................................................... 3-23.2.5 LED Indicators................................................................................................. 3-23.3 Memory Map ....................................................................................................... 3-33.4 MPC885 Registers Programming ........................................................................ 3-53.4.1 Memory Controller Registers Programming ................................................... 3-53.4.2 Chip Selects and Memory Mapping ................................................................ 3-6

Chapter 4 Functional Description

4.1 Reset and Reset Configuration ............................................................................ 4-14.1.1 Regular Power-On Reset ................................................................................. 4-14.1.2 Manual Soft Reset............................................................................................ 4-14.1.3 Manual Hard Reset .......................................................................................... 4-24.1.4 MPC885 Internal Sources................................................................................ 4-24.1.5 Reset Configuration ......................................................................................... 4-24.1.5.1 Power-On Reset Configuration.................................................................... 4-24.1.5.2 Hard-Reset Configuration............................................................................ 4-34.1.5.3 Soft-Reset Configuration ............................................................................. 4-34.2 Local Interrupter .................................................................................................. 4-44.3 Buffering .............................................................................................................. 4-44.4 Chip-Select Generator.......................................................................................... 4-44.5 Flash Memory SIMM .......................................................................................... 4-54.6 Synchronous DRAM............................................................................................ 4-54.6.1 SDRAM Programming .................................................................................... 4-94.6.1.1 SDRAM Initializing Procedure ................................................................... 4-94.6.2 SDRAM Refresh............................................................................................ 4-104.7 Protocol Selection .............................................................................................. 4-104.7.1 ATM25........................................................................................................... 4-104.7.1.1 Physical Interface....................................................................................... 4-104.7.1.2 Board Configuration (Strap/Switch).......................................................... 4-104.7.2 ATM155......................................................................................................... 4-104.7.2.1 Physical Interface....................................................................................... 4-114.7.2.2 Board Configuration (Strap/Switch).......................................................... 4-114.7.3 10Base-T Ethernet Operation ........................................................................ 4-114.7.3.1 Physical Interface....................................................................................... 4-114.7.3.2 Board Configuration (Strap/Switch).......................................................... 4-114.7.4 100Base-T Ethernet Operation ...................................................................... 4-11

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4.7.4.1 Physical Interface....................................................................................... 4-124.7.4.2 Board Configuration (Strap/Switch).......................................................... 4-124.7.5 T1/E1 Framer................................................................................................. 4-124.7.5.1 Physical Interface....................................................................................... 4-124.7.5.2 Board Configuration (strap/switch) ........................................................... 4-124.7.6 EIA232 Interfaces .......................................................................................... 4-124.7.6.1 Physical Interface....................................................................................... 4-124.7.6.2 Board Configuration (Strap/Switch).......................................................... 4-134.7.7 IrDA............................................................................................................... 4-134.7.8 USB 2.0 Full-/Low-Speed Interface .............................................................. 4-134.7.8.1 Physical Interface....................................................................................... 4-144.7.8.2 Board Configuration (Strap/Switch).......................................................... 4-144.7.9 PCMCIA Interface......................................................................................... 4-144.7.9.1 Physical Interface....................................................................................... 4-144.7.9.2 Board Configuration (Strap/Switch).......................................................... 4-164.7.9.3 PCMCIA Power Control............................................................................ 4-164.7.10 I2C Interface .................................................................................................. 4-164.8 BCSR—Board Control and Status Register ...................................................... 4-164.8.1 BCSR Disable Protection Logic .................................................................... 4-174.8.2 BCSR0—Hard Reset Configuration Register................................................ 4-174.8.3 BCSR1—Board Control Register 1............................................................... 4-194.8.4 BCSR2—Board Control / Status Register 2 .................................................. 4-214.8.5 BCSR3—Board Control / Status Register 3 .................................................. 4-214.8.6 BCSR4—Board Control / Status Register 4 .................................................. 4-224.8.7 BCSR5—Board Control / Status Register 5 .................................................. 4-234.9 Debug Port Controller........................................................................................ 4-234.9.1 MPC885ADS As Debug Port Controller For Target System ........................ 4-244.9.1.1 Debug Port Connection—Target System Requirements ........................... 4-244.9.2 Debug Port Control / Status Register............................................................. 4-254.9.3 Standard MPC885 Debug Port Connector Pin Description........................... 4-264.9.3.1 VFLS(0:1).................................................................................................. 4-264.9.3.2 HRESET .................................................................................................... 4-264.9.3.3 SRESET..................................................................................................... 4-274.9.3.4 DSDI—Debug-Port Serial Data In ............................................................ 4-274.9.3.5 DSCK—Debug-Port Serial Clock ............................................................. 4-274.9.3.6 DSDO—Debug-Port Serial Data Out........................................................ 4-274.10 Power Supplies .................................................................................................. 4-274.10.1 Power to Board .............................................................................................. 4-274.10.2 Processor Power............................................................................................. 4-284.10.3 Other On-Board Power .................................................................................. 4-284.10.4 PCMCIA Interface......................................................................................... 4-28

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4.10.5 USB Interface ................................................................................................ 4-28

Chapter 5 Support Information

5.1 Interconnect Signals............................................................................................. 5-15.1.1 J34—10BaseT Ethernet Port Connector.......................................................... 5-25.1.2 J33A and J33B—EIA232 Ports Connectors.................................................... 5-25.1.3 J22—T1/E1 RJ45 Connector ........................................................................... 5-45.1.4 J8—ATM25 RJ45 Connector........................................................................... 5-45.1.5 U14—ATM155 Multi-Mode Optical Connector ............................................. 5-55.1.6 MPC885ADS J31—CPM Expansion Connector ............................................ 5-55.1.7 J23, J24, J25, J26, J27, J28, J29, and J30 Logic Analyzer Connectors ........... 5-85.1.8 J21—External Debug Port Controller Input Interconnect ............................. 5-145.1.9 J35 and J36—100BaseT Ethernet Port Connectors....................................... 5-155.1.10 J15—12-V Power Connector......................................................................... 5-155.1.11 J14—5-V Power Connector........................................................................... 5-165.1.12 J14—2.1-mm Power Jack Connector ............................................................ 5-165.1.13 J39—Mach’s In-System Programming (ISP) ................................................ 5-165.1.14 J13—JTAG Connector For Altera Programing ............................................. 5-175.1.15 Expansion Connector ADD, Data Control, and PCMCIA Port..................... 5-175.1.16 PCMCIA Port Connector............................................................................... 5-215.2 MPC885ADS Part List ...................................................................................... 5-24

Appendix A Revision History

A.1 Revision Changes From Revision 0.03 to Revision 1 ........................................ A-1

Appendix B MPC885ADS Board Schematics

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Figures

2-1 MPC885 Top Side Part Location Diagram ................................................................. 2-22-2 MPC885 Top View...................................................................................................... 2-32-3 Standalone Configuration............................................................................................ 2-52-4 J14: +5-V Power Connector........................................................................................ 2-52-5 J15: +12-V Power Connector...................................................................................... 2-62-6 BDM Connector .......................................................................................................... 2-62-7 BDM Connector Connected to the Board ................................................................... 2-72-8 J33A and J33B — DCE Connectors (Female)............................................................ 2-72-9 Memory SIMM Installation ........................................................................................ 2-83-1 SW4 Description ......................................................................................................... 3-24-1 SDRAM Connection Scheme ..................................................................................... 4-84-2 PCMCIA Port Configuration .................................................................................... 4-154-3 Standard Debug Port Connector................................................................................ 4-26

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Tables

1-1 MPC885ADS Specification ........................................................................................ 1-22-1 Dip Switch S7 Configuration...................................................................................... 2-32-2 Dip Switch S2 Configuration...................................................................................... 2-43-1 MPC885ADS LEDs.................................................................................................... 3-23-2 Memory Map in MP885ADS..................................................................................... 3-43-3 SIU Register Programming......................................................................................... 3-53-4 Memory Controller Initialization For 50 MHz Example ............................................ 3-63-5 UPMB Initialization for on-board SDRAM up to 66 MHz ........................................ 3-74-1 Power-On Reset DPLL Configuration ........................................................................ 4-34-2 MPC885ADS Chip Select Assignment....................................................................... 4-54-3 SDRAM ADD Pin Refer to MPC885 Pins ................................................................. 4-64-4 SDRAM Connected to MPC885................................................................................. 4-74-5 Estimated SDRAM Performance Figures ................................................................... 4-84-6 SDRAM’s Mode Register Programming .................................................................... 4-94-7 BCSR0 Description................................................................................................... 4-184-8 BCSR1 Description................................................................................................... 4-194-9 BCSR2 Description................................................................................................... 4-214-10 BCSR3 Description................................................................................................... 4-214-11 BCSR4 Description................................................................................................... 4-224-12 BCSR5 Description................................................................................................... 4-234-13 Debug Port Control / Status Register ........................................................................ 4-254-14 DSCK Frequency Select ........................................................................................... 4-255-1 J34—Ethernet Port Interconnect Signals .................................................................... 5-25-2 J33A and J33B Interconnect Signals .......................................................................... 5-25-3 J22—T1/E1 RJ45 Connector ...................................................................................... 5-45-4 J8—ATM25 RJ45 Connector...................................................................................... 5-45-5 J31—MPC885ADS Interconnect Signals ................................................................... 5-55-6 J23—Interconnect Signals .......................................................................................... 5-85-7 J24—Interconnect Signals .......................................................................................... 5-95-8 J25—Interconnect Signals ........................................................................................ 5-105-9 J26—Interconnect Signals ........................................................................................ 5-105-10 J27—Interconnect Signals ........................................................................................ 5-115-11 J28—Interconnect Signals ........................................................................................ 5-125-12 J29—Interconnect Signals ........................................................................................ 5-125-13 J30—Interconnect Signals ........................................................................................ 5-13

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5-14 J21—Interconnect Signals ........................................................................................ 5-145-15 J35 and J36—Ethernet Port Interconnect Signals..................................................... 5-155-16 J15—Interconnect Signals ........................................................................................ 5-155-17 J14—Interconnect Signals ........................................................................................ 5-165-18 J39 (ISP Connector)—Interconnect Signals ............................................................. 5-165-19 J13 (JTAG Connector for Altera Programing)—Interconnect Signals ..................... 5-175-20 J32—MPC885ADS’s Interconnect Signals .............................................................. 5-185-21 J11—PCMCIA Connector Interconnect Signals ...................................................... 5-215-22 MPC885ADS Part List.............................................................................................. 5-25

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Chapter 1 General Information

1.1 IntroductionThis document is an operation guide for the MPC885ADS board and contains operational,functional, and general information about the ADS board. The MPC885ADS is meant toserve as a platform for software and hardware development around the MPC885microprocessor. Using the ADS board’s on-board resources and its associated debugger, adeveloper is able to download his code, run it, set breakpoints, display memory andregisters, and connect his own proprietary hardware through the expansion connectors, tobe incorporated in a desired system with the MPC885 processor.

1.2 MPC885ADS ObjectivesThe MPC885ADS board is meant to be used as a general platform for software andhardware development around the MPC885 family. This board delivers several keyelements to the overall success of the MPC885 PowerQUICC™ processor and providesboth a direct physical interface to every processor pin and an application interface to manyof the processor functional blocks. Using its on-board resources and its associateddebugger, the developer is able to load his code, run it, set breakpoints, display memory andregisters and connect his own proprietary hardware through the expansion connectors, tobe incorporated to a system with the MPC885.

This board can also be used as a demonstration tool, that is, application software may beprogrammed into its Flash memory and run in exhibitions, and so on.

1.3 Abbreviations List• ADS—The MPC885ADS Application Development System, the subject of this

document

• UPM—User Programmable Machine

• GPCM—General-Purpose Chip-select Machine

• GPL—General-Purpose Line (associated with the UPM)

• I/R—Infrared

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• BCSR—Board Control and Status Register

• ZIF—Zero Input Force

• BGA—Ball Grid Array

• SIMM—Single In-line Memory Module

1.4 Related DocumentationMPC885 PowerQUICC™ Reference Manual

1.5 SpecificationsThe MPC885ADS specifications are given in Table 1-1.

1.6 MPC885ADS Features• MPC885, running up to 80 MHz bus frequency, mounted on ZIF BGA socket

• 8 Mbyte, unbuffered, synchronous DRAM onboard, supporting an optional loading of up to 16 Mbytes

• 8-Mbyte Flash SIMM, 5- or 12-V programmable, with automatic Flash SIMM identification

• T1/E1 PHY through TDMA

• Two 10/100BaseT Ethernet PHY supporting MII and RMII interfaces

• ATM mode operates in UTOPIA split mode or mux mode and can also work in multi or single PHY.

Table 1-1. MPC885ADS Specification

Characteristics Specification

Power requirements (no other boards attached) +5 Vdc @ 1.4 A (typical), 6 A (maximum)

MPC885 microprocessor Up to 80 MHz bus speed

Addressing:Total address range

Flash memorySynchronous DRAM

4 Gbytes

8 Mbyte8 Mbytes, SDRAM, 32 bits wide expandable to 16 Mbytes

Operating temperature 0 ºC to 30 ºC

Storage temperature –25 ºC to 85 ºC

Relative humidity 5% to 90% (non-condensing)

Dimensions:LengthWidthThickness

9.2" (234 mm)8.0" (203 mm)0.062" (1.6 mm)

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• ATM25 PHY connected to the UTOPIA interface

• ATM155 utilizing the UTOPIA interface

• Adtech-compatible UTOPIA interface

• Memory disable option for each local memory map slave

• Board control and status register (BCSR)—6 BCSRs controlling board operation

• Programmable hard-reset configuration through BCSR

• PCMCIA socket (port A) 5 V only, with full buffering, power control, and port disable option. Complies with PCMCIA 2.1+ standard

• Module enable indications

• 10BaseT port through SCC3, with standby mode

• USB 2.0 (FULL / LOW only)–compatible interface, type A and B connectors

• IrDA (115.2 Kbps) port interface support on SCC2, with standby mode

• Dual EIA232 interfaces utilizing SMC1 and SMC2, with low-power option for each port

• I2C access through header

• On-board debug port controller

• MPC885ADS serving as debug station for target system option

• External tools identification capability, through BCSR

• Expansion connectors include all the CPU/CPM ports and bus signals in order to control external peripherals (note that some pins have been reassigned)

• Soft / Hard1 reset push button

• ABRT push button

• Single2 5-V supply

• Reverse / over voltage protection for power inputs

• 1.8-V VDDL and 3.3-V VDDH

• Power indications for each power bus

• External switches for selections the ATM and Fast Ethernet options in the MPC885

• Full visibility to the processor pins through Mictor connectors

• BDM and EPP (parallel interface, not functional at this time) host interfaces

1Hard reset is applied by depressing both the soft reset and ABRT buttons.2Unless a 12-V supply is required for a PCMCIA card or for a 12-V programmable Flash SIMM.

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100BT PHY

MII/RMII

100BT PHY

MII/RMII

10BT PHY

GPSI

RS232 2 ea.

USB 2.0

IrDA

T1/E1

UTOPIA/ADTECH

ATM155Transceiver

ATM25Transceiver PCMCIA

CPM I/OSwitching

Logic(SMC 1 & 2)

(TDMA)

ControlLogic

ExpansionConnectors

SwitchedI/O Control

MuxA/D

8M FLASH(SIMM)

MPC885

(357 PinPackage)

ProgramLogic

(EPP to Serial)

A & Dx32 SDRAM

16M-Load 8M

POWER &RESET

Misc.Debug

EPP 1284A(25 Pin Host)

BDM(10 Pin)

BufferedA & D

I/OPorts

UTOPIA(FULL/LOW)



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Chapter 2 Hardware Preparation and Installation

2.1 IntroductionThis chapter provides unpacking, hardware preparation, and installation instructions for theMPC885ADS.

2.2 Unpacking InstructionsNOTE

If the shipping carton is damaged upon receipt, request thecarrier’s agent to be present during unpacking and inspection ofequipment.

Unpack equipment from the shipping carton. Refer to the packing list and verify that allitems are present. Save the packing material for storing and reshipping of equipment.

CAUTIONAVOID TOUCHING AREAS OF INTEGRATEDCIRCUITRY; STATIC DISCHARGE CAN DAMAGECIRCUITS.

2.3 Hardware PreparationTo select the desired configuration and ensure proper operation of the MPC885ADS board,the dip-switch settings or jumpers may need to be changed before installation. The locationof the switches, LEDs, dip switches, jumpers and connectors is illustrated in Figure 2-1.The board has been factory tested and is shipped with dip-switch settings as described inthe following sections.

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Figure 2-1. MPC885 Top Side Part Location Diagram



Hardware Preparation

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2.3.1 Replacing the MPC885 Microprocessor

Turn off the power before replacing the MPC885. When replacing the MPC885, note wherethe microprocessor’s A1 pin is. Place the new MPC885 with pin 1 aligned with the cornermarked near the socket. Figure 2-2 shows a top view of the MPC885. A1 is located at thetop left corner.

Figure 2-2. MPC885 Top View

2.3.2 MODCKx—Dip Switch 7

Switch S7 is a two-position switch that controls the MODCK pins of the processor.Switch 1 selects the clock source for the processor (PIT clock), while switch 2 sets theprescaler if the crystal oscillator is used. See the MPC885 PowerQUICC Family ReferenceManual for details. Table 2-1 demonstrates the switch settings for dip switch S7.

2.3.3 CPM Multiplexing—Dip Switch 2

Switch S2 is a four-position dip-switch that controls the multiplexing of the CPM pins.Table 2-2 demonstrates the switch settings for dip switch S2.

Table 2-1. Dip Switch S7 Configuration

Switch Number ON OFF

1 (MODCK1) Crystal oscillator (OSCM) 1

1 Indicates factory default.

External clock (EXTCLK)

2 (MODCK2) 4 (prescaler for OSCM) 1 512 (prescaler for OSCM)

A1

MPC885



Installation Instructions

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2.4 Installation InstructionsWhen converting software developed on the previous MPC8xxFADS board to run on theMPC885ADS, the user should make changes to the BR2, BR3, BR4, and OR4 registerprogramming as follows:

• BR2 — Set the valid bit to 0 (bit 31).

• BR3 — Set the valid bit to 0 (bit 31).

• BR4 = 0x000000C1, where “C” selects UPMB and “A” enables the valid bit, base at 0

• OR4 = 0xFF800800

This configuration will map the 8 Mb SDRAM to address 0 ending at 0x007FFFFF and willdisable CS2 and CS3 since DRAM is not present on this board. When the MPC885ADShas been configured as desired by the user, it can be installed according to the requiredworking environment in one of the following modes of operation:

• Debug port

• Standalone

2.4.1 Standalone Operation

In this mode, the ADS board may connect to a host through one of its other ports, that is,the EIA232 port, I/R port, Ethernet port, and so on. Operating in this mode requires anapplication program to be programmed into the board’s Flash memory. Figure 2-3 is anillustration of standalone operation.

Table 2-2. Dip Switch S2 Configuration

Switch Number ON OFF

1 EIA232-1 (SMC1) 1

1 Indicates factory default.

ADTECH (UTOPIA upper addresses)

2 R/MII-2 (FE2) 1 EIA232-2 (SMC2)

3 R/MII-2 (FE2) AND T1 (TDMA) 1 10BaseT (SCC3)

4 PCMCIA (port A) UTOPIA (ATM) 1




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Figure 2-3. Standalone Configuration

2.4.2 Debug Port Operation

In this mode of operation, the user controls the board through J21 (BDM Connector) withan external tool connected to the computer’s parallel port.

2.4.3 J14—+5-V Power Supply Connection

The MPC885ADS requires a +5-V DC @ 6-A maximum power supply for operation.Connect the +5-V power supply to connector J14 as shown in Figure 2-4.

Figure 2-4. J14: +5-V Power Connector

J14 is a three-terminal block power connector with a power plug. The plug is designed toaccept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. To provide solidground, two GND terminals are supplied. It is recommended to connect both GND wiresto the common of the power supply while VCC is connected with a single wire.

J14 is a connector that should be used with the power supply, which is supplied with theboard. Plug the power supply to J14.

Host Computer

5-V Power Supply

EIAS

232

Ethe

rnet

I/R

+5 V

GND

GND

1

2

3




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NOTESince hardware applications may be connected to theMPC885ADS through the expansion connectors, J31 and J32,power consumption should be taken into consideration when apower supply is connected to the MPC885ADS. In other wordswhen adding hardware into the expansion connectors,remember that the additional hardware cannot have more than1A of current consumption.

2.4.4 J15: +12-V Power Supply Connection

The MPC885ADS requires a +12-V DC @ 1-A maximum power supply for the PCMCIAchannel Flash programming capability or for +12-V programmable Flash SIMM. TheMPC885ADS can work properly without the +12-V power supply if there is no need toprogram either a 12-V programmable PCMCIA Flash card or a 12-V programmable FlashSIMM.

Connect the +12-V power supply to connector J15 as shown in Figure 2-5.

Figure 2-5. J15: +12-V Power Connector

J15 is a two-terminal block power connector with a power plug. The plug is designed toaccept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires.

2.4.5 J21—Debug Port Connector

The user can control the board through this connector. Today most control software usesthis connector through a command converter box that is connected from the other side tothe PC parallel port. Figure 2-6 shows a BDM connector.

Figure 2-6. BDM Connector

+12 V

GND

1

2

13

5

7

9

2

4

6

8

10

VFLS0 SRESETGND

GND

HRESET

V3.3

DSCK

VFLS1

DSDI

DSDO




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Figure 2-7 shows a BDM connector that is connected to the board.

Figure 2-7. BDM Connector Connected to the Board

2.4.6 Terminal to MPC885ADS EIA 232 Connection

A serial (EIA232) terminal or any other EIA232 equipment, may be connected to theEIA232 connectors, J33A and J33B. The EIA232 connector is a DB-9 pin, female, stackedD-type connector, as shown in Figure 2-8.

The connectors are arranged in a manner that allows for 1:1 connection with the serial portof a personal computer through a flat cable.

Figure 2-8. J33A and J33B — DCE Connectors (Female)

NOTEThe RTS line (pin 7) is not connected on the MPC885ADS.

2.4.7 Memory Installation

The MPC885ADS has a Flash memory SIMM. To install a memory SIMM, take it out ofits package, put it diagonally in its socket and twist it to a vertical position until the metallock clips are locked. See Figure 2-9 for an illustration of the installation.

1357

9

246810

VFLS0 SRESETGNDGNDHRESETV3.3

DSCKVFLS1DSDIDSDO

Computer

Parallel Port

MPC885ADS

1

TX 2

RX 3RTS

4CTS

5

DSR6

GND

7

CD

8

9 N.C.DTR

EIA232 Serial Port Connector




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CAUTIONThe memory SIMMs have an alignment nibble near their #1pin. It is important to align the memory correctly beforetwisting it; otherwise, both the memory SIMM and its socketmay be damaged.

Figure 2-9. Memory SIMM Installation

NOTEIf using the RPCF08324NE5BSSG-70 Flash Memory SIMM,please make sure that the resistor loading on the SIMM is asfollows:

R1-loaded, R2-no load, R3-no load, R4-loaded, R5-no load,R6-no load, and R7-loaded

(1)

(2)

SIMM Socket

Memory SIMM

Metal Lock Clip



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Chapter 3 Operating Instructions

3.1 IntroductionThis chapter provides necessary information for using the MPC885ADS in debug andstandalone configurations. This includes controls and indicators, memory map details, andsoftware initialization of the board.

3.2 Controls and IndicatorsThe MPC885ADS has the following switches and indicators.

3.2.1 Abort Switch—SW6

The abort switch, SW6, aborts program execution by issuing a level 0 interrupt to theMPC885. If the ADS is in standalone mode, it is the responsibility of the user to provide ameans of handling the interrupt since the MPC885ADS does not include a residentdebugger. The abort switch signal is debounced and cannot be disabled by software.

3.2.2 Soft Reset Switch—SW5

The soft reset switch, SW5, performs a soft reset on the MPC885 internal modules,maintaining MPC885’s configuration (clocks and chip-selects) SDRAM contents. Theswitch signal is debounced and cannot be disabled by software. At the end of the soft resetsequence, the soft-reset configuration is sampled and becomes valid.

3.2.3 Hard Reset Switches—SW5 and SW6

When both switches, SW5 and SW6, are depressed simultaneously, a hard reset isgenerated to the MPC885. When the MPC885 is hard reset, all of its configuration is lost,including data stored in the SDRAM, and the MPC885 has to be re-initialized. At the endof the hard-reset sequence, the hard-reset configuration stored in BCSR0 becomes valid.

MOTOROLA Chapter 3. Operating Instructions 3-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE


Controls and Indicators

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3.2.4 Software Options Switch—SW4

SW4 is a general purpose 4-switch dip-switch, which is available to the user as an input. Itis not used on the board. This switch is connected over the EXTOLI(0:3) lines, which areavailable in BCSR. Software options may be manually selected according to the stat ofSW4.

Figure 3-1. SW4 Description

3.2.5 LED Indicators

The following table lists each LED provided on the ADS board and its function.Table 3-1. MPC885ADS LEDs

LED Name Color Function/Source

RUN Green Controlled by the host interface PLD

5V POWER Green Tied to board’s VCC

SDRAM ENABLED Yellow Output from BCSR

SIGNAL LAMP Green User controlled from BCSR

RESERVED Yellow Output from BCSR PLD—formerly DRAM enable

FLASH ENABLED Yellow Output from BCSR

PCMCIA ENABLED Yellow Output from BCSR

EIA232 PORT 1 ENABLED Yellow Output from BCSR

INFRA-RED ENABLED Yellow Output from BCSR

ETHERNET ENABLED Yellow 10Base-T, output from BCSR

EIA232 PORT 2 ENABLED Yellow Output from BCSR

100Base-T—1 Yellow Fast Ethernet 1, from control PLD

100Base-T—2 Yellow Fast Ethernet 2, from control PLD

USB ENABLED Yellow Output from BCSR

SW4

ON1

2

3

4

EXTOLI0 driven to ’0’




EXTOLI0 pulled to ’1’






Memory Map

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3.3 Memory MapAll accesses to MPC885ADS’s memory slaves are controlled by the MPC885 memorycontroller. Therefore, the memory map is re-programmable to the user’s desire. After a hardreset is performed by the debug station, the debugger checks for the existence, size, delay,and type of SDRAM and FLASH memory SIMMs mounted onboard and initializes thechip selects accordingly. The SDRAM and FLASH memory respond to all types ofmemory access, that is, user/supervisory, program/data, and DMA.

The MPC885ADS memory map uses the SDRAM and FLASH memory as shown inTable 3-2.

SPARE 1 Yellow Connected to test point for wire-mod





TxLED (ATM25) Green From ATM25 PHY

RxLED (ATM25) Green From ATM25 PHY

EPP Green Output from host interface PLD

SERIAL Green Output from host interface PLD

LINK (10Base-T) Yellow 10Base-T link established

TX/RX (10Base-T) Green 10Base-T data traffic

FDX (10Base-T) Red 10Base-T full duplex mode

LINK (100Base-T-1) Yellow Link established for 100Base-T-1

TX/RX (100Base-T-1) Green Data traffic for 100Base-T-1

FDX (100Base-T-1) Red Full-duplex mode for 100Base-T-1

100Mbps (100Base-T-1) Green Speed for 100Base-T-1

LINK (100BBase-T-2) Yellow Link established for 100Base-T-2

TX/RX (100BBase-T-2) Green Data traffic for 100Base-T-2

FDX (100BBase-T-2) Red Full-duplex mode for 100Base-T-2

100Mbps (100BBase-T-2) Green Speed for 100Base-T-2

USB Power Green Power supplied to USB-A connector

Table 3-1. MPC885ADS LEDs (continued)

LED Name Color Function/Source



Memory Map

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Table 3-2. Memory Map in MP885ADS

ADDESS RANGE Memory TypePort Size

00000000–007FFFFF (8M) SDRAM — CS4 32

02000000–020FFFFF (1M)

02000000–020000FF02000100–020001FF02000200–020002FF02000300–020003FF02000400–020004FF

Communication ports—CS5

ATM25ATM155

T1/E1 framer,BCSR5, control register

Reserved

02100000–02107FFF (32K)

02100000–02107FE302100004–02107FE702100008–02107FEB0210000C–02107FEF02100010–02107FF3

BCSR[0–4] 1—CS1

BCSR0BCSR1BCSR2BCSR3BCSR4

1 The device appears repeatedly in multiples of its size. That is, BCSR0 appears at memory locations 2100000, 2100020, 2100040..., while BCSR1 appears at 2100004, 2100024, 2100044, and so on.

32 2

2 Only the upper 16 bits (D0–D15) are used.

02108000–021FFFFF Empty space

02200000–02203FFF MPC885 internal MAP 3

3 Refer to the MPC885 PowerQUICC Family Reference Manual for a complete description of the MPC885 internal memory map.

32

02204000–0221FFFF Empty space

02220000–02227FFF Security engine (SEC) 64

02228000–027FFFFF Empty space

02800000–029FFFFF (2M)Flash SIMM—CS0

32

02A00000–02BFFFFF (2M)

02C00000–02FFFFFF (4M)

03000000–FFFFFFFF Empty space



MPC885 Registers Programming

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3.4 MPC885 Registers Programming The MPC885 provides the following functions on the MPC885ADS:

• SDRAM controller

• Chip-select generator

• UART for terminal or host computer connection

• Ethernet controller

• Infrared port controller

• General-purpose I/O signals

• ATM controller

• T1/E1 (TDM) controller

• Fast Ethernet controller

The internal registers of the MPC885 must be programmed after a hard reset as describedin Table 3-3. The addresses and programming values are in hexadecimal base.

For a better understanding of the following initialization, refer to the MPC885PowerQUICC Family Reference Manual for more information.

3.4.1 Memory Controller Registers Programming

The memory controller on the MPC885ADS is initialized to 50-MHz operation. Theregister programming is based on a 50-MHz timing calculation, except for refresh timer,which is initialized to 16.67 MHz. The reason for initializing the ADS to 50 MHz is toallow proper (although not efficient) ADS operation through all available ADS clockfrequencies.

Table 3-3. SIU Register Programming

Register Init Value (hex) Description

SIUMCR 01010440 Internal arbitration, external master arbitration priority - 0, external arbitration priority - 0, PCMCIA channel II pins - PCMCIA, debug port on JTAG port pins, FRZ/IRQ6~ - FRZ, debug register - locked, no parity for non-CS regions, DP(0:3)/IRQ(3:6)~ pins - DP(0:3), reservation disabled, SPKROUT - Three-stated, BS_A(0:3)~ and WE(0:3)~ are driven just on their dedicated pins, GPL_B5~ enabled, GPL_A/B(2:3)~ function as GPLs.

SYPCR FFFFFF88 Software watchdog timer count (FFFF), bus-monitor timing (FF), bus-monitor - enabled, S/W watch-dog - freeze, S/W watch-dog - disabled, S/W watch-dog (if enabled) causes NMI, S/W (if enabled) not prescaler.

TBSCR 00C2 No interrupt level, reference match indications cleared, interrupts disabled, no freeze, timebase disabled

PISCR 0082 No level for interrupt request, periodic interrupt disabled, clear status, interrupt disabled, FREEZE, periodic timer disabled




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WARNINGDue to availability problems with a few of the supportedmemory components, the initializations below were not testedwith all parts. Therefore, the below initializations are liable tochange throughout the testing period.

3.4.2 Chip Selects and Memory Mapping

The MPC885ADS uses the processor’s memory controller to provide chip selects for thevarious devices on the board. The ADS uses the following chip select assignments.

• CS0—Flash memory

• CS1—BCSR registers 0 to 4

• CS2—Reserved

• CS3—Reserved

• CS4—SDRAM

• CS5—CPM PHYs such as ATM25, ATM155, and T1 and BCSR register 5

• CS6—Unused, provided to expansion interface

• CS7—Unused, provided to expansion interface

Table 3-4. Memory Controller Initialization For 50 MHz Example

Register Device TypeInit Value

(hex)Description

BR0 All Flash SIMMs supported

02800001 Base at 2800000, 32-bit port size, no parity, GPCM

OR0 MCM29F020-90 FFE00D34 2-Mbyte block size, all types access, CS early negate, 6 wait state, timing relax

MCM29F040-90SM732A1000A-9

FFC00D34 4-Mbyte block size, all types access, CS early negate, 6 wait state, timing relax

MCM29F080-90SM732A2000-9

FF800D34 8-Mbyte block size, all types access, CS early negate, 6 wait state, timing relax

MCM29F020-12 FFE00D44 2-Mbyte block size, all types access, CS early negate, 8 wait state, timing relax

MCM29F040-12SM732A1000A-12

FFC00D44 4-Mbyte block size, all types access, CS early negate, 8 wait state, timing relax

MCM29F080-12SM732A2000-12

FF800D44 8-Mbyte block size, all types access, CS early negate, 8 wait state, timing relax

BR1 BCSR 02100001 Base at 2100000, 32-bit port size, no parity, GPCM

OR1 FFFF8110 32-Kbyte block size, all types access, CS early negate, 1 wait state




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BR4 48LC2M32B2 SDRAM 0x000000C1 Base at 0x0, on UPM B

OR4 0xFF800800 8-Mbyte block size, all types access, initial address multiplexing according to AMB

BR5 Comm peripheral 0x02000401

OR5 Comm peripheral 0xFFFF89A6

MBMR 48LC2M32B2 SDRAM D0802114 1

80802114 2Refresh clock divided by D0 or 80, periodic timer enabled, type 0 address multiplexing scheme, 1 cycle disable timer, GPL4enabled, 1 loop read, 1 loop write, 4-beat refresh burst

1 For 50 MHz BRGCLK2 For 32MHz BRGCLK.

Table 3-5. UPMB Initialization for on-board SDRAM up to 66 MHz

Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception

Offset In UPM 0 8 18 20 30 3C

Contents @ offset +

0 1F07FC04 1F07FC04 1F27FC04 1F07FC04 1FF5FC84 7FFFFC07

1 EEAEFC04 EEAEFC04 EEAEBC00 EEAEBC00 FFFFFC04 X

2 11ADFC04 10ADFC04 01B93C04 10AD7C00 FFFFFC04 X

3 EEBBBC00 F0AFFC00 1FF77C47 F0AFFC00 FFFFFC04 X

4 1FF77C47 F0AFFC00 X F0AFFC00 FFFFFC84

5 1FF77C35 F1AFFC00 X E1BBBC04 FFFFFC07

6 EFEABC34 EFBBBC00 X 1FF77C47 X

7 1FB57C35 1FF77C47 X X X

8 X X X

9 X X X

A X X X

B X X X

C X X

D X X

E X X

F X X

Table 3-4. Memory Controller Initialization For 50 MHz Example (continued)

Register Device TypeInit Value

(hex)Description




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Chapter 4 Functional DescriptionIn this chapter, the various modules that comprise the MPC885ADS are described in detail.

4.1 Reset and Reset ConfigurationSeveral reset sources exist on the ADS.

• Regular power-on reset

• Manual soft reset

• Manual hard reset

• MPC885 internal sources (see the MPC885 PowerQUICC Family Reference Manual)

4.1.1 Regular Power-On Reset

Regular power-on reset operates using the DALLAS DS1818 device. The reference voltageof this device is the MAIN VDDH bus of the MPC885. However, while the reset line isasserted, the HRESET line is asserted to the MPC885.

When HRESET is asserted to the MPC885, the hard-reset configuration is made availableto the MPC885 through BCSR0. See Section 4.1.5.2, “Hard-Reset Configuration,” andTable 4-7.

4.1.2 Manual Soft Reset

To support application development that is not around the debug port and residentdebuggers, a soft-reset push button is provided (SW5). Depressing the button asserts theSRESET pin of the MPC885, generating a soft-reset sequence.

When the SRESET line is asserted to the MPC885, the soft-reset configuration is madeavailable to the MPC88, by the debug-port controller. See Section 4.1.5.3, “Soft-ResetConfiguration.”

MOTOROLA Chapter 4. Functional Description 4-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE


Reset and Reset Configuration

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4.1.3 Manual Hard Reset

To support application development not close to the debug port, a hard-reset push button isprovided1. When the soft-reset push button (SW5) is depressed in conjunction with theabort push button (SW6), the HRESET line is asserted, generating a hard-reset sequence.The button sharing is for economical and saves board space and does not affectfunctionality in any way.

4.1.4 MPC885 Internal Sources

Since the HRESET and SRESET lines of the MPC885 are open drain, and the on-boardreset logic drives these lines with open-drain gates, correct operation of the internal resetsources of the MPC885 is facilitated. As a rule, an internal reset source asserts HRESETand/or SRESET for a minimum of 512 system clocks. It is beyond the scope of thisdocument to describe these sources; however, debug-port soft reset and hard reset, whichare part of the development system and therefore mentioned, are regarded as such.

4.1.5 Reset Configuration

During reset, the MPC885 device samples the state of some external pins to determine eachpin’s operation modes and pin configuration. Three kinds of reset levels are available in theMPC885, and each level has its own configuration sampled. The following are the threetypes of reset levels:

• Power-on reset configuration

• Hard-reset configuration

• Soft-reset configuration

4.1.5.1 Power-On Reset Configuration

Just before PORESET is negated by the external logic, the power-on reset configuration,which includes the MODCK(1:2) pins, is sampled. These pins determine the clockoperation mode of the MPC885. Four clock modes are supported on the MPC885ADS.They are shown in Table 4-1, which shows the power-on reset DPLL configuration.

1Not a dedicated button.



Reset and Reset Configuration

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The MPC885ADS provides two methods for clocking the processor. First, a crystal may beconnected between the XTAL and EXTAL pins per the MPC885 PowerQUICC FamilyReference Manual. Note that the value of this crystal must be 10 MHz where previousMPC8xx processors allowed values as low as 32 KHz. Second, a 10-MHz oscillator maybe connected to EXTCLK, again, per the MPC885 PowerQUICC Family ReferenceManual. The ADS also provides a connector to an external clock source through theEXTCLK pin. The clock source is programmed through the dip switches connected toMODCK1 and MODCK2.

4.1.5.2 Hard-Reset Configuration

During the hard-reset sequence, when the RSTCONF pin is asserted, the MPC885 data busstate is sampled to acquire the MPC885’s hard-reset configuration. The reset configurationword is driven by the BCSR0 register, the defaults of which are set during power-on reset.The BCSR0 drives half of the configuration word, that is, data bits D(0–15), in which thereserved bits are designated RSRVxx. If the hard-reset configuration is to be changed1,BCSR0 may be written with new values, which become valid after HARD reset is appliedto the MPC885.

On the ADS, the RSTCONF line is always driven during hard reset, that is, no use ispossible with the MPC885’s internal hard-reset configuration defaults.

4.1.5.3 Soft-Reset Configuration

The rising edge of SRESET is used to configure the development port. Before the negationof SRESET, DSCK2 is sampled to determine whether debug mode is enabled or disabled.After SRESET is negated, if debug mode was enabled, DSCK is sampled again for debugmode entry or non entry.

Table 4-1. Power-On Reset DPLL Configuration

MODCK[1:2] Default at Power-On ResetOSCLK (DPLL and

Interface input)General System Frequency (GCLK2)

MFI[12:15] PDF[27:30]

00 8 0000 OSCM freq 40 MHz (for OSCLK freq = 10 MHz)

01 15 0000 OSCM freq 75 MHz (for OSCLK freq = 10 MHz)

10 6 0010 EXTCLK freq 1:1 mode (The allowable frequencies on EXTCLK are 45 to 66 MHz)

11 15 0000 EXTCLK freq 75 MHz (for EXTCLK freq = 10 MHz)

Note: Note: S = 1, MFN = 0, MFD = 1 for all of the reset configurations.

Note: The general system clock[GCLK2] is jdbck divided by 2.Note: divout1 is jdbck divided by 2.

1With respect the ADS’s power-on defaults.2DSCK is configured at hard reset to reside on the JTAG port.



Local Interrupter

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DSDI is used to determine the debug port clock mode and is sampled after the negation ofSRESET.

The soft reset configuration is provided by the debug-port controller. An option is given toenter debug mode directly or only after an exception.

4.2 Local InterrupterThe only external interrupt that is applied to the MPC885 through its interrupt controller isthe abort (NMI), which is generated by a push button. When this button is depressed, theNMI input to the MPC885 is asserted. The purpose of this type of interrupt is to support theuse of resident debuggers if any are made available to the ADS. All other interrupts to theMPC885 are generated internally by the MPC885’s peripherals and by the debug port.

To support external (off-board) generation of an NMI, the IRQ0 line, which is routed as anNMI input, is driven by an open-drain gate. This allows for external hardware to also drivethis line. If an external hardware indeed does so, it is compulsory that IRQ0 is driven by anopen-drain (or open-collector) gate.

4.3 BufferingSince the ADS is meant to serve also as a hardware development platform, it is necessaryto buffer the MPC885 from the local bus so that the MPC885’s capacitive drive capabilityis not wasted internally and remains available for the user’s off-board applications throughthe expansion connectors.

Buffers are provided for address and strobe lines while transceivers are provided for data.The data transceivers open only if there is an access to a valid1, 2 board address or duringhard-reset configuration3. This way, data conflicts are avoided in case an off-board memoryis read, provided that it is not mapped to an address valid on board. It is the users’responsibility to avoid such errors.

4.4 Chip-Select GeneratorThe memory controller of the MPC885 is used as a chip-select generator to accesson-board4 memories, thus saving the board’s area, reducing cost and power consumption,and increasing flexibility. To enhance off-board application development, memory modules(including the BCSRx) may be disabled through BCSR15 in favor of an external memoryconnected through the expansion connectors. This way, a CS line may be used off-boardthrough the expansion connectors while its associated local memory is disabled. 1An address which covered in a chip-select region.2Except for SDRAM, which is unbuffered.3To allow a configuration word stored in Flash memory to become active.4Peripherals and off-board.5After the BCSR is removed from the local memory map, there is no way to access it but to reapply power to the ADS.



Flash Memory SIMM

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When a CS region is disabled through BCSR1, the local data transceivers do not openduring access to that region, avoiding possible1 contention over data lines.

The MPC885’s chip-selects assignment to the various memories and registers on the ADSare as shown in Table 4-2.

4.5 Flash Memory SIMMThe MPC885 ADS is provided with 8 Mbytes of 70-ns Flash memory SIMM.The FlashSIMM resides on an 80-pin SIMM socket. To minimize use of the MPC885’s chip-selectlines, only one chip-select line (CS0) is used to select the flash as a whole, whiledistributing chip-select lines among the internal banks is done through on-boardprogrammable logic, according to the presence-detect lines of the Flash SIMM inserted tothe ADS. Control over the Flash is achieved by using the GPCM and a dedicated CS0region, controlling the whole bank. During hard-reset initializations, the CPLD reads theFlash presence-detect lines through BCSR2 and decides how to program the BR0 and OR0registers, within which the size and the delay of the region are determined. The Flashmodule may be disabled or enabled at any time by writing a 1 or 0 to the FLASH_EN bitin BCSR1, respectively.

4.6 Synchronous DRAMTo enhance performance, especially in higher operation frequencies, the MPC885ADSprovides 8 Mbytes of SDRAM on the board. This memory is unbuffered from the bus tomaximize performance. The configuration of the memory is 4 × 512K × 32. The ADSsupports an optional board loading of 16 Mbytes. The SDRAM is enabled/disabled throughthe SDRAMEN bit in the BCSR1 register (see Table 4-8). The timing of the SDRAM iscontrolled by UPMB.

To enhance performance, the SDRAM is unbuffered from the MPC885, saving the delayassociated with address and data buffers. Since only one memory chip is involved, it does

1During read cycles.

Table 4-2. MPC885ADS Chip Select Assignment

Chip Select: Assignment

CS0 Flash memory

CS1 BCSR

CS(2–3) Unused, user available

CS4 SDRAM

CS5 Communication peripherals

CS(6–7) Unused, user available



Synchronous DRAM

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not adversely affect overall system performance. The SDRAM does not reside on a SIMMbut is soldered directly to the ADS printed circuit board (PCB). The SDRAM may beenabled or disabled at any time by writing a ‘1’ or a ‘0’ to the SDRAMEN bit in BCSR1.See Table 4-8.

The SDRAM’s timing is controlled by UPMB through its assigned CS (see Table 4-2) line.Unlike a regular DRAM, the synchronous DRAM has a CS input in addition to the RASand CAS signals. The SDRAM connection scheme is shown in Figure 4-1.

This SDRAM has 11 rows and 8 columns. The suggested interface between an MPC885and an SDRAM is illustrated in Figure 4-1, and it is clear that this is a glueless interface.For a 32-bit bus, one 32-bit SDRAM device is connected. The control is driven by theUPMB on the MPC885, so the CS on the SDRAM is interfaced to CS4 on the MPC885.Any other chip-select line excluding CS0 will do. The DQM signals of the used SDRAMdevices select byte lanes and are connected to the appropriate byte strobe (BS0:3) signalson the MPC885. A10 SD is connected to GPL0, since this has the functionality to eitherdrive an address on the line, or a defined level. This is required as A10 SD acts as both anaddress line and a control line. RAS and CAS are generated by GPL1 and GPL2,respectively. The WE is generated by GPL3. CLK is driven by the MPC885’s CLKOUTsignal which is a reference point with respect to the MPC885 memory controller. Since theSDRAM used in the example has 2048 rows and 256 columns, 11 row address lines and 8column address lines should be used. The BS lines are connected to line A10 and A9 of theMPC885 and are used as a high-order address bit. Remember that the MPC885 addresslines have a different numbering scheme than the SDRAM address lines when reading theaddress line mapping for 32 bits in Table 4-3.

Through the UPM register AMx =0b000, the address bits A11:21 MPC885 are mapped tolines A19:29 MPC885 as row addresses. As we start with line A21 MPC885 to connect toA8 SD, A20 MPC885 to A9 SD we need to provide the left over row address A10 SD notby using line A19 MPC885 (which would show A10 MPC885 as multiplexed row address),but by using GPL0 as described above. In the UPM Register MBMR, we program GPL0 toshow A10 MPC885 to complete row addressing. As in this case there are four banks in theSDRAM device. Sometimes, a single 32-bit SDRAM bank is not enough memory for anapplication. Connecting multiple 32-bit SDRAM-based banks to the MPC885 is fairlystraightforward. Extending the interface described above is easy.

Table 4-3. SDRAM ADD Pin Refer to MPC885 Pins

MPC885 SDRAM

A9, A10 BS1, BS0

A11:A21 11 row

A22:A29 8 column



Synchronous DRAM

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Above, the most significant row address bit is connected to BS SD.A10 MPC885 and isused due to the address size of 19 bits (8/11 address multiplex!) covered by the exampleSDRAM device. For an SDRAM device with two BS lines, BS0 SD and BS1 SD, wesimply use the next address bit, A10, A9 MPC885, with more significance to keep thememory mapping linear. In essence, we use address lines for the binary encoding of thebank selection.

NOTEIf the user wants to change the SDRAM to a larger one, 16MA11 of the SDRAM is connected to A10. This connectionalready exists on the board layout, so the user has to connectBS0, BS1 to MPC885 and add A9 and A8 by moving resistorson board called RJ20 and RJ21 from pins 1, 2 to 2, 3. If the userwants to change to 16 Mb SDRAM, A11 of the SDRAM isconnected to A10.

Table 4-4. SDRAM Connected to MPC885

MPC885 Output ADD

SDRAM ADDMPC885 Internal

Column ADD

MPC885 Internal Row

ADD

A29 A0 A29 A21

A28 A1 A28 A20

A27 A2 A27 A19

A26 A3 A26 A18

A25 A4 A25 A17

A24 A5 A24 A16

A23 A6 A23 A15

A22 A7 A22 A14

A21 A8 A13

A20 A9 A12

GPL0 A10 (AP) A11

A10 Note1 N.C. (A11)

A10 / A9 Note1 BS0 A10

A9 / A8 Note 1 BS1 A9



Synchronous DRAM

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Table 4-5 shows the estimated SDRAM performance figures.

Figure 4-1 shows the SDRAM connection scheme.

Figure 4-1. SDRAM Connection Scheme

Table 4-5. Estimated SDRAM Performance Figures

Number of System Clock

Cycles

System Clock Frequency [MHz]

50

Single read 5

Single write 3+1 1

1 One additional cycle for RAS precharge.

Burst read 5,1,1,1

Burst write 3,1,1,1 + 11

Refresh 21 2

2 4-beat refresh burst, not including arbitration overhead.

CS

RAS

CAS

WE

A10

BS(1:0)

A(9:0)

CKE

CLK

DQM3

DQM2

DQ(31:0)

CS4

GPL1

GPL2

GPL3

GPL0

SDRAMEN

SYSCLK

D(0:31)

BS0_B

BS1_B

A(20:29)

A(9,10)

(A11)

DQM1

DQM0

BS2_B

BS3_B



Synchronous DRAM

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4.6.1 SDRAM Programming

After power-up, the SDRAM needs to be initialized to establish its mode of operation. TheSDRAM is programmed by issuing a mode register set command. During execution of thiscommand, data is passed to the mode register through the SDRAM’s address lines. Thiscommand is fully supported by the UPM by means of a dedicated memory address register(MAR) and the UPM command run option.

Mode register programming values are shown in Table 4-6. In order to operate the SDRAMat a higher speed than 50 MHz, the user should read the application note MP8xx SDRAMInterface (AN2066) and use the MPC860 UPM Programming Tool - UPM860(MPC860COD09) and the UPM860 Manual for MPC860 UPM Programming Tool(MPC860COD10)on the Freescale Semiconductor website.

4.6.1.1 SDRAM Initializing Procedure

After power-up, the SDRAM needs to be initialized in a certain manner, as describedbelow:

1. Set MAR with the proper value (0x88 for 50 MHz)

2. Write MCR with 0x80808105 to run the MRS command programmed in locations 5–8 of UPMB.

3. Change MBMR’s TLFB field to 8 to constitute 8-beat refresh bursts.

4. Write MCR with 0x80808830 to run the refresh sequence (8 refresh cycles are performed now).

5. Restore MBMR’s TLFB field to 4 to provide 4-beat refresh bursts for normal operation.

6. Write the MCR with 0x80808106. The SDRAM is initialized and ready for operation.

Table 4-6. SDRAM’s Mode Register Programming

Value @ Frequency

SDRAM Option 50 MHz

Burst length 4

Burst type Sequential

CAS latency 2

Write burst length Burst



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4.6.2 SDRAM Refresh

The SDRAM is refreshed using its auto-refresh mode, that is, using UMPB’s periodic timer.A burst of four auto-refresh commands is issued to the SDRAM every 62.4 µs, so that all2048 SDRAM rows are refreshed within the specified 32.8 msec.

4.7 Protocol Selection

4.7.1 ATM25

The ATM25 circuit is connected to the processor through the 8-bit, UTOPIA level 2interface. The PHY device is an IDT 77V107, which provides the transmissionconvergence (TC) and the physical media-dependent (PMD) sublayers. The PHY supports25.6 Mbps and 51.2 Mbps operation. The PHY is configured through a multiplexed addressand data bus. Note that the PHY supports only three UTOPIA addresses, selected by theUTOPIA address 0 and 1 bus signals. The logical address ‘11’ cannot be used since theUTOPIA bus generates the address ‘1F’ between valid addresses.

This PHY supports UTOPIA bus speeds of up to 50 MHz. The MPC885’s SCCR registeris used to program the UTOPIA bus speed. Note that when using other ATM PHY’s, eitheron-board or externally, the UTOPIA bus speed must satisfy all PHY devices. Note also thatholding this device in reset prevents the proper operation of the UTOPIA bus.Programming this PHY to an address that the processor has been programmed to ignorecauses this PHY to be silent on the UTOPIA bus.

4.7.1.1 Physical Interface

The analog transmit and receive pairs are provided through a standard RJ45 connector andassociated pin assignments.

4.7.1.2 Board Configuration (Strap/Switch)

Dip switch S2, switch 4, must be configured for ATM operation.

4.7.2 ATM155

The ATM155 circuit is connected to the processor through the 8-bit, UTOPIA level 2interface. The PHY device is a NEC UPD98404, which provides the TC and PMDsublayers. The PHY supports 155-Mbps SONET STS-3c/SDH STM-1 operation.Configuration of the PHY is done through the address and data buses. Note that the ADSprovides UTOPIA address 0 and 1 interface signals to the PHY device. Address signals 2,3, and 4 are forced to a ‘0’. The MPC885 should be programmed to internally generate boththe transmit and receive clocks.



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This PHY supports UTOPIA bus speeds of 20–40 MHz. The MPC885’s SCCR register isused to program the UTOPIA bus speed. Note that when using other ATM PHYs, eitheron-board or externally, the UTOPIA bus speed must satisfy all devices. Note also thatholding this device in reset prevents the proper operation of the UTOPIA bus.Programming this PHY to an address that the MPC885 has been programmed to ignore willcause this PHY to be silent on the UTOPIA bus.


The ATM155 connection to the outside world is through an optical transceiver HFBR-5805from Agilent. The connector is a duplex, "SC" receptacle.


Dip switch S2, switch 4, must be configured for ATM operation.

4.7.3 10Base-T Ethernet Operation

The 10Base-T PHY device is connected to the processor’s SCC3 and utilizes GPSIsignaling. The PHY is a Davicom 9161 device. The PHY address is selected byprogramming resistors and is loaded from the factory as device 0x00010. A 25-MHzoscillator provides timing for the device. Configuration of the PHY is provided throughMDIO/MDC signaling.


The analog transmit and receive pairs are provided through a standard RJ45 connector andassociated 10Base-T pin assignments.


Dip switch S2, switch 3, must be configured for 10Base-T operation. This necessarilydisables the operation of the T1/E1 interface.

4.7.4 100Base-T Ethernet Operation

The MPC885 provides two each 100Base-T PHY devices. Both devices are the Davicom9161 and can be configured individually to support either the MII or RMII interface to theprocessor. The boards are loaded from the factory to support the MII interface. To configurethe board for RMII operation, the user must reconfigure the option select resistors tosupport 50-MHz clocking.

The PHY addresses are selected by programming resistors and are loaded from the factory.The PHY device that corresponds to Fast Ethernet 1 is located at address 0x00000. Fast



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Ethernet 2 is at address 0x00001. Configuration of the PHYs is provided throughMDIO/MDC signaling.


The 100BaseT connection to the outside world is through a RJ45 8-pin connector.


Dip switch S2, switches 2 and 3, must be configured for Fast Ethernet 2 to operate. Thisdisables the operation of the 10Base-T and EIA232-2 interfaces.

4.7.5 T1/E1 Framer

The ADS provides a T1/E1 interface and framer through the Dallas Semiconductor DS2155single-chip transceiver. The transceiver is connected through a TDM interface to TDMA ofthe processor.


The T1/E1 connection to the outside world is through a RJ45 8 pin connector.

4.7.5.2 Board Configuration (strap/switch)

Dip-Switch S2, switch 3 must be configured for T1/E1 operation and disables 10Base-Toperation.

4.7.6 EIA232 Interfaces

Two EIA232 interfaces are provided on the ADS and utilize SMC1 and SMC2 of theprocessor. A Maxim 3241 single-chip transceiver is used for each interface and can beindividually enabled/disabled. The Maxim parts generate the necessary signal levels tocomply with EIA232 specification. The Maxim parts support 250 Kbps and 15 KV of ESDprotection.


The two separate EIA232 circuit connections to the outside world are through industrystandard DB9 connectors.

In the list below, the directions ‘I/O’ are relative to the ADS board, that is, ‘I’ means inputto the ADS).

• CD (O)—Data carrier detect. This line is always asserted by the ADS.

• TX (O)—Transmit data



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• RX (I)—Receive data

• DTR (I)—Data terminal ready. This signal may be used by the software on the ADS to detect if a terminal is connected to the ADS board.

• DSR (O)—Data set ready. This line is always asserted by the ADS.

• RTS (I)—Request to send. This line is not connected in the ADS.

• CTS (O)—Clear to send. This line is always asserted by the ADS.


Dip switch S2, switch 1, must be configured for EIA232-1 operation, and switch 2 must beconfigured for EIA232-2 operation.

4.7.7 IrDA

The IrDA circuit is connected to SCC2 and provides an optical transmitter and receiversupporting IrDA. SCC2 provides IrDA transmission speeds up to 115.2 Kbps. Thetransceiver is the TFDU6102 manufactured by Vishay.

4.7.8 USB 2.0 Full-/Low-Speed Interface

The MPC885 ADS provides both series A and series B interface compliant with the USB2.0–specification for full/low speeds, and supporting both host and device configurations.The USB transceiver is a Phillips PDIUSBP11A and supports the full-speed, 12-Mbps andlow-speed, 1.5-Mbps data rates. A USB clock is provided by a separate 48 MHz oscillatorconnected to the MPC885’s clock 2.

NOTEWhen generating SOF packets using the MPC885 USBcontroller, the user should know that the PC15 pin (DREQ0) isconnected to the ATM_RXCLAV signal, which may go low,thus affecting the external interrupt signal at DREQ0. Toresolve this conflict, the user should set switch #4 in S2 to theON position. Setting the switch will isolate PC15 fromATM_RXCLAV, and the external interrupt signal will not beaffected. In addition, when using TOUT1 as the externalinterrupt signal source, the user should not use PA6 as TOUT1because PA6 is permanently connected to the USB controllerclock signal. Instead, the user should use either PC12 or PE21as TOUT1.



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The MPC885 ADS provides a series A and a series B connector interface. Writing to anADS BCSR register provides a 5 V DC to pin 1 of the series A connector.


None required.

4.7.9 PCMCIA Interface

The PCMCIA interface is a single slot, PCMCIA 2.1–compliant interface connected toMPC885’s ‘slot A’. This interface supports both 5- and 3.3-V PC cards. Note that theapplication software should read the status of the PCMCIA voltage-selection andcard-detect signals to determine which supply voltage should be applied to the interface.Many of the address, data and control signals from the MPC885 are buffered. A PCMCIApower controller is provided to support ‘hot insertion’ of PC cards. Audio support isprovided by a small speaker connected to the processor.


The ADS provides a single PC card slot compatible with both 5- and 3.3-V cards.

Figure 4-2 shows the PCMCIA port configuration.



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Figure 4-2. PCMCIA Port Configuration

5

D[8:15]

D[0:7]

CE2_A(B)

CE1_A(B)

ALE_A(B)

Data_A[7:0]

Data_A[15:8]

R/W

RDY/BSY_A(B), BVD(1:2)_A(B)

WE/PGM

Address_A[25:0]

CE1

CE2

12V

Power Logic

A[6:31]

8

8

1

1

26

1

11

PCCVCC

PCCVPP

5V

1

WE/PGM

REG 1REG

OE1

OE

IORD,IOWR 2IORD,IOWR

RESET_A(B)

2

SPKROUT

1

1

26

3

1

1

1

2

2

8

8

1

1

3

1

or equiv.

WAIT_A(B), IOIS16_A(B)

POE_A(B)1

1

4

Bufferwith OE

Transparent Latch with OE

CD(1:2)_A(B),VS(1:2)_A(B)4

VDD

VDD

From BCSR

RESET 1

VDD

VDD

PCMCIA_EN

MPC885

PCMCIA POWER CONTROL

PCMCIA SOCKET

OE

From BCSR

OE

LTC1315

LPF



BCSR—Board Control and Status Register

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Pin multiplexing of the processor requires that the PCMCIA signals be switched with thesignals that support the UTOPIA bus. Thus dip switch S2, switch 4, must be configuredcorrectly.

4.7.9.3 PCMCIA Power Control

To support hot-insertion1 the socket’s power is controlled through a dedicated PCMCIApower controller, the LTC1315 made by Linear Technology. This device, controlled byBCSR1, switches 12-V VPP for card programming and controls the gates of externalMOSFET transistors, through which the PC card VCC is switched.

When a card is inserted while the channel is enabled through BCSR1, that is, both of theCD(1:2) (card detect) lines are asserted (low), the status of the voltage select lines VS(1:2)should be read to determine the PC card’s operation voltage level according to which,PCCVCC(0:1) bits in BCSR1 should be set, to drive the correct VCC (5 V) to the PC card.

When a card is being removed from the socket while the channel is enabled throughBCSR1, the MPC885 may sense the negation of CD1 and CD2 and cut the power supplyto the card.

WARNINGAny application S/W handling the PCMCIA channel mustcheck the voltage-sense lines before power is applied to the PCcard. Otherwise, if 5 V of power is applied to a 3.3-V–onlycard, the PC card will suffer permanent damage.

4.7.10 I2C Interface

The ADS provides access to the processor’s I2C interface through the 3 pin header labeledJ7.

4.8 BCSR—Board Control and Status RegisterMost of the hardware options on the MPC885ADS are controlled or monitored by theBCSR, which is a 32-bit2 read/write register file. The BCSR is accessed through theMPC885’s CS1 region and in fact includes six registers, BCSR0–BCSR5. Since theminimum block size for a CS region is 32 Kbytes, BCSR0—BCSR4 are multiplyduplicated within that region to facilitate software reuse.

1Card insertion when the ADS is powered.2In fact only the upper 16 bits,D[0–15], are used, but the BCSR is mapped as a 32-bit register and should be accessed

as such.




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MPC885-specific additions to the MPC866ADS BCSR registers include:

• USB low-speed selection in BCSR4, bit 5

• USB full-speed selection in BCSR4, bit 13

• USB enable in BCSR4, bit 14

• Expansion port OE in BCSR4, bit 15

• Reset MII-2 in BCSR5, bit 5

• Enable MII-2 RX in BCSR5, bit 6

4.8.1 BCSR Disable Protection Logic

The BCSR itself may be disabled in favor of off-board logic. To avoid accidental disable ofthe BCSR, an event from which only power re-appliance recovers, protection logic isprovided.

The BCSR_EN bit resides on BCSR1. This bit wakes-up active (low) during power-up andmay not be changed1 unless the BCSR_EN_PROTECT bit in BCSR3 was previouslywritten with ‘1’.

After the BCSR_EN_PROTECT is written with ‘1’ to unprotect the BCSR_EN bit there isonly one shot at disabling the BCSR, since, immediately after any write to BCSR1,BCSR_EN_PROTECT is re-activated and BCSR_EN is re-protected and the disablingprocedure has to be repeated if desired.

4.8.2 BCSR0—Hard Reset Configuration Register

BCSR0 is located at offset 0 on BCSR space. It may be read or written at any time2. Duringhard reset, data contained in BCSR0 is driven on the data bus to provide the hard-resetconfiguration for the MPC885. If the FLASH_CFG_EN bit in BCSR1 is not active, BCSR0may be written at any time to change the hard-reset configuration of the MPC885. The newvalues become valid when the next hard-reset is issued to the MPC885 regardless of thehard-reset source. The description of BCSR0 bits is shown in Table 4-7.

1It may be written but will not be influenced.2Provided that BCSR is not disabled.




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Table 4-7. BCSR0 Description

Bits Mnemonic FUNCTIONPON DEF.

Attr

0 ERB External arbitrationDuring hard-reset:0 Arbitration is performed internally.1 Arbitration is performed externally.

— R,W

1 IP Interrupt prefixDuring hard reset:0 Interrupt prefix set to 0xFFF000001 Interrupt prefix set to 0

— R,W

2 Reserved — —

3 BDIS Boot disableDuring hard reset:0 CS0 region is enabled for boot.1 CS0 region is disabled for boot.

— R,W

4–5 BPS(0:1) Boot port size. Determines the port size for CS0 at boot.00 32 bit01 8 bit10 16 bit11 Reserved

— R,W

6 Reserved — —

7–8 ISB(0:1) Initial space base. Value during hard-reset determines the initial base address of the internal MPC885 memory map. 00 0x0000000001 0x00F0000010 0xFF00000011 0xFFF00000

— R,W

9–10 DBGC(0:1) Debug pins configuration. Determines the function of the PCMCIA pins during hard-reset.00 PCMCIA operation01 Watchpoints10 Reserved11 Show-cycle attribute pins (for example, VFLSx)

— R,W

11–12 DBPC(0:1) Debug port pins configuration. Determines location of the debug port pins during hard-reset00 JTAG port pins01 Nonexistent10 Reserved11 PCMCIA pins

— R,W

13–14 EBDF(0:1) External bus division factor. Value during hard reset determines the factor upon which the CLKOUT of the MPC885 external bus, is divided with respect to its internal MPC885 clock. 00 GCLK2 divided by 101 GCLK2 divided by 210 Reserved11 Reserved

— R,W




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4.8.3 BCSR1—Board Control Register 1

The BCSR1 serves as a control register on the ADS. It is accessed at offset 4 from theBCSR base address. It may be read or written at any time1. BCSR1 fields are described inTable 4-8.

15 Reserved — —

16–31 Reserved — —

1Provided that BCSR is not disabled.


Bits Mnemonic FunctionPON DEF

Attr

0 FLASH_EN Flash enable. When this bit is active (low), the Flash memory module is enabled on the local memory map. When inactive, the Flash memory is removed from the local memory map and CS0, to which the Flash memory is connected may be used off-board through the expansion connectors.

— R,W

1 Reserved — R,W

2 ETHEN Ethernet port enable. When asserted (high) the EEST connected to SCC1 is enabled. When negated (low), the EEST is in standby mode, while all its system i/f signals are three-stated.

— R,W

3 IRDEN Infra-red port enable. When asserted (low), the infra-red transceiver, connected to SCC2 is enabled. When negated, the infra-red transceiver is put in shutdown mode. And SCC2 pins are available for off-board use through the expansion connectors.

— R,W

4 FLASH_CFG_EN

Flash configuration enable.When this bit is negated (high), it allows the hard reset config word in BCSR0 to drive the data bus during power up. When this bit is asserted (low): (A) The hard-reset configuration held in BCSR0 is NOT driven on the data bus during hard-reset and(B) Configuration data held at the 1st word of the Flash memory is driven to the data bus during hard reset. 1

— R,W

5 CNT_REG_EN_PROTECT

Control register enable protect. When this bit is active (low) the BCSR_EN bit in that register can not be written. When in-active, BCSR_EN may be written to remove the BCSR from the memory map. After any write to BCSR1 this bit becomes active again. This bit is a read-only 2 bit on that register.

— R


Bits Mnemonic FUNCTIONPON DEF.

Attr




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6 BCSR_EN BCSR enable. When this bit is active (low) the Board Control and Status Register is enabled on the local memory map. When inactive, the BCSR may not be read or written and its associated CS1 is available for off-board use through the expansion connectors. This bit may be written with ‘1’ only if CNT_REG_EN_PROTECT bit is negated (1).When the BCSR is disabled it still continues to configure the board according the last data held in it even during hard-reset.

— R,W

7 EIA232EN_1 EIA232 port 1 enable. When asserted (low) the EIA232 transceiver for port 1, is enabled. When negated, the EIA232 transceiver for port 1, is in standby mode and the relevant MPC885 communication port pins are available for off-board use through the expansion connectors.

— R,W

8 PCCEN PC card enable. When asserted (low), the on-board PCMCIA channel is enabled, that is, address and strobe buffers are enabled to / from the card. When negated, all buffers to / from the PCMCIA channel are disabled allowing off-board use of its associated lines.

— R,W

9 PCCVCC0 PC card VCC select 0. These signal in conjunction with PCCVCC1 determine the voltage applied to the PCMCIA card’s VCC. Possible values are 0, 3.3, and 5 V.

— R,W

10–11 PCCVPP(0:1) PC card VPP. These signals determine the voltage applied to the PCMCIA card’s VPP.00 0 V01 5 V10 12 V11 High impedence

— R,W

12 Reserved — R,W

13 EIA232EN_2 EIA232 port 2 enable. When asserted (low) the EIA232 transceiver on SMC2, is enabled. When negated, the EIA232 transceiver for port 2, is in standby mode and the relevant MPC885 communication port pins are available for off-board use through the expansion connectors.

— R,W

14 SDRAMEN SDRAM enable. When this bit is active (high), the SDRAM module is enabled on the local memory map. When in-active, the SDRAM is place in low-power mode, in fact removed from the local memory map, allowing its associated CS line, to be used off-board through the expansion connectors.

— R,W

15 PCCVCC1 PC card VCC select 1. These signal in conjunction with PCCVCC0 determine the voltage applied to the PCMCIA card’s VCC.PCCVCC1, PCCVCC000 0 V01 5 V10 3.3 V11 0 V

— R,W


1 Provided that this option is supported by the MPC885 by driving address lines low and asserting CS0 during hard reset.

2 It is written in BCSR3.



Attr




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4.8.4 BCSR2—Board Control / Status Register 2

BCSR2 is a status register that is accessed at offset 8 from the BCSR base address. It is aread-only register that may be read at any time1. BCSR2’s various fields are described inTable 4-9.


BCSR3 is an additional control/status register that may be accessed at offset 0xC fromBCSR base address. BCSR3 may be read or written at any time. BCSR3 is described inTable 4-10.




Attr

0–3 FLASH_PD(4:1) Flash Presence Detect(4:1). These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket. There are additional 3 presence detect lines which encode the SIMM’s delay but appear in BCSR3. 0–4 Reserved5 4-Mbyte SIMM, Smart Modular Tech6 8-Mbyte SIMM, Motorola7 4-Mbyte SIMM, Motorola8 2-Mbyte SIMM, Motorola, Smart Modular Tech, or RPC9–F Reserved

— R

4–8 Reserved Unimplemented — —

9–12 EXTTOLI(0–3) External tools identification. These bits represent the switch settings of switch S4 and are used in legacy ADS systems for design tool identification. The switch S4 is also available for user defined purposes.0000–0111 Reserved1000–1110 User defined1111 Nonexistent

— R

13–31 Reserved — R



Attr


5 CNT_REG_EN_PROTECT

Control register enable protect. When this bit is active (low) the BCSR_EN bit in that register can not be written. When in-active, BCSR_EN may be written to remove the BCSR from the memory map. After any write to BCSR1 this bit becomes active again. This bit is a write-only bit on that register.

— W





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Note: 70 nS Flash will actually read as ‘011’ on bits 9 - 11.Note: Not all types of Flash are guaranteed to be detected correctly by the Flash presence detect lines.


The BCSR4 serves as a control register on the ADS. It is accessed at offset 10H from BCSRbase address. It may be read or written at any time1. BCSR4 fields are described inTable 4-11

NOTEUSB_LO_SPD (bit 5) and USB_FULL_SPD (bit 13), are setup at reset to both be in an off condition ‘1’. This will cause aUSB error condition. To remedy this situation, turn either bit 5or bit 13 to ‘0’ depending on what mode is desired.

9–11 FLASH_PD(7:5) Flash presence detect(7:5). These lines are connected to the Flash SIMM presence detect lines which encode the delay of Flash SIMM mounted on the Flash SIMM. There are additional four presence detect lines that encode the SIMM’s type but appear in BCSR2.0–3 Reserved000 Not supported001 150010 120011 90100–111 Not supported

—

12–31 Reserved — R




Attr

0 10BT_RST 10BaseT PHY reset. A ‘0’ resets the 10BaseT, GPSI PHY. — R,W

1–2 Reserved — R,W

3 SIGNAL_LAMP Signal lamp. When this signal is active (low), a dedicated LED illuminates. When inactive, this led is darkened. This led is used for S/W signaling to user.

— R,W

4 Reserved — R,W

5 USB_LO_SPD 1 USB low-speed mode. ‘0’ configures the driver for low speedand enables the pull-up resistor on D-.

— R,W

6 USB_VCC USB VCC. A ‘1’ supplies VCC power to the series A connector — R,W

7–12 Reserved — R,W

Table 4-10. BCSR3 Description (continued)


Attr



Debug Port Controller

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The BCSR5 serves as a control register on the ADS. It is accessed at address 0x2000300on CS5. It may be written at any time. BCSR5 fields are described in Table 4-12

4.9 Debug Port ControllerThe debug port of the MPC885ADS is implemented on-board, connected to the MPC885through the JTAG port. Since the location1 of the debug port is determined through the

13 USB_FULL_SPD1 USB full-speed mode. A ‘0’ configures the driver for full speed. — R,W

14 USB_EN USB port enable. Setting this bit to a ‘0’ enables the operation of the USB port.

— R,W

15 EXPANS_EN Expansion port enable. Setting this bit to a ‘0’ enables the expansion port data bus

— R,W


1 The board’s initial state has these bits turned off. To enable either low or full speed, the user must write a 0 to either USB_LO_SPD or USB_FULL_SPD.



Attr

0 Reserved — —

1 MII2_EN MII2 enable. A ‘0’ enables the Ethernet PHY attached to MII2. A ‘1’ disables the PHY

— R/W

2 MII2_RST MII2 reset. A ‘1’ resets the Ethernet PHY attached to MII2. — R/W

3 T1_RST Reset E1/T1 framer. Driving ‘1’ to this pin resets the FRAMER. On power-on reset, this pin drives the value of MPC885 POR signal. Write 0x10 in order to reset the framer.

— R/W

4 RESET_ATM155 Reset ATM155 PHY. Driving ‘1’ to this pin resets the PHY. On power-on reset, this pin drives the value of MPC885 POR signal. Write 0x08 in order to reset the PHY.

— R/W

5 RESET_ATM25 Reset ATM25 PHY. Driving ‘1’ to this pin resets the PHY. On power-on reset, this pin drives the value of MPC885 POR signal. Write 0x04 in order to reset the PHY.

— R/W

6 MII1_EN MII1 enable. A ‘0’ enables the Ethernet PHY attached to MII1. A ‘1’ disables the PHY

— R/W

7 MII1_RST MII1 reset. A ‘1’ resets the Ethernet PHY attached to MII1. — R/W

1In terms of MPC885 pins.

Table 4-11. BCSR4 Description (continued)


Attr




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hard-reset configuration, it is important that the relevant configuration bits (seeSection 4.1.5, “Reset Configuration”) are not changed if working with the local debug portis desired.

The MPC885’s debug port is configured at soft reset to asynchronous clock mode, that is,the debug port generates the debug clock, DSCK, which is asynchronous with the MPC885system clock.

The debug port I/F has two registers: a control/status register and a data register. Thecontrol/status register holds I/F related control/status functions, while the data registerserves as the parallel side of the transmit/receive shift register.

4.9.1 MPC885ADS As Debug Port Controller For Target System

The ADS may be used as a debug port controller for a target system, provided that the targetsystem has a 10-pin header connector matching the one on the ADS.

In this mode of operation, the on-board debug port controller is connected to the targetsystem’s debug-port connector. Since DSDO signal is driven by the MPC885, it is a mustto remove the local MPC885 from its socket to avoid contention over this line.

When the MPC885 is removed from its socket, all ADS’s modules are inaccessible, exceptfor the debug-port controller. All module-enable indications are darkened, regardless oftheir associated enable bits in the BCSR. Pull-up resistors are connected to chip-selectlines, so they do not float when the MPC885 is removed from its socket, avoiding possiblecontention over data-bus lines.

4.9.1.1 Debug Port Connection—Target System Requirements

In order for a target system to be connected to the ADS as a debug port controller, a fewmeasures need to be taken on the target system:

• A 10-pin header connector should be made available, with electrical connections matching Figure 4-3.

• Pull-down resistors, of approximately 1 KΩ should be connected over DSDI1 and DSCK1 signals. These resistors are to provide normal2 operation, when a debug-port controller, is not connected to the target system

• The debug-port should be enabled and routed to the desired pins. See the DBGC and DBPC fields within the hard-reset configuration word.

1Remember that the location of DSDI and DSCK is determined by the hard-reset configuration.2Normal, that is, boot through CS0.




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4.9.2 Debug Port Control / Status Register

The control/status register is an 8-bit register (bit 7 stands for MSB). Table 4-13 shows thedebug port control/status register.

Table 4-13. Debug Port Control / Status Register

Bits Mnemonic FunctionI/F

Reset DEF

Attr

7 MpcRst MPC885 reset. This status only bit indicates when active (high) that either a SOFT or a HARD reset is driven by the MPC885.

— R

6 TxError Transmit error. When this status only bit is active (high) it indicates that the last transmission towards the MPC885, was cut by an internal MPC885 reset source. This bit is updated for each byte sent.

— R

5 InDebug In debug mode. When this status only bit is active (high) it indicates that the MPC885 is in debug mode 1.

1 Provided that the PCMCIA channel II pins are configured as debug pins, that is, VFLS(0:1) signals are available. If not, the debug port can not be operated correctly.

— R

4–3 DebugClockFreq Debug clock frequency select. This field controls a frequency divider which divides DSCK. For the division factors and associated DSCK frequencies, see Table 4-14.

00 R/W

2 StatusRequest Status request. When the host writes this bit active (low), the I/F will issue a status read request to the host by asserting ADS_REQ line to the host. When the host writes the control register with this bit negated, no status read request is issued.Upon I/F reset this bit wakes-up active.

0 R/W

1 DiagLoopBack Diagnostic loopback mode. When this control bit is active (low) the I/F is placed in diagnostic loopback mode. That is, DSDI is connected internally to DSDO, DSDI is tri-stated, and each data byte sent to the I/F data register, is sampled back into the receive shift register. This mode allows for complete ADI I/F test, up to transmit and receive shift registers.Upon I/F reset this bit wakes-up active.

0 R/W

0 DebugEntry Debug mode entry. When this bit is active (low), the MPC885 will enter debug mode instantly after SOFT reset. When inactive, the MPC885 will start executing normally and will enter debug mode only after exception.Upon I/F reset this bit wakes-up active.

0 R/W

Table 4-14. DSCK Frequency Select

DebugClockFreqDSCK

Frequency (MHz)

00 10

01 5




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Figure 4-3. Standard Debug Port Connector

4.9.3 Standard MPC885 Debug Port Connector Pin Description

The pins on the standard debug port connector are the maximal group needed to supportdebug port controllers for both the MPC8xx and MPC885 families. Some of the pins areredundant for the MPC885 family but are necessary for the MPC8xx family.

4.9.3.1 VFLS(0:1)

These pins indicate to the debug port controller whether or not the MPC885 is in debugmode. When both VFLS(0:1) are at 1, the MPC885 is in debug mode. These lines may servealternate functions with the MPC885, in which case FRZ needs to selected on either theADS or target system1.

4.9.3.2 HRESET

This is the Hard-Reset bi-directional signal of the MPC885. When this signal is asserted(low) the MPC885 enters hard reset sequence which includes hard-reset configuration. Thissignal is made redundant with the MPC885 debug port controller since there is a hard-resetcommand integrated within the debug port protocol.

10 2.5

11 1.25

1If a target system needs to use VFLS(0:1) alternate function, the FRZ line should be connected to both VFLS(0:1) pins on the debug port connector.

Table 4-14. DSCK Frequency Select (continued)

DebugClockFreqDSCK

Frequency (MHz)

1

3

5

7

9

2

4

6

8

10

VFLS0 SRESET

DSCK

VFLS1

DSDI

DSDO

GND

GND

HRESET

VDD



Power Supplies

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4.9.3.3 SRESET

This is the soft-reset bi-directional signal of the MPC885. The debug port configuration issampled and determined on the rising-edge1 of SRESET (for both processor families). Onthe MPC885 it is a bidirectional signal that may be driven externally to generate soft resetsequence. This signal is in fact redundant regarding the MPC885 debug port controllersince there is a soft-reset command integrated within the debug port protocol.

4.9.3.4 DSDI—Debug-Port Serial Data In

Through the DSDI signal, the debug port controller sends its data to the MPC885. TheDSDI serves also a role during soft-reset configuration. (See Section 4.1.5.3, “Soft-ResetConfiguration.”)

4.9.3.5 DSCK—Debug-Port Serial Clock

During asynchronous clock mode, the serial data is clocked into the MPC885 according2

to the DSCK clock. The DSCK serves also a role during soft-reset configuration. (SeeSection 4.1.5.3, “Soft-Reset Configuration”).

4.9.3.6 DSDO—Debug-Port Serial Data Out

DSDO is clocked out by the MPC885 according to the debug port clock, in parallel3 withthe DSDI being clocked in. The DSDO serves also as the ready signal for the debug portcontroller to indicate that the debug port is ready to receive the controller’s command (ordata).

4.10 Power SuppliesThe power supply provides optioning to support both the versatile requirements for failureanalysis and fixed supplies to support customer development systems.

4.10.1 Power to Board

Power is supplied to the ADS through the same modular, switching, 5-V, 6-A DC powersupply used in many other PowerQUICC ADSs. Connection to the AC side of the supplyis through a standard 3-prong receptacle that accepts cabling to the various country specificwall jacks. A cable molded to this supply provides the DC voltage to the ADS board. Thespecific part number for this external supply is: SCEPTRE, SPU41-1, PS-5060APL05

1In fact that configuration is divided into two parts, the first is sampled 3 system clock cycles prior to the rising edge of SRESET and the second is sampled 8 clocks after that edge.

2DSDI must meet setup / hold time to / from rising edge of the DSCK.3Full-duplex communication.



Power Supplies

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4.10.2 Processor Power

A regulated 3.3-V supply for I/O and a separate regulated 1.8-V supply for the core providethe power for the MPC885 processor. Each of these supplies provides connections formeasuring voltage and current. Note that for failure analysis a different set of regulators canbe loaded along with circuits for varying the supply voltage and enabling/disabling thesupplies externally. The variable regulator circuits can control the 3.3-V output from 4.3 Vdown to about 1.3 V and the 1.8-V output from 2.7 V down to 1.3 V.

4.10.3 Other On-Board Power

Other supplies on the board include a regulated 3.3 V for many of the circuits and anunregulated 5 V coming from the off-board supply.

4.10.4 PCMCIA Interface

The power supplied to the PCMCIA interface is consistent with the circuits found on theMPC866ADS. Software controls the switching of 5 V or 3.3 V to this interface. Aprogramming voltage is also provided to the interface.

4.10.5 USB Interface

5 V of power is optionally provided for the USB connector, controlled by USB_VCC inBCSR4. When USB_VCC0 is driven high, a 5-V supply is connected to pin 1 of the USBconnector.



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Chapter 5 Support InformationThis chapter provides all the information needed to support, maintain, and connect to theMPC885ADS.

5.1 Interconnect SignalsThe MPC885ADS connects to external devices through the following set of connectors:

• J6 — External clock in

• J7 —I2C interface connector

• J8—ATM25 RJ45 connector

• J11—PCMCIA port

• J12 — Not Used

• J13—JTAG connector for Altera programing

• J14—3-pin 5-V power in

• J15—12-V power in

• J16—EPP

• J19 — Not Used

• J20 — EPP enable connector

• J21—External debug port controller input and output

• J22—T1/E1 RJ45 connector

• J23, J24, J25, J26, J27, J28, J29, and J30 logic analyzer connectors

• J31—CPM expansion connector

• J32—CPM expansion connector

• J33A—EIA232 port 1

• J33B—EIA232 port 2

• J34—10BaseT Ethernet port

• J35 and J36—100BaseT Ethernet ports. RJ45

• J37 — Series A Connector

MOTOROLA Chapter 5. Support Information 5-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE


Interconnect Signals

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• J38 — Series B Connector

• J39—ISP connector for Mach programing

• U14—ATM155 multi-mode optical connector

• U43—Infrared interface

5.1.1 J34—10BaseT Ethernet Port Connector

The Ethernet connector on the MPC885ADS, J34, is a twisted-pair (10BaseT)-compatibleconnector. The Ethernet port uses a 90o, 8-pin, RJ45 connector. The signals of the J34 aredescribed in Table 5-1.

5.1.2 J33A and J33B—EIA232 Ports Connectors

The EIA232 ports’ connectors, J33A and J33B, are 90°, 9-pin, female D-type stackedconnectors, with A being the lower connector. The signals of the J33A and J33B arepresented in Table 5-2

Table 5-1. J34—Ethernet Port Interconnect Signals

Pin No. Signal Name Description

1 TX + Twisted-pair transmit data positive output from the MPC885ADS

2 TX – Twisted-pair transmit data negative output from the MPC885ADS

3 RX + Twisted-pair receive data positive input to the MPC885ADS

4 — Not connected

5 — Not connected

6 RX – Twisted-pair receive data negative input to the MPC885ADS

7 — Not connected

8 — Not connected

Table 5-2. J33A and J33B Interconnect Signals


1 CD Carrier detect output, is always asserted by the MPC885ADS

2 TX Transmit data output from the MPC885ADS

3 RX Receive data input to the MPC885ADS

4 DTR Data terminal ready input to the MPC885ADS (PB23 input for SMC1 / PB23 input for SMC2)

5 GND Ground signal of the MPC885ADS

6 DSR Data set ready, is always asserted from the MPC885ADS.




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7 RTS (N.C.) Request to send. This line is not connected to the MPC885ADS.

8 CTS Clear to send, is always asserted from the MPC885ADS

9 — Not connected

Table 5-2. J33A and J33B Interconnect Signals (continued)





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5.1.3 J22—T1/E1 RJ45 Connector

The T1/E1 connector on the MPC885ADS, J22, is a twisted-pair 8-pin connector. Thesignals of the J22 are described in Table 5-3.

5.1.4 J8—ATM25 RJ45 Connector

The ATM25 connector on the MPC885ADS, J8, is a twisted-pair 8-pin connector. Thesignals of the J8 are described in Table 5-4.

Table 5-3. J22—T1/E1 RJ45 Connector




3 GND Connected to GND



6 GND Connected to GND

7 — Not connected

8 — Not connected

Table 5-4. J8—ATM25 RJ45 Connector


1 TX + Twisted-pair transmit data positive input to the MPC885ADS

2 TX – Twisted-pair transmit data negative input to the MPC885ADS

3 Not connected Not connected




7 RX + Twisted-pair receive data positive output from the MPC885ADS

8 RX – Twisted-pair receive data positive output from the MPC885ADS




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5.1.5 U14—ATM155 Multi-Mode Optical Connector

The U14 is an optical connector with RX and TX SC type also for receive and transmit.

5.1.6 MPC885ADS J31—CPM Expansion Connector

J31 is a 90°, 96-pin, DIN 41612 connector that allows for the convenient expansion of theMPC885’s serial ports.

Table 5-5. J31—MPC885ADS Interconnect Signals

Pin No. Signal Name

A1 VCC

A2 VCC

A3 VCC

A4 VCC

A5 VCC

A6 N.C.

A7 GND

A8 GND

A9 GND

A10 GND

A11 GND

A12 GND

A13 GND

A14 PE31

A15 PE30

A16 PE29

A17 PE28

A18 PE27

A19 PE26

A20 PE25

A21 PE24

A22 PE23

A23 PE22

A24 PE21

A25 PE20




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A26 PE19

A27 PE18

A28 PE17

A29 PE16

A30 PE15

A31 PE14

A32 GND

B1 PB31

B2 PB30

B3 PB29

B4 PB28

B5 PB27

B6 PB26

B7 PB25

B8 PB24

B9 PB23

B10 PB22

B11 PB21

B12 PB20

B13 PB19

B14 PB18

B15 PB17

B16 PB16

B17 PB15

B18 PB14

B19 GND

B20 PC15

B21 PC14

B22 PC13

B23 PC12

B24 PC11

Table 5-5. J31—MPC885ADS Interconnect Signals (continued)

Pin No. Signal Name




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B25 PC10

B26 PC9

B27 PC8

B28 PC7

B29 PC6

B30 PC5

B31 PC4

B32 GND

C1 PA15

C2 PA14

C3 PA13

C4 PA12

C5 PA11

C6 PA10

C7 PA9

C8 PA8

C9 PA7

C10 PA6

C11 PA5

C12 PA4

C13 PA3

C14 PA2

C15 PA1

C16 PA0

C17 Vcc

C18 N.C.

C19 PD15

C20 PD14

C21 PD13

C22 PD12

C23 PD11


Pin No. Signal Name




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5.1.7 J23, J24, J25, J26, J27, J28, J29, and J30 Logic Analyzer Connectors

These connectors are 38-pin, receptacle MICTOR connectors manufactured by AMP. Eachconnector connects to a dedicated adapter for the HP 16500 series logic analyzer, whichinterconnects to two 16-bit pods. Table 5-6 through Table 5-13 show the interconnectsignals for these connectors.

C24 PD10

C25 PD9

C26 PD8

C27 PD7

C28 PD6

C29 PD5

C30 PD4

C31 PD3

C32 GND

Table 5-6. J23—Interconnect Signals

PinNo.

MPC885Signal Name

PinNo.

MPC885Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 SYSCLK 6 MODCK1

7 A0 8 A16

9 A1 10 A17

11 A2 12 A18

13 A3 14 A19

15 A4 16 A20

17 A5 18 A21

19 A6 20 A22

21 A7 22 A23

23 A8 24 A24

25 A9 26 A25

27 A10 28 A26


Pin No. Signal Name




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29 A11 30 A27

31 A12 32 A28

33 A13 34 A29

35 A14 36 A30

37 A15 38 A31


Pin No.

MPC885Signal Name

Pin No.

MPC885Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 REGAb 6 TSIZ1

7 D0 8 D16

9 D1 10 D17

11 D2 12 D18

13 D3 14 D19

15 D4 16 D20

17 D5 18 D21

19 D6 20 D22

21 D7 22 D23

23 D8 24 D24

25 D9 26 D25

27 D10 28 D26

29 D11 30 D27

31 D12 32 D28

33 D13 34 D29

35 D14 36 D30

37 D15 38 D31

Table 5-6. J23—Interconnect Signals (continued)

PinNo.

MPC885Signal Name

PinNo.

MPC885Signal Name




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Pin No.

MPC885Signal Name

Pin No.

MPC885Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 TAb 6 TEAb

7 VFLS0 8 FCSb

9 VFLS1 10 BCSRCSb

11 AT2 12 DRMCS1b

13 VF2 14 DRMCS2b

15 VF0 16 SDRMCSb

17 VF1 18 CS5b

19 AT0 20 CS6b

21 AT3 22 CS7b

23 BGb 24 BS0Ab

25 BBb 26 BS1Ab

27 BRb 28 BS2Ab

29 BIb 30 BS3Ab

31 GPL5Bb 32 WE0b

33 BURSTb 34 WE1b

35 RWb 36 WE2b

37 TSb 38 WE3b


Pin No.

MPC885Signal Name

Pin No.

MPC885Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 EXTCLK 6 ALEA

7 N.C. 8 IRQ2b

9 AT1 10 IRQ3b

11 TEXP 12 N.C.

13 RESETA 14 N.C.

15 POEAb 16 N.C.

17 MODCK1 18 N.C.

19 MODCK2 20 N.C.




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21 RPORib 22 SPKROUT

23 RSTCNFb 24 BVS1

25 HRESETb 24 BVS2

27 SRESETb 28 BWP

29 WAITBb 30 BCD2b

31 WAITAb 32 BCD1b

33 GPL4Ab 34 BBVD1

35 GPL4Bb 36 BBVD2

37 CE1Ab 38 BRDY


Pin No.

MPC885Signal Name

Pin No.

MPC885Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 IRQ1b 6 IRQ7b

7 NMIb 8 PB16

9 PD3 10 PB17

11 PD4 12 PB18

13 PD5 14 PB19

15 PD6 16 PB20

17 PD7 18 PB21

19 PD8 20 PB22

21 PD9 22 PB23

23 PD10 24 PB24

25 PD11 26 PB25

27 PD12 28 PB26

29 PD13 30 PB27

31 PD14 32 PB28

33 PD15 34 PB29

35 PB14 36 PB30

37 PB15 38 PB31


Pin No.

MPC885Signal Name

Pin No.

MPC885Signal Name




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Pin No.

MPC885 Signal Name

Pin No.

MPC885 Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 DRMWb 6 BCE2Ab

7 GPL5Ab 8 PA0

9 GPL3b 10 PA1

11 GPL2b 12 PA2

13 OEb 14 PA3

15 PC4 16 PA4

17 PC5 18 PA5

19 PC6 20 PA6

21 PC7 22 PA7

23 PC8 24 PA8

25 PC9 26 PA9

27 PC10 28 PA10

29 PC11 30 PA11

31 PC12 32 PA12

33 PC13. 34 PA13

35 PC14 36 PA14

37 PC15 38 PA15


Pin No.

MPC885 Signal Name

Pin No.

MPC885 Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 EPP_ CLK 6 N.C.

7 PP_INTb 8 HRESETb

9 BDM_ DSCK 10 PP_AD7

11 BDM_ DSDI 12 PP_AD6

13 PP_WEb 14 PP_AD5

15 PP_VFLSP0 16 PP_AD4

17 FRZ 18 PP_AD3




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19 PP_ VFLSP1 20 PP_AD2

21 VFLS0 22 PP_AD1

23 VFLS1 24 PP_AD0

25 SRESETb 26 PP_BUSY_ OUT

27 RPORIb 28 PP_RSTb

29 TP62 30 PP_ASTRb

31 TP66 32 PP_DSTRb

33 TP64 34 BDM_ DSDO

35 TP71 36 TP69

37 TP68 38 TP72


Pin No.

MPC885 Signal Name

Pin No.

MPC885 Signal Name

1 N.C. 2 N.C.

3 GND 4 N.C.

5 PE14 6 PE31

7 PE15 8 R/MIICRS1

9 PE16 10 MPCMDIO

11 PE17 12 R/MIITXEN1

13 PE18 14 R/MIICOL1

15 PE19 16 TP55

17 PE20 18 TP56

19 PE21 20 TP57

21 PE22 22 TP58

23 PE23 24 TP59

25 PE24 26 TP60

27 PE25 28 TP61

29 PE26 30 TP63

31 PE27 32 TP65

33 PE28 34 TP67


Pin No.

MPC885 Signal Name

Pin No.

MPC885 Signal Name




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5.1.8 J21—External Debug Port Controller Input Interconnect

The debug port connector, J21, is a 10-pin, male, header connector. The signals of the J21are described in Table 5-14.

35 PE29 36 TP70

37 PE30 38 TP73


Pin No.

Signal Name Attribute Description

1 VFLS0 O Visible history flushes status 0. Indicates in conjunction with VFLS1, the number of instructions flushed from the core’s history buffer. Indicates also whether the MPC is in debug mode. If not using the debug port, may be configured for alternate function.When the ADS is disconnected from the ADI bundle, it may be FRZ signal, depending on J1’s position.

2 SRESET~ I/O Soft reset line of the MPC. Active low, open-drain

3 GND Ground

4 DSCK I/O Debug serial clock. Over the rising edge of which serial data is sampled by the MPC from DSDI signal. Over the falling edge of which DSDI is driven towards the MPC and DSDO is driven by the MPC. Configured on the MPC’s JTAG port.When the debug-port controller is on the local MPC or when the ADS is a debug-port controller for a target system - OUTPUT, when the FADI bundle is disconnected from the ADS - INPUT.

5 GND Ground

6 VFLS1 O See VFLS0. When the ADS is disconnected from the ADI bundle, it may be FRZ signal, depended on J1’s position.

7 HRESET~ I/O Hard reset line of the MPC. Active low, open-drain

8 DSDI I/O Debug serial data in of the debug port. Configured on the MPC’s JTAG port.When the debug-port controller is on the local MPC or when the ADS is a debug-port controller for a target system - OUTPUT, when the ADI bundle is disconnected from the ADS - INPUT.

9 V3.3 O 3.3-V power indication. This line is merely for indication. No significant power may be drawn from this line.


Pin No.

MPC885 Signal Name

Pin No.

MPC885 Signal Name




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5.1.9 J35 and J36—100BaseT Ethernet Port Connectors

The Ethernet connectors on the MPC885ADS, J35 and J36, are twisted-pair (100BaseT)compatible connectors. The connectors are 90o, 8-pin, RJ45 connector; the signals aredescribed in Table 5-15.

5.1.10 J15—12-V Power Connector

The 12-V power connector, J15, is a two-lead, two-part, terminal block connector that isidentical in type to the 5-V connector. When necessary, J15 supplies programming voltageto the Flash SIMM and/or to the PCMCIA.

10 DSDO I/O Debug serial data output from the MPC. Configured on the MPC’s JTAG port.When the debug-port controller is on the local MPC or when the ADI bundle is disconnected from the ADS - OUTPUT, when the ADS is a debug-port controller for a target system - INPUT.

Table 5-15. J35 and J36—Ethernet Port Interconnect Signals

Pin No.

Signal Name Description




4 — Not connected

5 — Not connected


7 — Not connected

8 — Not connected


Pin No.


1 12V 12-V input from external power supply

2 GND GND line from external power supply


Pin No.





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5.1.11 J14—5-V Power Connector

The 5-V power connector, J14, is a three-lead, two-part, terminal block. The male part issoldered to the PCB, while the receptacle is connected to the power supply. This facilitatesfast connection or disconnection of power and avoids physical effort on the solder joints,which therefore maintains solid connection over time.

5.1.12 J14—2.1-mm Power Jack Connector

J14 is a 2.1-mm plug jack connector that is connected to the power supply supplied withthe board. In order to operate the board, the user should plug the connector of the powersupply into this connector.

5.1.13 J39—Mach’s In-System Programming (ISP)

This is a 10-pin generic 0.100" pitch header connector that provides in-systemprogramming capability for Vantis-made programmable logic on the board. A pinout of J39is shown in Table 5-18.


Pin No.


1 5V 5-V input from external power supply



Table 5-18. J39 (ISP Connector)—Interconnect Signals

Pin No.

Pin Name Attribute Description

1 ISPTCK I ISP test port clock. This clock shifts in/out data to/from the programmable logic JTAG chain.

2 N.C. — Not connected

3 ISPTMS I ISP test mode select. This signal, qualified with ISPTCK, changes the state of the prog. logic JTAG machine.

4 GND O Digital GND. Main GND plane.

5 ISPTDI I ISP transmit data in. This is the program logic’s JTAG serial data input.

6 VCC O 5-V/3.3 power supply bus. The power can be changed by RJ4 by connecting a resistor from 1, 2 to power 5 V, or 2, 3 to power 3.3 V




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5.1.14 J13—JTAG Connector For Altera Programing

This is a 10-pin generic 0.100" pitch header connector that provides in-systemprogramming capability for the Altera-made programmable logic on the board. A pinout ofJ13 is shown in Table 5-19.

5.1.15 Expansion Connector ADD, Data Control, and PCMCIA Port

J32 is a 90°, 96-pin, DIN 41612 connector that allows for convenient expansion of theMPC885. This connector includes the necessary signals to connect external peripheralswith address data and control signals. This connector also includes PCMCIA signals thatcan be used for ATM split mode. To use ATM split from the expansion connectors, the user

7 ISPTDO O ISP transmit data output. This is the program logic’s JTAG serial data output driven by the falling edge of TCK.




Table 5-19. J13 (JTAG Connector for Altera Programing)—Interconnect Signals

Pin No.


1 TCK I Test port clock. This clock shifts in / out data to / from the programmable logic JTAG chain.


3 TDO O Transmit data output. This the program logic’s JTAG serial data output driven by the falling edge of TCK.

4 VCC O 5-V power supply bus

5 TMS I Test mode select. This signal qualified with TCK, changes the state of the prog. logic JTAG machine.




9 TDI I Transmit data in. This is the program logic’s JTAG serial data input.


Table 5-18. J39 (ISP Connector)—Interconnect Signals (continued)

Pin No.





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should control it through SW3(2,3,4); most of the pins are on J31 and the PCMCIA pins areon J32. This connector also includes the following MII signals for use on the externalboard: CRS, MDIO, TXEN, and COL.

Table 5-20. J32—MPC885ADS’s Interconnect Signals

Pin No.


A1 EXP_BD0 Buffered data








A9 EXP_A16 Buffered address
















A25 N.C.

A26 HRESET

A27 SRESET

A28 RPORI




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A29 VPPIN

A30 SW_MODCK1

A31 SW_MODCK2

A32 GND

B1 V3.3

B2 V3.3

B3 V3.3

B4 V3.3

B5 V3.3

B6 V3.3

B7 N.C.

B8 GND

B9 GND

B10 GND

B11 GND

B12 GND

B13 GND

B14 BCEA1

B15 BCEA2

B16 BALEA

B17 FRZ

B18 IRQ7

B19 IRQ3

B20 IRQ2

B21 IRQ1

B22 NMI

B23 N.C.

B24 MPCMDIO

B25 MPCMDC

B26 GND

B27 N.C.

Table 5-20. J32—MPC885ADS’s Interconnect Signals (continued)

Pin No.





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B28 GND

B29 N.C.

B30 GND

B31 N.C.

B32 GND

C1 BWAITA

C2 IPA0

C3 IPA1

C4 IPA2

C5 IPA3

C6 IPA4

C7 IPA5

C8 IPA6

C9 IPA7

C10 GND

C11 BRESETA

C12 GND

C13 N.C.

C14 BWE0

C15 BDRMW

C16 BEDOOE

C17 BGPL2

C18 BGPL3

C19 GPL4A

C20 GPL4B

C21 GPL5A

C22 GPL5B

C23 GND

C24 BSYSCLK3

C25 GND

C26 BS0A


Pin No.





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5.1.16 PCMCIA Port Connector

The PCMCIA port connector, J11, is a 90°, 68-pin, male, PC card type. The signals of theJ11 are presented in Table 5-21.

C27 GND

C28 BRW2

C29 BTS

C30 TA

C31 CS7

C32 CS6

Table 5-21. J11—PCMCIA Connector Interconnect Signals

Pin No.


1 GND Ground

2 PCCD3 I/O PCMCIA data line 3





7 BCE1A~ O PCMCIA chip enable 1. Active low. Enables even-numbered address bytes

8 PCCA10 O PCMCIA address line 10

9 OE~ O PCMCIA output enable signal. Active low. Enables data outputs from PC card during memory read cycles.





14 PCCA14 O PCMCIA address line 14.

15 WE~/PGM~ O PCMCIA memory write strobe. Active low. Strobes data to PC card during memory write cycles.


Pin No.





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16 RDY I +Ready/-Busy signal from PC card. Allows PC card to stall access from the host in case a previous access’ processing is not completed.

17 PCCVCC O 5-V VCC for the PC card. Switched by the MPC885ADS, through BCSR1.

18 PCCVPP O 12-V/5-V VPP for PC-card programming. 12 V available only if 12 V is applied to P8. Controlled by the MPC885ADS through BCSR1.




22 PCCA7 O PCMCIA address line











33 WP I Write protect indication from the PC card

34 GND Ground

35 GND Ground

36 CD1~ I Card detect 1~. Active low. Indicates in conjunction with CD2~ that a PC card is placed correctly in socket.






42 BCE2A~ O PCMCIA chip enable 2. Active low. Enables odd-numbered address bytes.

Table 5-21. J11—PCMCIA Connector Interconnect Signals (continued)

Pin No.





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43 VS1 I Voltage sense 1 from the PC card. Indicates in conjunction with VS2, the operation voltage for the PC card.

44 IORD~ O I/O read. Active low. Drives data bus during I/O cards’ read cycles.

45 IOWR~ O I/O write. Active low. Strobes data to the PC card during I/O card write cycles.






51 PCCVCC O 5-V VCC for the PC card. Switched by the MPC885ADS, through BCSR1.

52 PCCVPP O 12-V/5-V VPP for PC-card programming. 12 V available only if 12 V is applied to P8. Controlled by the MPC885ADS, through BCSR1.





57 VS2 I Voltage sense 2 from the PC card. Indicates in conjunction with VS1, the operation voltage for the PC card.

58 RESET O Reset signal for the PC card

59 WAITA~ I Cycle wait from the PC card. Active low.

60 INPACK~ I Input port acknowledge. Active low. Indicates that the PC card can respond to I/O access for a certain address.

61 PCREG~ O Attribute memory or I/O space - Select. Active low. Used to select either attribute (card-configuration) memory or I/O space.

62 BVD2 I Battery voltage detect 2. Used in conjunction with BVD1 to indicate the condition of the PC card’s battery.

63 BVD1 I Battery voltage detect 1. Used in conjunction with BVD2 to indicate the condition of the PC card’s battery.




67 CD2~ I Card detect 2~. Active low. Indicates in conjunction with CD1~ that a PC card is placed correctly in socket.


Pin No.




MPC885ADS Part List

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5.2 MPC885ADS Part ListIn this section, the MPC885ADS’s bill of materials is listed according to each part’sreference designation.

68 GND Ground


Pin No.




MPC885ADS Part List

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Table 5-22. MPC885ADS Part List

Reference Designation Description ManufacturerManufacturer's Part Number (usually 7"

taped reel)

C4 C9 C11 C13 C15 C17 C19 C21 C24 C30 C31 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C100 C101 C102 C103 C104 C105 C106 C107 C108 C110 C113 C114 C115 C116 C117 C118 C120 C122 C124 C126 C128 C130 C132 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C160 C162 C164 C169 C176 C185 C187 C190 C193 C194 C195 C196 C223 C224 C225 C226 C227 C228 C229 C230 C231 C232 C233 C234 C235 C236 C238 C243 C244 C245 C247 C248 C249 C253 C254 C255 C256 C257 C258 C259 C260 C261 C262 C263 C264 C265 C271 C272 C273 C274 C275 C282 C284 C292 C293 C294 C295 C299 C300 C301 C302 C303 C304 C305 C306 C307 C308 C309 C313 C314 C315 C316 C317 C318 C319 C320 C321 C324 C325 C326 C327 C328 C329 C330 C331 C332 C333 C337 C338 C339 C340 C341 C342 C343 C345 C346 C347 C348 C349 C350 C351 C355 C356 C357 C358 C359 C360 C361 C362 C363 C364 C365 C366 C367 C368 C373 C374 C376

Capacitor ceramic 0.1 µF 16 V 10% X7R

Novacap AVX Kemet

0603B104K250NT 06033C104KAT2A C0603C104K5RAC

C5 C10 C12 C14 C16 C18 C20 C22 C25 C29 C89 C90 C91 C92 C93 C94 C95 C96 C97 C112 C123 C159 C161 C163 C165 C167 C170 C177 C179 C241 C242 C250 C251 C252 C283 C369

Capacitor ceramic 0.01 µF 25 V 10% X7R

AVX 06033C103KAT2A



MPC885ADS Part List

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C23 C63 C64 C65 C66 C98 C99 C119 C121 C125 C127 C129 C131 C133 C173 C174 C175 C182 C184 C239 C240 C281 C297 C298 C311 C312 C335 C336

Capacitor tantalum 10 µF 16 V 20% Venkel CorpKemet

TA016TCM106MBR T496B106M016AS

C109 C111 Capacitor ceramic 470 pF 50 V 10% C0G

Novacap AVX Kemet Murata Panasonic Philips Electronics NV

0805N471K500NT 08055A471KT2A C0805C471K5GAC GRM40C0G471K50PT ECUV1H471KCG 0805CG471K9B00

C166 C178 Capacitor ceramic 1000 pF 16 V 10% X7R

AVX 0603YC102KAT2A

C168 C172 C191 C372 C375 Capacitor tantalum 100 µF 10 V 20%

AVX TAJD107M010R

C171 C183 Capacitor tantalum 1 µF 16 V 20% Nichicon

Panasonic

AVX

Kemet NEC Vishay Sprague

F931C105MA F931E105MA ECST1CY105R ECST1EY105R TAJA105M016R TAJA105M025R T491A105M025AS NRA105M25R08 293D105X0025A2T

C180 C246 Capacitor tantalum 68 µF 20 V 20% Kemet AVX

T491D686M020AS TAJD686M020R

C188 Capacitor ceramic 0.01 µF 1 KV 10% X7R

Novacap 1210B103K102NXTM

C189 Capacitor ceramic 100 pF 16 V 10% C0G

Novacap

AVX

Kemet Murata Panasonic Philips Electronics NV

0805N101K160NT 0805N101K250NT 0805N101K500NT 08053A101KT2A 08055A101KT2A C0805C101K5GAC GRM40C0G101K50PT ECUV1H101KCG 0805CG101K9B00

C197 C198 C199 C200 C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 C222 C266 C267 C268 C269 C270 C276 C277 C278 C279 C280

Capacitor ceramic 0.01 µF 1.5 KV 10% X7R

Novacap 1206B152K102NTM

C237 Capacitor polyester 0.47 µF 100 V 10% MPF

Panasonic ECWU1474KCV

Table 5-22. MPC885ADS Part List (continued)


taped reel)



MPC885ADS Part List

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C285 C344 Capacitor tantalum 4.7 µF 10 V 10%

SMEC TCC4.7K10A

C286 C287 C288 C289 C290 C291

Capacitor ceramic 120 pF 16 V 10% C0G

Novacap

AVX



C296 C310 C322 C323 C334 Capacitor ceramic 1000 pF 2 KV 20% X7R

Novacap

AVX Venkel Corp.

1808B102M202NT 1808B102M302NT 1808GC102MT1A C1808X7R202102MNE C1808X7R302102MNE

C371 C370 Capacitor ceramic 18 pF 16 V 10% C0G

Novacap

AVX



D1 D2 D11 D12 D15 D31 D32 D39 D42 D43 D46 D47 D48

Diode LED chip green 25 mA 2 V Agilent Technologies Infineon

HSMG-C650 Q62702-P5191

D3 D6 Diode dual Schottky power rectifier MBRD620CTL 20 V 6 A

On Semiconductor MBRD620CT

D4 Diode Zener transient voltage Suppressor 5 V 1500 W peak

On Semiconductor 1SMC5.0AT3

D7 Diode Zener transient voltage Suppressor 12 V 1500 W peak

On Semiconductor 1SMC12AT3

D9 D10 D13 D33 D34 D35 D36

Diode-switching high-speed MMBD914 75 V 75 mA

On Semiconductor Zetex

MMBD914LT1 FMMD914TA

D14 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D38 D41 D45

Diode LED chip yellow 20 mA 2 V Infineon Q62702-P5193

D37 D40 D44 Diode LED chip red AlGaAs 25 mA 1.8 V

Agilent Technologies HSMH-C650

FID1 FID2 FID3 FID4 NOT A COMPONENT—Fiducial small, 1.2-mm ring, 0.6-mm drill

N/A N/A

F1 Fuse polyswitch resettable device 2.6 A 6 V SMT

Raychem SMD260



taped reel)



MPC885ADS Part List

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F2 F3 Fuse polyswitch resettable device 1.5 A 33 V SMT

Raychem SMD150/33

JP1 JP2 JP5 JP6 JP7 JP8 JP9 JP10 JP11 JP12 JP13

Jumper wire 0.2" thru-hole Mill-Max 3360-1-14-15-00-00-08-0

J2 Conn SIMM 2×40 position 1.27-mm spacing

AMP 822021-5

J3 BGA357 socket, thru-hole, lidded, 25-mm sq.

3M 2357-1382-xx-1101

J3 BGA357 socket, thru-hole, open top, 25-mm sq.

3M 2357-9269-xx-2401

J5 Osc. socket half size DIP 8 Aries Elec. 1108800

J6 Conn SMB vertical Amp 221111-1

J7 J12 Conn header 1×3 0.1CTR SM 0 0

J8 J22 J34 J35 J36 Jack modular 8-pin RJ45 Amp 520251-4

J9 J10 Conn header shrouded 2×25 0.1CTR

FCI AMP/Tyco 52601-S50-4R 1-103308-0

J11 Conn PCMCIA right angle Molex 533806810

J13 J16 J21 J39 Conn header 2×5 0.1CTR SM 0 0

J14 Conn terminal block 1×3 5.08-mm CTR

On Shore Technology EDZ250/3

J15 Conn terminal block 1X2 5.08-mm CTR

On Shore Technology EDZ250/2

J17 Socket 0.1"×0.3" DIP 8 surface mount ‘tails-in’

Samtec ICF308SI

J18 Receptacle DB25 right angle PC mount TH

AMP 745783-4

J19 J20 Conn header 1×2 0.1CTR FCI 69190-402

J23 J24 J25 J26 J27 J28 J29 J30 Mictor 19×2 Receptacle AMP 2-767-004-2

J31 J32 Conn Right Angle Shrouded Receptacle 3 rows (3x32)

AVX or ELCO 26-8477-096-002-025

J33 Conn dual port D-sub female/female

NorComp 189-009-512-571

J37 Conn universal serial bus type A (USB) black

AMP 787616-6

J38 Conn universal serial bus type B (USB) black

AMP 787780-1

L1 Inductor 8200 µH 10% Q=90@252 KHz

Bourns PT12133



taped reel)



MPC885ADS Part List

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L2 L3 L5 L6 L7 L8 L9 L10L11 L12 L32 L34 L35 L36 L47 L48 L49 L52

Inductor ferrite suppression filter LC combined 3-pin

muRata NFE31PT222Z1E9

L4 Inductor 3.3 µH TDK NL322522T-3R3M

L13 Choke common-mode DC power line SMD

TDK ACM1110

L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L37 L38 L39 L40 L41 L42 L43 L44 L45 L46

Inductor ferrite bead 120 Ω @ 100 MHz 200 mA

muRata BLM18AG121SN1D

L33 Choke common mode 500 V 0.4 Ω DCR 47.0 µH

Pulse PE-65854

L51 L50 Inductor ferrite bead 68 Ω @ 100 MHz 640 mA

Fair-Rite 2743001112H

MH1 MH2 MH3 MH4 NOT A COMPONENT—Mounting hole 125-mil drill, no ring, non-plated through

N/A N/A

Q1 Q2 Transistor power MOSFET 2 A 20 V P-channel SO-8 dual

On Semiconductor MMDF3N03HDR2

Q6 Q4 Transistor power MOSFET 3 A 30 V P-channel SO-8 dual

On Semiconductor MMDF2P02HDR2

Q5 Dual power MOSFET 4 A 20 V 0.045 Ω

On Semiconductor MMDF4N01HD

RJ1 RJ2 RJ3 RJ4 RJ5 RJ6 RJ7 RJ8 RJ9 RJ10 RJ15 RJ16 RJ17 RJ18 RJ19 RJ20 RJ21

Resistor 0 1/10W 1% AVX/Kyocera CJ10-000F-T

RJ12 RJ11 Resistor 0 1/10W 1% AVX/Kyocera CJ10-000F-T

RN1 RN2 RN3 RN4 RN5 RN6RN7 RN8 RN9 RN10

Resistor network 8× common 10K 1/16W 5%

AVX/Kyocera Panasonic

RNA4A8E103JT EXBE10C103J

RP1 RP18 RP19 RP20 RP21 RP22 RP23 RP24

Resistor array 4× discrete 22 1/16W 5%

AVX/Kyocera KOA Speer Venkel Corp. Panasonic

CRA3A4E220JT CN1J4TE220J CRN16-4-220JT EXB-V8V220JV

RP3 RP4 RP5 RP7 RP8 RP10RP11 RP13 RP14 RP15 RP16

Resistor array 4× discrete 0 1/16W 5%

AVX/Kyocera CRA3A4E000JT

RP17 Resistor array 8× discrete 10K 1/16W 5%

CTS Corp. 742C163103J

RV4 RV3 3/8" square trim pot multiturn 1K TH Bourns 3296Y-1-102



taped reel)



MPC885ADS Part List

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R5 R6 Resistor 2.21K 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.

CR21-2211F-T RK73H2ATE2211F 2322 7326 2212 CRCW08052211FRT3 ERJ6ENF2211V CR0805-10W-2211FT

R7 R8 R9 R14 R15 R16 R23 R36 R47 R103 R104 R147 R172 R184 R185 R186 R187 R188 R205 R227 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R259

Resistor 0 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.

CJ21-000 -T RM73B2ATE000J 2322 730 91002 CRCW0805000JRT3 ERJ6GEYOR00V CR0805-10W-000JT

R10 R31 R32 R49 R50 R51 R54 R55 R56 R57 R58 R59 R60 R61 R62 R95 R98 R99 R111 R112 R113 R119 R120 R121 R122 R134 R135 R136 R137 R155 R156 R157 R217 R218 R219 R220 R226 R237 R238 R239 R240 R261 R265 R266 R267

Resistor 10.0K 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.


R12 R18 R20 R21 R53 R73 R74 R75 R93 R94 R100 R101 R105 R106 R116 R189 R190 R228 R263

Resistor 1.00K 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.


R17 Resistor 49.9 1/4W 1% Venkel Corp. CR1206-4W-49R9FT

R24 R35 Resistor 499 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.


R25 R27 R123 Resistor 47 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.

CR21-470J-T RM73B2ATE470J 2322 730 61479 CRCW0805470JRT3 ERJ6GEYJ470V CR0805-10W-470JT

R26 Resistor 619 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.




taped reel)



MPC885ADS Part List

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R28 R34 R130 Resistor 33.2 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.

CR21-33R2F-T RK73H2ATE33R2F 2322 732 63329 CRCW080533R2FRT3 ERJ6ENF33R2V CR0805-10W-33R2FT

R29 R38 R40 R42 R44 R46 Resistor 82.5 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.


R30 R33 Resistor 63.4 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.

CR21-63R4F-T RK73H2ATE63R4F 2322 732 66349 CRCW080563R4FRT3 ERJ-6ENF63R4V CR0805-10W-63R4FT

R37 R39 R41 R43 R45 Resistor 130 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.

CR21-1300F-T RK73H2ATE1300F 2322 732 61301 CRCW08051300FRT3 ERJ-6ENF1300V CR0805-10W-1300FT

R52 R143 R144 R145 R146 R168 R169 R170 R171 R201 R202 R203 R204



R63 Resistor 402 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.


R67 R65 Resistor 124K 1/16W 1% AVX/Kyocera CR21-1243F-T

R70 Resistor 5.11K 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.




taped reel)



MPC885ADS Part List

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R71 R72 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R96 R97 R150 R153 R174 R176 R178 R207 R209 R211



R76 Resistor 51.1K 1/10W 1% AVX/Kyocera CR21-5112F-T

R102 R125 R126 R127 R128 R129

Resistor 100 1/10W 1% AVX/KyoceraKOA Speer Philips Vishay Dale Panasonic Venkel Corp.



CR21-4R7J-T RM73B2ATE4R7J 2322 730 61478 CRCW08054R7JRT3 ERJ6GEYJ4R7V CR0805-10W-4R7JT

R109 R110 Resistor 470 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale Panasonic Venkel Corp.




R131 R124 Resistor 2.00K 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R132 R133 R161 R162 R195 R196

Resistor 49.9 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.




taped reel)



MPC885ADS Part List

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R138 R139 R163 R164 R194 R197

Resistor 22 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R140 R167 R200 Resistor 6.81K 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R141 R142 R165 R166 R198 R199

Resistor 78.7 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R148 R149 R151 R152 R158 R159 R160 R173 R175 R177 R180 R191 R192 R193 R206 R208 R210 R212

Resistor 100K 1/16W 1% AVX/Kyocera CR21-1003F-T

R154 R179 R216 Resistor 330 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R181 R182 R183 R213 R214 R215

Resistor 10.0K 1/16W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.

CR10-1002F-T RK73H1JTE1002F 2322 7046 1003 CRCW06031002FRT3 ERJ2RHF1002V CR0603-16W-1002FT

R221 Resistor 332 1/10W1% AVX/Kyocera CR21-3320F-T

R223 R222 Resistor 1.5K 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R224 R225 Resistor 24.3 1/10W 1% AVX/Kyocera CR21-24R3F-T



taped reel)



MPC885ADS Part List

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.

R257 Resistor 301 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R258 Resistor 35.7 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R260 Resistor 849 1/10W 1% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R264 Resistor 10M 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


R268 R269 Resistor 15K 1/10W 5% AVX/Kyocera KOA Speer Philips Vishay Dale PanasonicVenkel Corp.


S1 Transducer QMB-01 1.5 V 30 Ω 80 dB

Star Micronics Projects Unlimited

QMB-01 AT-01

S2 S4 Switch 4 position DIP surface mount J-lead

Grayhill 90HBJ04P

S3 Switch toggle PCB mount APEM 5236YCDB16X445

S5 Switch push button black PCB mount

ITT Cannon KS12R22CQD

S6 Switch push button red PCB mount

ITT Cannon KS12R23CQD

S7 Switch SPST SMD 2-position Grayhill 90HBW02P

TP1 TP2 TP3 TP4 TP5 TP16 TP17 TP18 TP19

NOT A COMPONENT—Testpoint via, 12-mil drill, 35-mil square pad

N/A N/A



taped reel)



MPC885ADS Part List

F

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c..

.

TP6 TP7 TP8 TP10 TP11 TP12 TP13 TP14 TP15

Test point PC 1×1 0.038DIA hole 0.05DIA eyelet plastic standoff

Concord Elect. Corp.

707-5402-10

T1 Transformer interface module ATM 25 PHY

Pulse PE-67583

T2 Transformer T1/E1 transmit and receive 1500Vrms 1:1.15CT & 1CT:2CT 0.7&0.7 DCR

Pulse PE-65865

T3 T4 T5 Isolation module 100BaseT 1500 V 1CT:1CT / 1CT:1CT 0.9 Ω DCR

Halo Midcom TG22-3506ND 7086-37

U1 IC SDRAM 2M×32 3.3 V 5.5 ns access 166 MHZ MT48LC2M32B2TG-6

Micron MT48LC2M32B2TG-6

U2 IC low voltage CMOS quad 2-input AND gate

Motorola 74LCX08D

U3 IC 32-bit bus transceiver with 3-state outputs

Standard SMD SN74LVC32245GKER

U4 IC 32-bit buffer/driver with 3-state outputs

Texas Instruments SN74LVC32244GKER

U6 U18 U39 U54 U55 IC 16-Bit buffer/driver with 3-state outputs

IDT UIDT74LVCH162244APA

U8 U9 U10 32- to 16-bit high-speed switch mux/demux

IDT IDTQS3VH16233PA

U11 Single ATM PHY IDT IDT77V107L25PF

U12 IC clock oscillator 32 MHz 100 ppm 3.3 V

ILSI Fox Electronics PletronicsConnor-Winfield

ISM91-3161CO-32.00M F4100-320 SM77H026-32.0MHZ HSM633-32.00M

U13 Advanced ATM Sonet framer ATM155 PHY

NEC uPD98404GJ-KEU

U14 ATM transceiver for SONET OC-3/SDH STM-1

Agilent HFBR-5805

U15 IC clock oscillator 19.44 MHz 20 ppm 3.3 V

Pletronics SM7720HV-19.440MHZ

U16 IC 32-bit transparent D-type latch with 3-state inputs

Texas Instruments SN74LVCH32373AGKER

U19 U38 IC 16-bit bus transceiver with 3-state outputs

IDT IDT74LVCHR162245APA



taped reel)



MPC885ADS Part List

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c..

.

U20 U46 U47 IC advanced CMOS quad buffer low-volt 74LCX125M

Fairchild 74LCX125M

U22 IC PLD 2500 gates MAX 3000 A

Altera EPM3128ATC144-5V

U23 IC reg linear low dropout MIC29501BU fixed

MICREL MIC29501-3.3BU

U24 IC reg linear low dropout MIC29500 3.3 V 5000 mA

Micrel MIC29500-3.3BT

U25 IC reg linear low dropout MIC39151BU fixed

MICREL MIC39151-1.8BU

U26 IC PCMCIA switching matrix with built-in N-Channel VCC switch drivers

Linear Technology LTC1315CG

U27 IC hex inverter Schmitt trigger On Semiconductor CD74AC14M

U28 IC EconoReset with push button DS1818-10 3.3 V 10%

Dallas Semiconductor

DS1818R-10/T&R

U29 IC hex inverter with open-drain outputs

On Semiconductor CD74AC05M

U31 U30 IC Octal buffer/line driver with 3-state outputs

On Semiconductor SN74LS244DW

U32 IC PLD Altera EPM3128ATC100-5V

U33 IC low voltage IEEE 161284 translating tranceiver

Fairchild 74LVX161284MTD

U35 IC low-voltage quad 2:1 mux/demux bus switch

IDT IDT74CBTLV3257PG

U36 IC T1/E1/J1 transceiver DS2155L 3.3 V

Dallas Semiconductor

DS2155L

U37 IC clock oscillator 2.048 MHz 50 ppm 3.3 V

Pletronics SM7745HV-4.000MHZ

U41 U40 IC true RS232 ESD-protected +/–15 KV

Maxim MAX3241ECAI

U42 IC 3.3-V zero delay buffer Cypress Semi. Corp.

CY2309SC-1H

U43 IC fast infrared transceiver module

Vishay TFDU6102-TR3

U44 U45 U50 10/100 Mbps Fast Ethernet transceiver

DAVICOM DM9161E



taped reel)



MPC885ADS Part List

F

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tor,

I


c..

.


ILSI ISM91-3151BO-50MHZ


ILSI ISM91-3151BO-25MHZ

U51 IC universal serial bus transceiver

Philips PDIUSBP11AD

U52 IC surface mount oscillators M-tron M216TCN-48.0000MHZ

U53 PLD Lattice M4A3-192/96-6VC

Y1 Crystal fund 10 MHz 50 ppm ILSI HC49USM-BB1F18-10MHZ



taped reel)



MPC885ADS Part List

F

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I


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.



F

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.

Appendix ARevision HistoryThis appendix provides a list of the major differences between revisions of the MPC885PowerQUICC Application Development System User’s Guide. This history has beenupdated as of Revision 0.03.

A.1 Revision Changes From Revision 0.03 to Revision 1

Major changes are as follows:

Section, Page Changes

Throughout manual The acronym ‘EPIC’ has been changed to ‘PIC’. The following register names have changed: EICR has been changed to ICR EVI has been changed to IVI.

1.5, 1-2 Increased the Frequency

2.3, 2-1 Deleted the bulleted list.

2.4, 2-4 Changed the end of SDRAM to 0X007FFFFF.

3.4.1, 3-6 Deleted the Warning at the top of the page

3-7 Changed the values in Table 3-5.

4-7 Changed the Note

5.1, 5-1 Changed the order in which the connectors were listed

MOTOROLA Appendix A. Revision History A-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE


Revision Changes From Revision 0.03 to Revision 1

F

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.

A-2 MPC885ADS User’s Guide MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE


MOTOROLA Appendix B. MPC885ADS Board Schematics B-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Appendix BMPC885ADS Board Schematics

Fre

esc

ale

Se

mic

on

du

cto

r, I

Freescale Semiconductor, Inc.


nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

NR

Dat

eR

evis

ion

DU

ET A

DS

Boa

rd

Sche

mat

ics

Firs

t Pro

toty

pe R

evis

ion

Rel

ease

Info

rmat

ion

Apr

il 3

2003

SDRA

M, F

LASH

MPC

885

CPU

030201 0604 05 0907 08 1210 11 1513 14 1816 17 2119 20 2422 23 25

BUFF

ERS

MPC

885

CPM

, PW

R, G

ND, I

2C

ATM

25 (8

bit)

ATM

155

(8 b

it)AD

TECH

(8 b

it)PC

MCI

ACo

ntro

l

Pow

erRe

set &

LED

'sHO

ST &

BDM

Inte

rface

T1&E

1Lo

gic

Anal

yzer

Expa

nsio

n Co

nnec

tors

RS23

2, In

fraRe

d, S

ys C

LK10

Base

T E

THER

NET

GPS

IFA

ST E

THER

NET

R/M

II #1

FAST

ETH

ERNE

T R/

MII

#2US

BBC

SRbl

ank

blan

k

CPM

sw

itchi

ng L

OG

IC

NR

June

27

2003

REV

IEW

Rev

isio

n

Revi

sion

His

tory

AA

ugus

t 11

2003

Rev

isio

n A

DU

ET A

DS

A

Rev

isio

n H

isto

ry

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

125

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EDOO

Eb

BS1

BSYS

CLK2

WE0b

SDRA

MEN

VPP

SDRM

CSb

WE1b

DRMW

b

BA01

GPL2

b

SDRAM

WE2b

A10

BS0

(GPL

0b)

WE3b

GPL3

b

FLASH

BA0

For

8M S

DRAM

(fa

ctor

y de

fault)

conn

ect

A10

to

BA0

RJ20 1-2

For

8M S

DRAM

(fa

ctor

y de

faul

t) A8

NOT

conn

ecte

d to

BA0

1 RJ

21 3-2

A8A10

A9

DU

ET A

DS

A

SDR

AM

, FLA

SH

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

225

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

D16

D28

D7

A26

FPD

1

D5

A24

D19

D6

D25

FPD

2

D2

D13

D29

A29

D30

FPD

4

D14

A27

D4

D23

A28

D27

FPD

3

D17

D21

D15

A22

D22

D24

D18

D3

FPD

5

D26

A23

D1

D12

D8

FPD

6

D11

A21

D9

D0

D31

A20

D10

A25

FPD

7

D20

BA29

BA21

BA20

BA25

BA24

BA13

BA19

BA9

BA18

BA11

BA8

BA23

BA16

BA26

BA14

BA10

BA28

BA22

BA12

BA7

BA17

BA15

BA27

BD21

BD0

BD7

BD25

BD11

BD31

BD13

BD10

BD6

BD17

BD9

BD28

BD30

BD3

BD1

BD27

BD26

BD8

BD16

BD19

BD18

BD20

BD4

BD2

BD23

BD29

BD22

BD24

BD15

BD12

BD5

BD14

A[20

:29]

(3,4

,17,

24)

FPD

[1:7

](2

4)

D[0

:31]

(3,4

,17)

BD[0

:31]

(4,1

0,11

,18,

24)

FCS1

b(2

4)

FCS4

b(2

4)

BWE2

b(4

,10)

BA[7

:29]

(4,1

0,11

,18,

24)

BWE1

b(4

,10)

BWE0

b(4

,10,

18)

BWE3

b(4

,10)

FCS2

b(2

4)

FOEb

(24)

FCS3

b(2

4)

WE1

b(3

,4,1

7) BSYS

CLK

2(1

9)

GPL

2b(3

,4,1

7)

WE0

b(3

,4,1

1,17

)

WE3

b(3

,4,1

7) SDR

MC

Sb(3

,17)

OE~

(3,4

,11,

17)G

PL3b

(3,4

,17) SD

RAM

EN(1

4,24

)

WE2

b(3

,4,1

7)

A10

(3,4

,17)

DR

MW

b(3

,4,1

7)

A8(3

,4,1

7)

A9(3

,4,1

7)

A10

(3,4

,17)

V3U

3

V3U

3

VPP

VCC

C18

.01u

FC

20.0

1uF

C22

.01u

F

J2 80 P

in S

IMM

Soc

ket

70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 8 9 10 11 12 13 14 15 16 17 18 19 20 26 27 28

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 24 23 22 21 5 6 29 53 73 74 75 76 77 78 794 7

272 371 1 25 54 80

DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

DQ

16D

Q17

DQ

18D

Q19

DQ

20D

Q21

DQ

22D

Q23

DQ

24D

Q25

DQ

26D

Q27

DQ

28D

Q29

DQ

30D

Q31

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

CE0

CE1

CE2

CE3

WE0

WE1

WE2

WE3

PD1

PD2

PD3

PD4

PD5

PD6

PD7

OE

NC

1

VCC

1VC

C2

VPP1

VPP2

GN

D1

GN

D2

GN

D3

GN

D4

C11

0.1u

F

BA

RJ2

010

K

1

2

3

C13

0.1u

FC

150.

1uF

U1B M

T48L

C2M

32B2

TG-6

1 3

6

912

15 29

32

35

38

43 41

44 46

4955

5258 84

81

8672

75

78

Vdd

VddQ

VssQ

VddQ

VssQ

Vdd

Vdd

VssQ

VddQ

VssQ

Vdd

VddQ

Vss

VssQ

VddQ

VddQ

VssQ

Vss

VssQ

VddQ

Vss

Vss

VddQ

VssQ

C21

0.1u

F

SDRA

M

U1A

MT4

8LC

2M32

B2TG

-6

2 4 75 8 1110 13

1416 17 18 19 2021 22 232425 26 27 28 30

31 33 34 36 37 39 40 42 45 504847 51 53 5654

59 5760 61 62 63 64 65 66 6768 697071

74 79 8276

73

858077 83

DQ

0D

Q1

DQ

3D

Q2

DQ

4

DQ

6D

Q5

DQ

7

NC

6

DQ

M0

WE

CAS

RAS

CS

NC

(A11

)BA

0BA

1

A10(

AP)

A0 A1 A2 DQ

M2

NC

5

DQ

16D

Q17

DQ

18D

Q19

DQ

20D

Q21

DQ

22D

Q23

DQ

24

DQ

27D

Q26

DQ

25

DQ

28D

Q29

DQ

31D

Q30

DQ

M3

NC

4

A3 A4 A5 A6 A7 A8 A9 CKE

CLK

NC

3N

C2

DQ

M1

DQ

8

DQ

11

DQ

13

DQ

9

NC

1

DQ

15

DQ

12

DQ

10

DQ

14

C19

0.1u

F

BA

RJ2

110

K

1

2

3

C12

.01u

F

C4

0.1u

F

C10

.01u

F

C17

0.1u

F

C9

0.1u

F

C14

.01u

F

C5

.01u

F

C16

.01u

F

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GPL4

BbGP

L5Bb

CS6b

SRES

ETb

BS2A

b

ATMR

XCLK

CS5

TRST

b

DSCK

GPL3

b

DRMW

b

TEAb

BS1A

b

TMS

TAb

RPOR

Ib

GPL5

Ab

DSDO

DRMC

S1b

MODC

K1

BCSR

CSb

BGb

RWb

BS0A

b

TSb

IRQ3

b

CS7b

BRb

HRES

ETb

BURS

T

BBb

SDRM

CSb

POEA

RSTC

ONF_

B

BIb

GPL2

b

DRMC

S2b

GPL4

Ab

BS3A

b

IRQ1

bNM

Ib

AS_B

MODC

K2

IRQ2

b

FRZ

IRQ7

b

FCSb

EDOO

E

DSDI

ALEA

BCE1

Ab

EXTA

L

XTALSYSC

LK

CLK4

IN (

EXTC

LK)

TEXP

BCE2

Ab

Place R17 very

close to pin

A5.

CLK4IN traces

should be placed

on outer layers

only.

CLK4IN trace Z should

be 50 ohms.

CLKOUT traces

should be placed

on outer layers

only.

CLKOUT trace Z should

be 50 ohms.

External clock

SMB jack

No Load R17

for on board

oscillator.

IRQ3

/IRQ

7 TA

BLE

R7

ATM/T1

YES

NO

R8

ENET

YES

NO

NO

YES

NO

YES

IRQ3

IRQ3

IRQ3

N/A

NC

IRQ7

IRQ3

N/A

ATM/T1

ENET

No Load R17

for on board

oscillator.

Oscillator socket

CLKOUT

1.8V

NO L

OAD

NO L

OAD

Defa

ult

DU

ET A

DS

A

MPC

885

CPU

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

325

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

AT0

AT3

A23

D2

D0

A3

D26

D16

A28

A26

A22

A8A7

D11

D8

D6

A25

A20

A13

A10

A0

AT2

VF0

D22

A31

A9

D28

D23

D19

D12

D1

D21

A24

A19

D27

D17

D13

A14

A11

A6

VF2

D5

A5

VFLS

0VF

LS1

D15

D9

A12

A4A1

D4

A16

D24

D10

D18

D3

A21

A15

D20

A27

D31

A18

D29

A17

VF1

D30

D25

D14

D7

A30

A29

A2

CLK

4IN

BCE1

Ab(4

,17,

18,2

4)

BCD

2b__

__AT

M_R

XD3_

SW4

(6,1

7,18

)

VFLS

1(1

5,17

)

DSD

I(1

5)

SPKR

OU

T(1

0,17

)

VF0

(17)

AT3

(17)

VF2

(17)

BCD

1b__

__AT

M_R

XD4_

SW4

(6,1

7,18

)

BWP_

___A

TM_R

XD2_

SW4

(6,1

7,18

)

WAI

TBb

(17)

BS0A

b(1

7,18

)

AT2

(17)

SRES

ETb

(15,

17,1

8,24

)

DR

MW

b(2

,4,1

7)

BBVD

1___

_ATM

_RXD

5_SW

4(6

,17,

18)

BIb

(17)

GPL

5Bb

(17,

18)

GPL

3b(2

,4,1

7)

WE0

b(2

,4,1

1,17

)

VF1

(17)

BBb

(17)

D[0

:31]

(2,4

,17)

GPL

2b(2

,4,1

7)

FRZ

(17,

18)

BVS1

____

ATM

_RXD

0_SW

4(6

,17,

18)

BUR

ST(1

7)

WE1

b(2

,4,1

7)

BS2A

b(1

7)

DSD

O(1

5)

BCE2

Ab(4

,17,

18,2

4)

RPO

RIb

(11,

14,1

5,17

,18)

A[0:

31]

(2,4

,17,

24)

GPL

4Bb

(17,

18)

WE2

b(2

,4,1

7)

DSC

K(1

5)

POEA

b(4

,17)

AT1

(17)

WE3

b(2

,4,1

7)

BWAI

TAb_

___A

TM_R

XSO

C_S

W4

(6,1

7,18

)

RST

CN

Fb(1

7,24

)

BS3A

b(1

7)

VFLS

0(1

5,17

)

GPL

4Ab

(17,

18)

BRES

ETA_

___A

TM_R

XCLK

_SW

4(6

,9,1

7,18

)

BS1A

b(1

7)

TAb

(11,

17,1

8,24

)

AT0

(17)

BGb

(17)

IRQ

7b(1

7,18

)

BBVD

2___

_ATM

_RXD

6_SW

4(6

,17,

18)

BVS2

____

ATM

_RXD

1_SW

4(6

,17,

18)

GPL

5Ab

(17,

18)

BRD

Y___

_ATM

_RXD

7_SW

4(6

,17,

18)

BRb

(17)

R/M

IICR

S-1

(17,

21)

R/M

IICO

L-1

(17,

21)

TEXP

(17)

IRQ

3b_I

RQ

7b(2

0,21

,22)

IRQ

3b(7

,8,1

6,17

,18)

TEAb

(4,1

7)

ALEA

(4,1

7)

OE~

(2,4

,11,

17)

HR

ESET

b(1

1,15

,17,

18,2

4)

TSb

(4,1

1,17

)

SYSC

LK(1

9)

EXTC

LK(1

7)

FCSb

(17,

24)

MO

DC

K1(1

7,24

)

IRQ

1b(1

7,18

)

CS7

b(1

7,18

,24)

RW

b(4

,11,

17,1

8)

IRQ

2b(1

7,18

)

MO

DC

K2(1

7,24

)

DR

MC

S2b

(17,

24)

CS6

b(1

7,18

,24)

BCSR

CSb

(17,

24)

CS5

b(1

1,17

,24)

DR

MC

S1b

(17,

24)

SDR

MC

Sb(2

,17)

NM

Ib(1

7,18

,24)

MPC

MD

IO(1

7,18

,20,

21,2

2)R

/MIIT

XEN

-1(1

7,21

)

SW_M

OD

CK1

(18,

24)

REG

Ab(1

0,17

)TS

IZ1

(17)

V3U

3

V3U

3V3

U3

V3U

3

V3U

3

V3U

3

V1U

8

V3U

3

V3U

3

V3U

3

V3U

3 R28

110

.0K

R10

10.0

K

Y1 10.0

00M

Hz

50pp

m@

25C

12

TP6 1

R27

010

.0K

RN

108x

10K 1

2346789

105

U2E

74LC

X08

714

GN

DVC

C

R25

8

22

DIP

8

J5 SOC

KET

for O

SC1 4

8 5

NC

GN

D

VCC

OU

T

R15

0

R27

110

.0K

C31

0.1u

F

R5

2.21

K

C37

118

pFC

0G

R26

410

M

R26

3

1.00

K

TP3

J3A

DU

ETPB

GA3

57IC

Soc

ket

M16

N18

N19

M19

M17

M18 L16

L19

L17

L18

K19

K18

K17

K16

J19

J17

J18

J16

E19

H18

H17

G19 F17

G17

H16 F19

D19

H19 E18

G18 F18

D18 P2 M

1 L1 K2 N1 K4 H3 F2 P1 L4 L3 L2 N3

N2 K3 K1 J2 M4 J1 J3 H2

H1 J4 M3

G2

G1

G3

M2

H4 F1 E1 F3 B8 A8 A10 B9 C9

C8

D9 A9 C7 A2 B1 C1 F4 E3 D2

D1 E2 D3

C5 B5 A7

B18

E16

C17

B19

C3

D8

E17

G16

D6

A6 D13

B14

C14

A15

D14

C16

A16

D15

B16

N4

P3 B10

A11

D10

P4 B13

C13

B17

A18

D16

A17

A14

A13

B11

C11

D11

A12

C12

B12

D7

D12

C10

U17

V18

T16

T17

W18

D17

C18

C19

F16

B7 B15

C15

B6 C6

A3 B4 B3 D4

E4 C2

B2 C4

A5

G4

A4 D5

T11

P19

T5 U12

R16

N17

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

IPB7

_PTR

_AT3

IPB6

_DSD

I_AT

0IP

B5_L

WP1

_VF1

IPB4

_LW

P0_V

F0IP

B3_L

WP2

_VF2

IPB2

_IO

IS16

B_B_

AT2

IPB1

_IW

P1_V

FLS1

IPB0

_IW

P0_V

FLS0

KR_B

_IR

Q4_

B

WAI

TA_B

IPA0

IPA1

IPA2

_IO

IS16

A_B

IPA3

IPA4

IPA5

IPA6

IPA7

BAD

DR

28BA

DD

R29

BAD

DR

30

WE0

_B_B

SB0_

B_IO

RD

_BW

E1_B

_BSB

1_B_

IOW

R_B

WE2

_B_B

SB2_

B_PC

OE_

BW

E3_B

_BSB

3_B_

PCW

E_B

WAI

TB_B

ALEB

_DSC

K_AT

1

TSIZ

1TS

IZ0_

REG

_B

OP2

_MO

DC

K1_S

TS_B

OP3

_MO

DC

K2_D

SDO

WR

_BC

S0_B

CS1

_BC

S2_B

CS3

_BC

S4_B

CS5

_BC

S6_C

E1B_

BC

S7_B

_CE2

B_B

IRQ

0_B

IRQ

1_B

RSV

_B_I

RQ

2_B

CR

_B_I

RQ

3_B

FRZ_

B_IR

Q6_

BIR

Q7_

B

GPL

A4_B

GPL

A5_B

GPL

A0_B

_GPL

B0_B

OE_

B_G

PLAB

1_B

GPL

AB2_

B_C

S2_B

GPL

AB3_

B_C

S3_B

GPL

B4_B

BDIP

_B_G

PLB5

_BBB

_BBG

_BBR

_BTS

_BTA

_BTE

A_B

AS_B

BI_B

BUR

ST_B

TCK/

DSC

KTM

STD

I/DSD

ITD

O/D

SDO

TRST

_B

BSA0

_BBS

A1_B

BSA2

_BBS

A3_B

ALEA

CE1

A_B

CE2

A_B

OP0

OP1

SRES

ET_B

HR

ESET

_BPO

RES

ET_B

RST

CO

NF_

B

GN

DSY

NG

ND

SYN

1

VDD

LSYN

TEXP

CLK

4IN

CLK

OU

T

XTAL

EXTA

L

SPAR

E1SP

ARE2

SPAR

E3SP

ARE4

TEST

_MO

DE

NC

RP1 4x

22

1 2 3 45678

TP21

R9

22

TP7 1

R25

7

301

U2A

74LC

X08

1 23

TP1

R28

21.

00K

R26

5

10.0

K

TP2

C25

.01u

F

U2B

74LC

X08

4 56

R25

9

0

C30

0.1u

F

TP4

L1 8200

uH50

mA

10%

12

R14 0

U2C

74LC

X08

10 98

R12

1.00

K

R8

0

C29

.01u

F

CTR

GND

GND

GND

2211

11-1GN

D

J6

SMB

Jack

Ver

tical2 1 3

54

C37

018

pFC

0G

R16

0

R6

2.21

K

R7

0

U2D

74LC

X08

13 1211

+C

2310

uF16

V

RN

98x

10K

12346789

105

R17

49.9

C24

0.1u

F

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BCSR

BCSR

Flas

h/PC

MCIA

Flas

h/PC

MCIA

Flas

h/PC

MCIA

Flas

h/PC

MCIA

5-Volt tolerant I/O

5-Volt tolerant I/O

5-Volt tolerant I/O

5-Volt tolerant I/O

5-Volt tolerant I/O

EDOO

EAL

EAOP

1

BCSR

SDRA

M

BCSR

DU

ET A

DS

A

BU

FFER

S

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

425

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

D2

BD19

BD7

D3

BD5

D30

D16

BD8

BD6

BD3

BD0

BD9

D4

D5

BD12

D31

BD21

D21

D6

BD11

BD14

BD29

D20

BD15

BD18

D27

BD31

BD13

D7

BD30

BD10

D10

D9

D25

D22

D12

D23

BD27

BD22

D24

BD23

D15

D13

D18

BD16

BD26

D11

D14

D8

D26

D29

BD20

BD2

D28

D19

BD24

BD1

D0

BD25

BD28

D17

BD17

BD4

D1

A23

A24

A25

A22

A11

A17

A26

A30

A21

A27

A15

A20

A19

A8

A28

A10

A31

A13

A29

A12

A18

A9

A16

A14

BA14

BA10

BA9

BA15

BA13

BA8

BA11

BA12

BA26

BA30

BA24

BA31

BA17

BA20

BA22

BA19

BA16

BA21

BA28

BA25

BA29

BA18

BA27

BA23

A6 A7BA

6BA

7

D[0

:31]

(2,3

,17)

A[6:

31]

(2,3

,17,

24)

BD[0

:31]

(2,1

0,11

,18,

24)

WE2

b(2

,3,1

7)

UBU

FEN

b(2

4)

GPL

3b(2

,3,1

7)

WE0

b(2

,3,1

1,17

)

WE3

b(2

,3,1

7)

LBU

FEN

b(2

4)

WE1

b(2

,3,1

7)

GPL

2b(2

,3,1

7)

BWE2

b(2

,10)

BWE0

b(2

,10,

18)

BWE3

b(2

,10)

BWE1

b(2

,10)

BGPL

3b(1

8)BG

PL2b

(18)

BED

OO

Eb(1

8)BA

LEA

(10,

18)

BPO

EAb

(10)

POEA

b(3

,17)

ALEA

(3,1

7)O

E~(2

,3,1

1,17

)

TSb

(3,1

1,17

)TE

Ab(3

,17)

DR

MW

b(2

,3,1

7)

RW

b(3

,11,

17,1

8)

BRW

2b(1

8,24

)

BDR

MW

b(1

8)

BTSb

(18)

BTE

Ab(2

4)

BA[6

:31]

(2,1

0,11

,18,

24)

BCE1

Ab(3

,17,

18,2

4)BC

E2Ab

(3,1

7,18

,24)

PBC

E1Ab

(10)

PBC

E2Ab

(10)

V3U

3

V3U

3V3

U3

V3U

3

V3U

3

V3U

3

V3U

3

C56

0.1u

F

TP19

RP1

44x

0 oh

m1 2 3 4

5678

TP17

RP4

4x0

ohm

1 2 3 45678

U3A

74LV

C32

245

A2 A1 B2 B1 C2

C1

D2

D1 E2 E1 F2 F1 G2

G1

H1

H2

A5 A6 B5 B6 C5

C6

D5

D6

E5 E6 F5 F6 G5

G6

H6

H5

A3 H3

A4 H4

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

DIR

1

DIR

2

OE1

OE2

TP18

R18

1.00

K

U4C

74LV

C32

244

B3 B4 D3

D4

E3 E4 G3

G4

C3

C4 F3 F4

K3 K4 M3

M4

N3

N4

R3

R4

L3 L4 P3 P4

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

C42

0.1u

FC

440.

1uF

U3B

74LV

C32

245

J2 J1 K2 K1 L2 L1 M2

M1

N2

N1 P2 P1 R2

R1 T1 T2

J5 J6 K5 K6 L5 L6 M5

M6

N5

N6

P5 P6 R5

R6

T6 T5J3 T3J4 T4

3B1

3B2

3B3

3B4

3B5

3B6

3B7

3B8

4B1

4B2

4B3

4B4

4B5

4B6

4B7

4B8

3A1

3A2

3A3

3A4

3A5

3A6

3A7

3A8

4A1

4A2

4A3

4A4

4A5

4A6

4A7

4A8

DIR

3

DIR

4

OE3

OE4

C38

0.1u

F

C47

0.1u

F

U4A

74LV

C32

244

A5 A6 B5 B6 C5

C6

D5

D6 A3 A4

A2 A1 B2 B1 C2

C1

D2

D1

E5 E6 F5 F6 G5

G6

H6

H5

H4

H3

E2 E1 F2 F1 G2

G1

H1

H2

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1OE

2OE

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

3A1

3A2

3A3

3A4

4A1

4A2

4A3

4A4

3OE

4OE

3Y1

3Y2

3Y3

3Y4

4Y1

4Y2

4Y3

4Y4

RP7

4x0

ohm

1 2 3 45678

C50

0.1u

F

R21

1.00

K

C54

0.1u

F

C41

0.1u

F

RP8

4x0

ohm

1 2 3 45678

RP1

54x

0 oh

m

1 2 3 45678

C46

0.1u

FC

530.

1uF

C39

0.1u

F

U3C

74LV

C32

245

B3 B4 D3

D4

E3 E4 G3

G4

C3

C4 F3 F4

K3 K4 M3

M4

N3

N4

R3

R4

L3 L4 P3 P4

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

C52

0.1u

F

RP3

4x0

ohm

1 2 3 45678

TP16

RP1

64x

0 oh

m1 2 3 4

5678

C48

0.1u

F

C35

0.1u

FC

400.

1uF

U6A

74LV

CH

1622

44

47 46 44 43 141 40 38 37 48 36 35 33 32 2530 29 27 26 24

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

1A0

1A1

1A2

1A3

OE1

2A0

2A1

2A2

2A3

OE2

3A0

3A1

3A2

3A3

OE3

4A0

4A1

4A2

4A3

OE4

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

3Y0

3Y1

3Y2

3Y3

4Y0

4Y1

4Y2

4Y3

C45

0.1u

FC

510.

1uF

C36

0.1u

F

R20

1.00

K

RP1

14x

0 oh

m

1 2 3 45678

C49

0.1u

F

C43

0.1u

F

U4B

74LV

C32

244

J5 J6 K5 K6 L5 L6 M5

M6 J3 J4

J2 J1 K2 K1 L2 L1 M2

M1

N5

N6 P5 P6 R5

R6 T6 T5 T4 T3

N2

N1

P2 P1 R2

R1

T1 T2

5A1

5A2

5A3

5A4

6A1

6A2

6A3

6A4

5OE

6OE

5Y1

5Y2

5Y3

5Y4

6Y1

6Y2

6Y3

6Y4

7A1

7A2

7A3

7A4

8A1

8A2

8A3

8A4

7OE

8OE

7Y1

7Y2

7Y3

7Y4

8Y1

8Y2

8Y3

8Y4

C37

0.1u

F

RP1

04x

0 oh

m1 2 3 4

5678

U6B

74LV

CH

1622

44

4 10 15 21 28 34 39 45

7 18 31 42

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

RP5

4x0

ohm

1 2 3 45678

C33

0.1u

F

C55

0.1u

F

C34

0.1u

F

RP1

34x

0 oh

m

1 2 3 45678

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

J3 decoupling capacitors

1.8V VDDL decoupling capacitors

place C57, C58, C59, C160, C61, C62 very near the VDDL

pins/plane

R/MI

I-RX

D0-1

mii1

-RMI

I1-R

XD0=

MII_

MDC

l1a-

L1TC

LKA

ETHR

CK-1

0bt

ETHT

CK-1

0bit

l1a-

L1RC

LKA

ETHT

X-10

btl1

a-L1

RXDA

l1a-

L1TX

DAET

HRX-

10bt

MII1

-TXE

RR

IRDT

XDIR

DRXD

USBO

EUS

BRXD

utp-

RXAD

DR[2

]ut

p-TX

ADDR

[2]

- sl

ave

utp-

RXCL

AV -

sla

veut

p-TX

CLAV

mii1

-RMI

I1-T

XD0,

MII

1-TXD0

utp-

RXAD

DR[0

]ut

p-TX

ADDR

[0]

- sl

ave

utp-

RXAD

DR[1

]ut

p-TX

ADDR

[1]

- sl

ave

utp-

RXAD

DR[4

]ut

p-TX

ADDR

[4]

- sl

ave

MII1

-RXD

3ut

p-TX

ADDR

[0]

utp-

RXAD

DR[0

] -

slave

utp-

TXAD

DR[1

]ut

p-RX

ADDR

[1]

- sl

ave

utp-

TXAD

DR[4

]ut

p-RX

ADDR

[4]

- sl

ave

utp-

TXAD

DR[2

]ut

p-RX

ADDR

[2]

- sl

ave

utp-

TXAD

DR[3

]ut

p-RX

ADDR

[3]

- sl

ave

utp-

RXAD

DR[3

]ut

p-TX

ADDR

[3]

- sl

ave

I2CS

CLI2

CSDA

SPIM

ISO

SPIM

OSI

SPIC

LKmi

i1-R

MII1

-REF

CLKMI

I1-T

XCLK

l1a-

L1RS

YNCA

EREN

A-10

btl1

a-L1

TSYN

CAEC

LSN-

10bt

USBT

XNUS

BTXP

USBR

XNUS

BRXP

MII1

-TXD

2MI

I1-T

XD3

utp-

RXCL

AVut

p-TX

CLAV

- s

lave?

ATMT

XSOC

ATMT

XD7

ATMT

XD6

ATMT

XD5

ATMT

XD4

ATMT

XCLK

ATMT

XENB

ATMR

XENB

ATMT

XD3

ATMT

XD2

ATMT

XD1

ATMT

XD0

mii2

-RMI

I2-T

XD0,

MII

2-TXD0

mii2

-RMI

I2-T

XD1,

MII

2-TXD1

mii2

-RMI

I2-R

EF_CLK

MII2

-TXC

LKMI

I2-T

XD2

MII2

-TXD

3mi

i2-R

MII2

-TXE

N, M

II2-

TXEN

MII2

-TXE

RRmi

i2-R

MII2

-RXD

0, M

II2-

RXD0

mii2

-RMI

I2-R

XD1,

MII

2-RXD1

MII2

-RXC

LKRS

DTR2

bMI

I2-R

XD2

MII2

-RXD

3mi

i2-R

MII2

-CRS

_DV,

MII

2-RXDV

mii2

-RMI

I2-R

XERR

, MI

I2-RXERR

ETEN

A-10

btMI

I2-C

OLMI

I2-C

RSMI

I1-R

XD2

MII1

-RXC

LK

PA7

PC4

PA8

PC5

PA9

I2C

off-board

connections

DU

ET A

DS

A

MPC

885

CPM

, PW

R, G

ND

, I2C

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

525

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

PE21

PE23

PE20

I2C

SDA

I2C

CSL

R/M

IIRXD

1-1

(17,

18,2

1)

R/M

IIRXD

V-1

(17,

18,2

1)R

/MIIR

XD0-

1(1

7,18

,21)

R/M

IIRXE

RR

-1(1

7,18

,21)

R/M

IITXD

1-1

(17,

18,2

1)

nUSB

OE

(17,

18,2

3)

USB

TXP

(17,

18,2

3)

USB

RXD

(6,1

7,18

)

USB

TXN

(17,

18,2

3)

USB

RXP

(6,1

7,18

)U

SBR

XN(6

,17,

18)

R/M

IIRXD

3-2

(17,

18,2

2)R

/MIIR

XD2-

2(1

7,18

,22)

R/M

IIRXD

1-2

(17,

18,2

2)

R/M

IICO

L-2

(17,

18,2

2)R

/MIIC

RS-

2(1

7,18

,22)

R/M

IITXE

N-2

(17,

18,2

2)

R/M

IITXD

1-2

(17,

18,2

2)R

/MIIT

XD0-

2(1

7,18

,22)

CLK

5(6

,17,

18)

R/M

IITXD

3-2

(17,

18,2

2)

MPC

MD

C(1

7,18

,20,

21,2

2)

R/M

IIRXC

LK-1

(17,

18,2

1)

R/M

IITXE

RR

-1(1

7,18

,21)

R/M

IITXD

3-1

(17,

18,2

1)R

/MIIT

XD2-

1(1

7,18

,21)

R/M

IITXD

0-1

(17,

18,2

1)

R/M

IITXC

LK-1

(17,

18,2

1)

R/M

IIRXD

3-1

(17,

18,2

1)

R/M

IIRXD

2-1

(17,

18,2

1)

R/M

IIRXE

RR

-2__

__ET

HTX

EN_S

W3

(6,1

7,18

)

R/M

IIRXC

LK-2

____

RSD

TR2b

_SW

2(6

,17,

18)

R/M

IITXE

RR

-2__

__R

STXD

2_SW

2(6

,17,

18)

RST

XD1_

___A

TM_R

XAD

DR

3_SW

1(6

,17,

18)R

SDTR

1b__

__AT

M_T

XAD

DR

2_SW

1(6

,17,

18)

RSR

XD1_

___A

TM_T

XAD

DR

3_SW

1(6

,17,

18)

R/M

IIRXD

0-2_

___R

SRXD

2_SW

2(6

,17,

18)

ATM

_TXC

LAV

(6,1

7,18

)

ATM

_TXD

7(7

,8,9

,17,

18)

ATM

_TXD

6(7

,8,9

,17,

18)

ATM

_TXD

5(7

,8,9

,17,

18)

ATM

_TXD

4(7

,8,9

,17,

18)

ATM

_TXD

0(7

,8,9

,17,

18)

ATM

_TXD

1(7

,8,9

,17,

18)

ATM

_TXD

3(7

,8,9

,17,

18)

ATM

_TXD

2(7

,8,9

,17,

18)

ATM

_RXA

DD

R0

(7,8

,9,1

7,18

)AT

M_R

XAD

DR

1(7

,8,9

,17,

18)

ATM

_TXE

N(7

,8,9

,17,

18)

ATM

_RXE

N(7

,8,9

,17,

18)

ATM

_TXS

OC

(7,8

,9,1

7,18

)

ATM

_RXC

LAV

(6,1

0,17

,18)

ATM

_TXA

DD

R1

(7,8

,9,1

7,18

)AT

M_T

XAD

DR

0(7

,8,9

,17,

18)

ATM

_TXA

DD

R4

(7,8

,9,1

7,18

)

ATM

_RXA

DD

R2

(7,8

,9,1

7,18

)

ATM

_RXA

DD

R4

(7,8

,9,1

7,18

)

T1_L

1RC

LKA_

___E

THTX

CK_

SW3

(16,

17,1

8)

T1_L

1RSY

NC

A___

_ETH

CR

S_SW

3(6

,17,

18)

T1_L

1RXD

A___

_ETH

TXD

_SW

3(6

,17,

18)

T1_L

1TSY

NC

A___

_ETH

CO

L_SW

3(6

,17,

18)

T1_L

1TXD

A___

_ETH

RXD

_SW

3(6

,17,

18)

T1_L

1TC

LKA

(16,

17,1

8)

R/M

IIRXD

V-2

(17,

18,2

2)

PC8

(14,

17,1

8)PC

9(1

4,17

,18)

PC14

(14,

17,1

8)

IRD

TXD

(17,

18,1

9)IR

DR

XD(6

,17,

18)

PB26

(17,

18)

PB27

(17,

18)

PB28

(14,

17,1

8)PB

29(1

4,17

,18)

PB30

(17,

18)

CLK

2(1

7,18

,23)

CLK

6(6

,17,

18)

ATM

_TXC

LK(9

,17,

18)

CH

INSb

(14,

15)

V1U

8V3U

3_VD

DH

V3U

3_VD

DH

V3U

3_VD

DH

V3U

3_VD

DH

V3U

3

V1U

8V1

U8

V1U

8V1

U8

V1U

8V1

U8

C73

0.1u

F

R23

22

C74

0.1u

F

C82

0.1u

F

C69

0.1u

F

C80

0.1u

F

C70

0.1u

FC

670.

1uF

J3C

DU

ETPB

GA3

57So

cket

IC

G6

G7

G8

G9

G10

G11

G12

G13

H7

H8

H9

H10

H11

H12

H13

H14

J7 J8 J9 J10

J11

J12

J13

K7 K8 K9 K10

K11

K12

K13

L7 L8 L9 L10

L11

L12

L13

M7

M8

M9

M10

M11

M12

M13

N7

N8

N9

N10

N11

N12

N13

N14

P7 P13

E7 E8 E10

E12

E13

E15 F5 F6 F7 F8 F9 F10

F11

F12

F13

F14

F15

G5

G14 H

6H

15 J6 J14 K5 K6 K14 L6 L14

L15

M5

M6

M14 N

6N

15 P5 P6 P8 P9 P10

P11

P12

P14

P15

R5

R7

R8

R11

R13

R14 E5 E6 E9 E11

E14

G15 H

5 J5 J15

K15 L5

M15 N

5R

6R

9R

10R

12R

15

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

HVD

DH

VDD

H

VDD

LVD

DL

VDD

LVD

DL

VDD

LVD

DL

VDD

LVD

DL

VDD

LVD

DL

VDD

LVD

DL

VDD

LVD

DL

VDD

LVD

DL

VDD

LVD

DL

+C

6610

uF16

V

C72

0.1u

FC

680.

1uF

C79

0.1u

F

C60

0.1u

F

C75

0.1u

FC

780.

1uF

+C

6310

uF16

V

C59

0.1u

F

C76

0.1u

F

C57

0.1u

F

R26

610

.0K

+C

6410

uF16

V

J3B

DU

ETPB

GA3

57So

cket

IC

U3

U1 T4 W2

U4

W13

U13 V14

W15 T1

5W

17 W9

P16

W11 P1

7N

16

U18

U10 V11

W12 T1

2V1

3T1

3U

14 V15

W16

U16 V17

R17

U19 V19

T19

P18 V3

W10

T10

U11

V12

W14

T14

U15

V16

T18

V10

R18

R19

V7 W6

T7 W8

R1

T6 R4

V9 V1 V2 V8 T3 T1 V4 V5 T8 W7

U9

W3

R3

U2

T2 R2

U5

U6

U7

U8

W4

W5

V6T9

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PB14

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

PB24

PB25

PB26

PB27

PB28

PB29

PB30

PB31

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PE14

PE15

PE16

PE17

PE18

PE19

PE20

PE21

PE22

PE23

PE24

PE25

PE26

PE27

PE28

PE29

PE30

PE31

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PD4

PD6

PD5

PD3

C61

0.1u

FC

580.

1uF

C62

0.1u

F

C81

0.1u

F

C71

0.1u

F

J7 1x3

Hea

der

0.1

CTR

123

+C

6510

uF16

V

C77

0.1u

F

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ETH

TCK

RST

XD2

PC4

RST

XD1

EREN

A

L1R

SYN

CA

10BT

/TD

MA

& M

II2

L1R

XDA

PA8

RXA

DD

R3

MII2

_RXC

LK

TXAD

DR

2

RSR

XD1

PE21

PE20

RSD

TR1

L1TX

DA

MII2

_TXE

RR

L1TS

YNC

A

ETH

TX

PB25

232-

2/M

II2

PE23

PB23

MII2

_RXD

0

ETH

RX

RSD

TR2

RSR

XD2

ECLS

N

PA9

TXAD

DR

3

ADTE

CH

(hi-p

hy >

4)/2

32-1

PC5PB

24

Switch 1

Switch 2

Switch 3

MII_

RXE

RR

-2

ETH

TXEN

Switch 5

E2D1D2E3F4C1B1

UTO

PIA/

PCM

CIA

Switch 4

B6 A2D3

SEL1 low = A to B1

SEL1 high = A to B2

SEL2 low = A to B1

SEL2 high = A to B2

SEL1 low = A to B1

SEL1 high = A to B2

SEL2 high = A to B2

SEL2 low = A to B1

SEL1 high = A to B2

SEL1 low = A to B1

NO LOAD

SEL2 low = A to B1

SEL2 high = A to B2

DU

ET A

DS

A

CPM

sw

itchi

ng L

OG

IC

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

625

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

IAP0

IAP3

IAP1

IAP7

IAP6

IAP4

WAI

TA_B

IAP5

IAP2

OP0

SW1_

ATM

_TXA

DD

R3

(7,8

,9)

SW1_

ATM

_RXA

DD

R3

(7,8

,9)

Switc

h_2

(11)

Switc

h_1

(11)

Switc

h_3

(11)

SW1_

ATM

_TXA

DD

R2

(7,8

,9)

SW1_

RSD

TR1b

(19)

R/M

IITXE

RR

-2__

__R

STXD

2_SW

2(5

,17,

18)

SW2_

RST

XD2

(19)

T1_L

1TXD

A___

_ETH

RXD

_SW

3(5

,17,

18)

SW3_

T1_L

1TXD

A(1

6)

T1_L

1RSY

NC

A___

_ETH

CR

S_SW

3(5

,17,

18)

T1_L

1RXD

A___

_ETH

TXD

_SW

3(5

,17,

18)

SW1_

RST

XD1

(19)

T1_L

1TSY

NC

A___

_ETH

CO

L_SW

3(5

,17,

18)

SW3_

ETH

CO

L(2

0)

SW1_

RSR

XD1

(19)

SW3_

ETH

RXD

0(2

0)

SW3_

ETH

CR

S(2

0)

SW2_

RSR

XD2

(19)

SW3_

T1_L

1RXD

A(1

6)

SW3_

ETH

TXD

(20)

SW2_

R/M

IITXE

RR

-2(2

2)SW

2_R

/MIIR

XCLK

-2(2

2)

SW3_

T1_L

1RSY

NC

A(1

6)

SW2_

RSD

TR2b

(19)

SW2_

R/M

IIRXD

0-2

(22)

R/M

IIRXD

0-2_

___R

SRXD

2_SW

2(5

,17,

18)R

/MIIR

XCLK

-2__

__R

SDTR

2b_S

W2

(5,1

7,18

)

RST

XD1_

___A

TM_R

XAD

DR

3_SW

1(5

,17,

18)R

SRXD

1___

_ATM

_TXA

DD

R3_

SW1

(5,1

7,18

) RSD

TR1b

____

ATM

_TXA

DD

R2_

SW1

(5,1

7,18

)

SW3_

T1_L

1TSY

NC

A(1

6)

SW3_

R/M

IIRXE

RR

-2(2

2)

SW3_

ETH

TXE

N(2

0)

R/M

IIRXE

RR

-2__

__ET

HTX

EN_S

W3

(5,1

7,18

)

BWAI

TAb_

___A

TM_R

XSO

C_S

W4

(3,1

7,18

)

SW4_

BRES

ETA

(10)

Switc

h_4

(11)

SW4_

ATM

_RXS

OC

(7,8

,9)

BRES

ETA_

___A

TM_R

XCLK

_SW

4(3

,9,1

7,18

)

SW4_

BWAI

TAb

(10)

CLK

6(5

,17,

18)

CLK

5(5

,17,

18)

SW3_

R/M

IITXC

LK-2

(22)

SW3_

ETH

RXC

K(2

0)

SW3_

R/M

IITXD

2-2

(22)

SW3_

ETH

TXC

K(2

0)

SW4_

BVS1

(10)

SW4_

BVS2

(10)

SW4_

BWP

(10)

SW4_

BCD

2b(1

0)SW

4_BC

D1b

(10)

SW4_

BBVD

2(1

0)SW

4_BB

VD1

(10)

SW4_

BRD

Y(1

0)

SW4_

ATM

_RXD

7(7

,8,9

)SW

4_AT

M_R

XD6

(7,8

,9)

SW4_

ATM

_RXD

3(7

,8,9

)SW

4_AT

M_R

XD4

(7,8

,9)

SW4_

ATM

_RXD

2(7

,8,9

)

SW4_

ATM

_RXD

5(7

,8,9

)

SW4_

ATM

_RXD

0(7

,8,9

)SW

4_AT

M_R

XD1

(7,8

,9)

BVS1

____

ATM

_RXD

0_SW

4(3

,17,

18)

BVS2

____

ATM

_RXD

1_SW

4(3

,17,

18) BC

D2b

____

ATM

_RXD

3_SW

4(3

,17,

18)

BWP_

___A

TM_R

XD2_

SW4

(3,1

7,18

) BBVD

1___

_ATM

_RXD

5_SW

4(3

,17,

18)

BCD

1b__

__AT

M_R

XD4_

SW4

(3,1

7,18

)

BRD

Y___

_ATM

_RXD

7_SW

4(3

,17,

18)BB

VD2_

___A

TM_R

XD6_

SW4

(3,1

7,18

)

ATM

_RXC

LAV

(5,1

0,17

,18)

ATM

_TXC

LAV

(5,1

7,18

)

SW4_

ATM

_TXC

LAV

(7,8

,9)

SW4_

ATM

_RXC

LAV

(7,8

,9)

USB

RXD

(5,1

7,18

)

USB

RXN

(5,1

7,18

)U

SBR

XP(5

,17,

18)

IRD

RXD

(5,1

7,18

)

SW5_

USB

RXD

(23)

SW5_

USB

RXP

(23)

SW5_

USB

RXN

(23)

SW5_

IRD

RXD

(19)

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

TP89

TP80

U8C

IDTQ

S3VH

1623

3

4344 13

14VC

CG

ND

GN

DVC

C

TP97

TP81

C87

0.1u

F

U8B

IDTQ

S3VH

1623

3

28

22 2342 4116 1739 3819 2036 35

29 15 40 18 37 21 34 24 31

33 3225 26

TEST

2

14B1

14B29B

1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

13B1

13B2

SEL2

9A 10A

11A

12A

13A

14A

15A

16A

15B1

15B2

16B1

16B2

U9A

IDTQ

S3VH

1623

3

27

8 956 552 353 525 650 49

30 1 54 4 51 7 48 10 45

47 4611 12

TEST

1

6B1

6B2

1B1

1B2

2B1

2B2

3B1

3B2

4B1

4B2

5B1

5B2

SEL1

1A 2A 3A 4A 5A 6A 7A 8A

7B1

7B2

8B1

8B2

TP96

C86

0.1u

F

U9B

IDTQ

S3VH

1623

3

28

22 2342 4116 1739 3819 2036 35

29 15 40 18 37 21 34 24 31

33 3225 26

TEST

2

14B1

14B29B

1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

13B1

13B2

SEL2

9A 10A

11A

12A

13A

14A

15A

16A

15B1

15B2

16B1

16B2

U10

AID

TQS3

VH16

233

27

8 956 552 353 525 650 49

30 1 54 4 51 7 48 10 45

47 4611 12

TEST

1

6B1

6B2

1B1

1B2

2B1

2B2

3B1

3B2

4B1

4B2

5B1

5B2

SEL1

1A 2A 3A 4A 5A 6A 7A 8A

7B1

7B2

8B1

8B2

C88

0.1u

F

R28

3

10.0

K

R28

510

.0K

U10

CID

TQS3

VH16

233

4344 13

14VC

CG

ND

GN

DVC

C

R28

610

.0K

C83

0.1u

F

TP94

U8A

IDTQ

S3VH

1623

3

27

8 956 552 353 525 650 49

30 1 54 4 51 7 48 10 45

47 4611 12

TEST

1

6B1

6B2

1B1

1B2

2B1

2B2

3B1

3B2

4B1

4B2

5B1

5B2

SEL1

1A 2A 3A 4A 5A 6A 7A 8A

7B1

7B2

8B1

8B2

TP78

C84

0.1u

F

TP86

R28

410

.0K

U10

BID

TQS3

VH16

233

28

22 2342 4116 1739 3819 2036 35

29 15 40 18 37 21 34 24 31

33 3225 26

TEST

2

14B1

14B29B

1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

13B1

13B2

SEL2

9A 10A

11A

12A

13A

14A

15A

16A

15B1

15B2

16B1

16B2

R29

310

.0K

TP87

TP88

TP79

TP95

U9C

IDTQ

S3VH

1623

3

4344 13

14VC

CG

ND

GN

DVC

C

C85

0.1u

F

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

See User Manual for Layout Rules

1. Traces between 98408 and PE-67583 should be short

2. Traces between PE-67583 and RJ-45 should be short

3. Add surface ground fill between TX and RX pairs

4. No power and ground planes under transformer and RJ-45

plan

epl

ane

TxLE

D

add

this

tex

t to

sil

kscreen

add

this

tex

t to

sil

kscreen

RxLE

D

FID

UC

IALS

FOR

U11

DU

ET A

DS

A

ATM

25

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

725

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

AD4

AD2

AD1

AD5

AD3

AD0

AD6

RES

ET~

RD

~C

S~

WR

~

AD7

ALE

INT~

V3U

3_AT

M25

AVD

D_A

TM25

ATM

_TXD

1(5

,8,9

,17,

18)

ATM

_TXD

2(5

,8,9

,17,

18)

ATM

_TXD

4(5

,8,9

,17,

18)

ATM

_TXD

0(5

,8,9

,17,

18)

ATM

_TXD

7(5

,8,9

,17,

18)

ATM

_TXD

6(5

,8,9

,17,

18)

ATM

_TXD

3(5

,8,9

,17,

18)

ATM

_TXD

5(5

,8,9

,17,

18)

ATM

_TXE

N(5

,8,9

,17,

18)

ATM

_TXC

LK_A

TM25

(9)

ATM

_TXS

OC

(5,8

,9,1

7,18

)

ATM

_RXE

N(5

,8,9

,17,

18)

ATM

_RXC

LK_A

TM25

(9)

RST

_25B

(11)R

D_A

TM25

B(1

1)C

S_AT

M25

B(1

1)

WR

_ATM

25B

(11)

ALE_

ATM

25(1

1)

ATM

_RXA

DD

R1

(5,8

,9,1

7,18

)AT

M_R

XAD

DR

0(5

,8,9

,17,

18)

ATM

_TXA

DD

R1

(5,8

,9,1

7,18

)AT

M_T

XAD

DR

0(5

,8,9

,17,

18)

SW4_

ATM

_RXS

OC

(6,8

,9)

IRQ

3B(3

,8,1

6,17

,18)SW

4_A

TM_T

XCLA

V(6

,8,9

)

SW4_

ATM

_RX

D4

(6,8

,9)

SW4_

ATM

_RX

D6

(6,8

,9)

SW4_

ATM

_RX

D7

(6,8

,9)

SW4_

ATM

_RX

D0

(6,8

,9)

SW4_

ATM

_RX

D1

(6,8

,9)

SW4_

ATM

_RX

D3

(6,8

,9)

SW4_

ATM

_RX

D2

(6,8

,9)

SW4_

ATM

_RX

D5

(6,8

,9)

AD[0

:7]

(8,1

1,16

)

SW4_

ATM

_RXC

LAV

(6,8

,9)

V3U

3

V3U

3

V3U

3V3

U3

V3U

3

AVD

D

AVD

D

AAn

alog

1

AAn

alog

1

AAn

alog

1A

Anal

og1

AAn

alog

1

AAn

alog

1

C95

.01u

F

R29

82.5

C10

00.

1uF

+C

9810

uF16

V

J8 RJ4

5

Shie

lded

87654321 910

P8P7P6P5P4P3P2P1 GN

DA

GN

DB

R34

33.2

C10

9

470p

FC

0G

R26

619

C92

.01u

F

R24

499

C96

.01u

F

C10

50.

1uF

R35

499

L3

3 pi

n FB

13

2

C90

.01u

FC

97.0

1uF

C11

1

470p

FC

0G

R30

63.4

C10

10.

1uF

LPF

TRAN

SMIT

CH

ANN

EL

REC

EIVE

CH

ANN

EL

LPF

T1 PE-6

7583

1

3 5 4

2 6 1113

16 15

147 8 10 912

TX+

MID

1

AGN

D1

MID

2

TX-

NC

1

NC

2M

ID3

RX+

RX-

MID

4

RJ_

TX+

RJ_

TX-

RJ_

RX+

RJ_

RX-

AGN

D2

C91

.01u

F

R25

47

L2

3 pi

n FB

13

2

C10

60.

1uF

R33

63.4

R36

0

C10

30.

1uF

+C

9910

uF16

V

C93

.01u

F

C10

70.

1uF

U11

B

IDT7

7V10

7

78 81 83 86

6 23 43 68

77 80 82 87

25 26 32 50 6394 9198 1

AVD

DAV

DD

AVD

DAV

DD

VDD

VDD

VDD

VDD

AGN

DAG

ND

AGN

DAG

ND

GN

DG

ND

GN

DG

ND

GN

D

VDD

GN

D

VDD

GN

DC

102

0.1u

F

D1

HSM

G-C

650

Gre

en

C10

80.

1uF

FID

2

1.2m

m M

ask

0.6m

m P

ad

C11

30.

1uF

U12

32.0

MH

z10

0PPM

1234

NC

GN

DO

UT

VCC

U11

AID

T77V

107

56 55 5367666564626160592724 21 22394041424445464737 36 35 34 33 2830 29 31 545758

9293 85 84 69 79 5 49 71 72 7352 703 24 51 74 88 89 9095 96 9775

7 8 9 10 11 12 13 141516171819 2038

48 99100

76

RD

WR

INT

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

TXC

LK

TXC

LAV

TXEN

TXSO

C

RXD

ATA7

RXD

ATA6

RXD

ATA5

RXD

ATA4

RXD

ATA3

RXD

ATA2

RXD

ATA1

RXD

ATA0

RXA

DD

R4

RXA

DD

R3

RXA

DD

R2

RXA

DD

R1

RXA

DD

R0

RXC

LK

RXC

LAV

RXE

NR

XSO

C

RES

ET

CS

ALE

TXD

-

TXD

+

RXD

+

RXD

-

RC

O

OSC N

CN

C

NC

NC

NC

NC

NC

TxR

EF

RxR

EF

TxLE

D

RxL

ED NC

NC

NC

NC

NC

NC

NCDA

TXD

ATA0

TXD

ATA1

TXD

ATA2

TXD

ATA3

TXD

ATA4

TXD

ATA5

TXD

ATA6

TXD

ATA7

TXAD

DR

0TX

ADD

R1

TXAD

DR

2TX

ADD

R3

TXAD

DR

4

TXPA

RIT

Y

RXP

ARIT

Y

RPL

I

M1

M0

SE

D2

HSM

G-C

650

Gre

en

L4 3.3u

H50

0mA

FID

1

1.2m

m M

ask

0.6m

m P

ad

C11

2.0

1uF

C11

00.

1uF

R32

10.0

K

C94

.01u

F

JP1

Jum

per .

2TH

12

C10

40.

1uF

R27

47

R31

10.0

K

R28

33.2

C89

.01u

F

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FID

UC

IALS

FOR

U13

Decoupling capacitors for VDD pins

Design the PCB with separate PWR planes

for the Transmitter and Receiver.

Connections between U13 pins 47/48 and

U14 pins 8/7 should be of minimum

length.

83

RX PWR P

lane

9

TX PWR Plane

50 ohm Microstrip should be used.

5

1 62

4

7

Place contiguous GND under U13.

plac

e C1

23 a

nd C

124

near

U15

plac

e U1

5 ne

ar U13

plac

e C1

20ne

ar U

13

VDD_

CS_1

Pla

ne

VDD_

TPE_

1 Pl

ane

VDD_

CR_1

Pla

ne

VDD_

RPE_

1 Pl

ane

VDD_

SP_1

Pla

ne

no load

Defa

ult-

Load

A

DU

ET A

DS

A

ATM

155

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

825

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

TDO

T_1

TDO

C_1

RD

IC_1

SD_1

RD

IT_1

19_4

4MH

Z_2

VDD

_TPE

_1

VDD

_CR

_1

VDD

_RPE

_1

VDD

_CS_

1

VDD

_SP_

1

VCC

_RX_

1

VCC

_TX_

1

19_4

4MH

Z_1

MD

6

MD

2M

D1

MD

3

MD

7

MD

0

MD

5M

D4

AD3

AD2

AD0

AD1

AD5

AD4

AD6

ATM

_TXD

2(5

,7,9

,17,

18)

ATM

_TXD

1(5

,7,9

,17,

18)

ATM

_TXD

3(5

,7,9

,17,

18)

ATM

_TXD

0(5

,7,9

,17,

18)

ATM

_TXD

7(5

,7,9

,17,

18)

ATM

_TXD

4(5

,7,9

,17,

18)

ATM

_TXD

6(5

,7,9

,17,

18)

ATM

_TXD

5(5

,7,9

,17,

18)

ATM

_TXE

N(5

,7,9

,17,

18)

ATM

_TXC

LK_A

TM15

5(9

)

ATM

_TXS

OC

(5,7

,9,1

7,18

)

ATM

_RXE

N(5

,7,9

,17,

18) C

S_AT

M15

5B(1

1)

RST

_155

B(1

1)

WR

_B(1

1,16

)R

D_B

(11)

ATM

_RXA

DD

R1

(5,7

,9,1

7,18

)

ATM

_TXA

DD

R1

(5,7

,9,1

7,18

)AT

M_T

XAD

DR

0(5

,7,9

,17,

18)

SW4_

ATM

_TXC

LAV

(6,7

,9)

IRQ

3B(3

,7,1

6,17

,18)

AD[0

:6]

(7,1

1,16

)

MD

[0:7

](1

1,16

)

ATM

_RXC

LK_A

TM15

5(9

)

SW4_

ATM

_RXS

OC

(6,7

,9)

SW4_

ATM

_RX

D3

(6,7

,9)

SW4_

ATM

_RX

D5

(6,7

,9)

SW4_

ATM

_RX

D1

(6,7

,9)

SW4_

ATM

_RX

D4

(6,7

,9)

SW4_

ATM

_RX

D6

(6,7

,9)

SW4_

ATM

_RX

D0

(6,7

,9)

SW4_

ATM

_RX

D7

(6,7

,9)

SW4_

ATM

_RX

D2

(6,7

,9)

ATM

_RXA

DD

R0

(5,7

,9,1

7,18

)

155M

PSEL

(11)

SW4_

ATM

_RXC

LAV

(6,7

,9)

V3U

3

VDD

155

VDD

155

VDD

155

VDD

155

VDD

155

VDD

155

V3U

3

VDD

155

VDD

155

VDD

155

VDD

155VD

D15

5

VDD

155

VDD

155

VDD

155

VDD

155

VDD

155

U15

19.4

4MH

z20

PPM

1 23 4

NC

GN

DO

UT

VDD

+C

125

10uF

16V

L73

pin

FB1

3

2

C12

80.

1uF

+C

119

10uF

16V

FID

3

1.2m

m M

ask

0.6m

m P

adC

132

0.1u

F

+C

121

10uF

16V

R39

130

U13

B

UPD

9840

4

1 27 36 60 73 95 108

119

129 16 37 71 72 86 102

109

110

124

143

144

39 45 49 5335

32 33

5842 46 505638

29 30 34

57

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

VDD

-TPE

VDD

-TPE

VDD

-TPE

VDD

-RPE

VDD

-SP

VDD

-CS

VDD

-CS

VDD

-CR

GN

D-T

PEG

ND

-TPE

GN

D-R

PEG

ND

-RPE

GN

D-S

P

GN

D-C

SG

ND

-CS

GN

D-C

S

GN

D-C

R

+C

131

10uF

16V

FID

4

1.2m

m M

ask

0.6m

m P

ad

C13

00.

1uF

Seri

alPM

D

CPU

Man

agem

ent

Inte

rfac

e

Uto

pia

Rx

Uto

pia

Tx

Para

llel

PMD JT

AG

Port

U13

A

UPD

9840

4

98 9710079808182838788899091929394

40 41 43 44 4847

118

117

116

115

114

113

112

111

107

106

105

104

103

120

123

121

122

130

131

132

133

134

135

136

137

138

139

140

141

142

128

125

127

126 78 99 96 101

666564632423 6261222120191817

84778567 68 25 26 283159 69 7051 52 54 55 10 11 12 13 14 15 74 75 76 7 8 9 4 3 5 2 6

R/W

_B/W

R_B

DS_

B/R

D_B

PHIN

T_B

MAD

D1

MAD

D2

MAD

D3

MAD

D4

MAD

D5

MD

0M

D1

MD

2M

D3

MD

4M

D5

MD

6M

D7

TFKT

TFKC

TCO

TTC

OC

TDO

CTD

OT

TDI7

TDI6

TDI5

TDI4

TDI3

TDI2

TDI1

TDI0

TAD

D4

TAD

D3

TAD

D2

TAD

D1

TAD

D0

TCLK

FULL

_B/T

CLA

VTE

NBL

_BTS

OC

RD

O0

RD

O1

RD

O2

RD

O3

RD

O4

RD

O5

RD

O6

RD

O7

RAD

D0

RAD

D1

RAD

D2

RAD

D3

RAD

D4

RC

LKEM

PTY_

B/R

CLA

VR

ENBL

_BR

SOC

MAD

D0

ACK_

B/R

DY_

BC

S_B

RES

ET_B

RPD

5R

PD4

RPD

3R

PD2

TPD

7TP

D6

RPD

1R

PD0

TPD

5TP

D4

TPD

3TP

D2

TPD

1TP

D0

MAD

D6

MSE

L

UM

PSEL

RPD

6R

PD7

TPC

TFC

REF

CLK

AIN

1

RPC

PSEL

0PS

EL1

RC

ITR

CIC

RD

ITR

DIC

PHYA

LM0

PHYA

LM1

PHYA

LM2

TFSS

TxFP TC

LR

xFP

RC

LPM

DAL

M

TEST

0TE

ST1

TEST

2

JDI

JDO

JMS

JCK

JRST

_B

C11

40.

1uF

R37

130

R42

82.5

C12

40.

1uF

R46

82.5

C11

60.

1uF

L8

3 pi

n FB

13

2

R44

82.5

L11

3 pi

n FB

13

2

R41

130

R47 0

C12

3.0

1uF

C12

0

0.1u

F

C11

50.

1uF

R38

82.5

BAR

J22

Zero

Ohm

1 3

2

R43

130

L53

pin

FB1

3

2

C13

40.

1uF

C11

80.

1uF

L9

3 pi

n FB

13

2

+C

127

10uF

16V

Qua

ntiz

erDriv

er

Prea

mp

LED

Phot

odio

de

Dup

lex

Opt

ical

Rec

epta

cle

U14

HFB

R-5

805

12 3 4 56 789

10

11

VEE_

RX

RD

RD

SD VCC

_RX

VCC

_TX

TDTDVEE_

TX

MT_HOLE1_GND

MT_HOLE2_GND

R45

130

+C

133

10uF

16V

L63

pin

FB1

3

2

C13

50.

1uF

C11

70.

1uF

L10

3 pi

n FB

13

2

C13

60.

1uF

C12

20.

1uF

R40

82.5

L12

3 pi

n FB

13

2

C13

70.

1uF

C12

60.

1uF

+C

129

10uF

16V

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

UTOPIA TX

Adtech TX

PD9

PD15

PD13

PD6

PD4

PD3

PD14

PD12

PD7

PD5

IAP0

IAP7

WAIT

_A

IAP4

IAP6 PB17

OP0

IAP1

IAP2

IAP5

UTOPIA RX

IAP3

Adtech RX

PB20

SW_P

B26

SW_P

B24

PB15

PB21

PB22

PD10

PD11

PB18

PB14

PC15

PB16

SW_P

B25

NO LOAD NO LOAD

DU

ET A

DS

A

AD

TEC

H

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

925

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

TxD

4Tx

D2

TxD

3

TxD

6

TxD

1

TxD

7Tx

D5

TxD

0

RxD

0

RxD

5

RxD

2R

xD1

RxD

3

RxD

7R

xD6

RxD

4

TxSO

C

RxS

OC

ATM

RX_

CLK

_PW

RAT

MTX

_CLK

_PW

R

ATM

_RXC

LK_A

DTE

CH

ATM

_TXC

LK_A

DTE

CH

TxAD

DR

0_m

aste

rTx

ADD

R2_

mas

ter

TxAD

DR

3_m

aste

rTx

CLA

V0_m

aste

rTx

ADD

R4_

mas

ter

TxAD

DR

1_m

aste

r

TxEN

_mas

ter

RxE

N_m

aste

r

RxA

DD

R4_

mas

ter

RxA

DD

R2_

mas

ter

RxA

DD

R0

RxC

LAV0

_mas

ter

RxA

DD

R3_

mas

ter

RxA

DD

R1_

mas

ter

ATM

_TXD

0(5

,7,8

,17,

18)

ATM

_TXD

3(5

,7,8

,17,

18)

ATM

_TXD

5(5

,7,8

,17,

18)

ATM

_TXD

7(5

,7,8

,17,

18)

ATM

_TXD

6(5

,7,8

,17,

18)

ATM

_TXS

OC

(5,7

,8,1

7,18

)

ATM

_TXD

4(5

,7,8

,17,

18)

ATM

_TXD

2(5

,7,8

,17,

18)

ATM

_TXD

1(5

,7,8

,17,

18)

SW4_

ATM

_RX

D4

(6,7

,8)

SW4_

ATM

_RX

D3

(6,7

,8)

SW4_

ATM

_RX

D1

(6,7

,8)

SW4_

ATM

_RXS

OC

(6,7

,8)

SW4_

ATM

_RX

D6

(6,7

,8)

SW4_

ATM

_RX

D2

(6,7

,8)

SW4_

ATM

_RX

D0

(6,7

,8)

SW4_

ATM

_RX

D5

(6,7

,8)

SW4_

ATM

_RX

D7

(6,7

,8)

ATM

_TXC

LK_A

TM25

(7)

ATM

_TXC

LK_A

TM15

5(8

)

ATM

_RXC

LK_A

TM25

(7)

ATM

_RXC

LK_A

TM15

5(8

)

BRES

ETA_

___A

TM_R

XCLK

_SW

4(3

,6,1

7,18

)

ATM

_TXC

LK(5

,17,

18)

ATM

_TXA

DD

R0

(5,7

,8,1

7,18

)SW

1_AT

M_T

XAD

DR

2(6

,7,8

)SW

1_AT

M_T

XAD

DR

3(6

,7,8

)SW

4_A

TM_T

XCLA

V(6

,7,8

)AT

M_T

XAD

DR

4(5

,7,8

,17,

18)

ATM

_TXA

DD

R1

(5,7

,8,1

7,18

)

ATM

_TXE

N(5

,7,8

,17,

18)

ATM

_RXE

N(5

,7,8

,17,

18)

ATM

_RXA

DD

R4

(5,7

,8,1

7,18

)AT

M_R

XAD

DR

2(5

,7,8

,17,

18)

ATM

_RXA

DD

R0

(5,7

,8,1

7,18

)

SW1_

ATM

_RXA

DD

R3

(6,7

,8)

SW4_

ATM

_RXC

LAV

(6,7

,8)

ATM

_RXA

DD

R1

(5,7

,8,1

7,18

)

V3U

3

V3U

3

V3U

3

V3U

3

C38

4.0

1uF

C37

712

0pF

C0G

U59

AC

Y230

9

2 3 14 15 6 7 10 11 16

91 8

CLK

A1C

LKA2

CLK

A3C

LKA4

CLK

B1C

LKB2

CLK

B3C

LKB4

CLK

OU

T

S1REF

S2

U59

B

CY2

309

4125

13VD

DG

ND

GN

DVD

DC

379

0.1u

F

L53

3 pi

n FB

13

2

R29

110

.0K

+C

382

10uF

16V

R27

710

.0K

R28

810

.0K

C38

112

0pF

C0G

TX D

ATA

01 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 494745434139373533

TX D

ATA

2

TX D

ATA

5TX

DAT

A 7

TX D

ATA

8

TX D

ATA

1TX

DAT

A 3

TX D

ATA

4TX

DAT

A 6

GND

TX D

ATA

10

TX D

ATA

13GN

D

TX D

ATA

15TX

PAR

ITY

TX A

DDR

0GN

DTX

ADD

R 3

TX C

LAV

0TX

CLA

V 1

TX C

LAV

3GN

DPT

X AD

DR 0

PTX

ADDR

2PT

X AD

DR 3

PTX

CLAV

0GN

DPT

X CL

AV 3

PTX

CLOC

K

GND

TX D

ATA

9TX

DAT

A 11

TX D

ATA

12TX

DAT

A 14

GND

TX S

OC20 3830 32 502 22 444016 2612 28 484214 36 46188 24 3464 10

TX A

DDR

1TX

ADD

R 2

TX A

DDR

4GN

DTX

CLA

V 2

TX E

NABL

ETX

CLO

CK

GND

GND

PTX

ADDR

1

PTX

ADDR

4PT

X CL

AV 1

PTX

CLAV

2PT

X EN

ABLE

J10

txAD

TEC

H H

eade

r Shr

oude

d

0.1

CTR

R27

810

.0K

C38

0.0

1uF

RX D

ATA

01 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 494745434139373533

RX D

ATA

2

RX D

ATA

5RX

DAT

A 7

RX D

ATA

8

RX D

ATA

1RX

DAT

A 3

RX D

ATA

4RX

DAT

A 6

GND

RX D

ATA

10

RX D

ATA

13GN

D

RX D

ATA

15RX

PAR

ITY

PRX

ADDR

0GN

DPR

X AD

DR 3

PRX

CLAV

0PR

X CL

AV 1

PRX

CLAV

3GN

DRX

ADD

R 0

RX A

DDR

2RX

ADD

R 3

RX C

LAV

0GN

DRX

CLA

V 3

RX C

LOCK

GND

RX D

ATA

9RX

DAT

A 11

RX D

ATA

12RX

DAT

A 14

GND

RX S

OC20 3830 32 502 22 444016 2612 28 484214 36 46188 24 3464 10

PRX

ADDR

1PR

X AD

DR 2

PRX

ADDR

4GN

DPR

X CL

AV 2

PRX

ENAB

LEPR

X CL

OCK

GND

GND

RX A

DDR

1

RX A

DDR

4RX

CLA

V 1

RX C

LAV

2RX

ENA

BLE

J9 rxAD

TEC

H H

eade

r Shr

oude

d

0.1

CTR

R27

951

0

U58

AC

Y230

9

2 3 14 15 6 7 10 11 16

91 8

CLK

A1C

LKA2

CLK

A3C

LKA4

CLK

B1C

LKB2

CLK

B3C

LKB4

CLK

OU

T

S1REF

S2

C38

30.

1uF

L54

3 pi

n FB

13

2

R29

251

0 U58

B

CY2

309

4125

13VD

DG

ND

GN

DVD

D

RP2

5

4x22

1 2 3 45678

R29

010

.0K

R28

910

.0K

RP2

6

4x22

1 2 3 45678

+C

378

10uF

16V

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DU

ET A

DS

A

PCM

CIA

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1025

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

PCCA

1

PCCD

3

BWE3

b

PCCA

10

PCCD

14

BD12

PCCA

7

BA20

PCCD

10

PCCD

10

BPO

EAb

BD15

PCCD

8

PCCA

16

BWE0

b

PCCA

25

PCCA

10

PCCD

6

PCCA

11

BALE

A

BA21

PCCD

7

PCCA

16

BA29

PCCA

19

PCCA

21BA

19

PCCA

22

BD2

PCCD

1

CVS1

PCCE

Nb

PCCA

8

PCCA

22

BPO

EAb

BD13

PCCA

2

BA24

PCCD

2

BA11

CR

DY

BD9

CIN

PAC

Kb

PCCA

3

BA22

CINP

ACKb

BBVD

2

BRD

Y

BD14

PCCA

17

BA16

PCCD

13

CC

D2b

BA8

PCCA

11

BWP

PCCA

17

PCCA

6PC

CD5

PCCD

11

PCCA

18

PCCD

15

CC

D2b

CCD1

b

BCD

1b

PCCD

7

BD3

CVS

1

PCCA

1

PCCA

19

PCCD

1

PCCA

12

BCD

2b

BVS1

CVS2

CW

P

PCCD

3

PCCD

9

PCCA

24

BA27

PCCA

14

PCCA

6

PCCD

4

BA13

PCRE

Gb

PCCD

0

PCCD

8

BA15

PCCA

9

PCCA

0

BA6

PCCD

12

CVS

2

PCCA

18

BD5

BD0

PCCA

2

BA30

BD4

PCCD

2

BA17

PCCA

0

BA25

PCCA

23

BD10

BA12

PCCA

3

PCCA

13

CVS

2

PCC

A[0:

25]

BWAI

TAb

PCCD

15

BD11

BA14

BWE2

b

PCCA

5

PCCA

20

BVS2

BA18

PCCA

15

PCCA

7

BA28

PCCD

6

BA10

CC

D1b

PCCD

12PC

CD5

PCCA

4

PCCD

13

PCC

D[0

:15]

BD1

PCCA

14

BD7

BD8

BBVD

1

PCCA

25

PCCA

4PC

CD4

BA9

PCCA

9

PCCA

12

BA31

CBV

D2

PCCA

5

PCCA

13

BA7

PCCD

0

PCCA

15

PCCA

21

BA23

PCCA

8

PCCD

9

BWE1

b

PCRE

Gb

PCCA

23

CVS

1

BA26

PCCD

11

PCCA

20

PCCA

24

BD6

PCCD

14

CBVD

2

CWP

CBVD

1

CWAI

TAb

CBV

D1

CW

AITA

b

BSPK

OU

T

BD[0

:15]

(2,4

,11,

18,2

4)

PCR

Wb

(24)

BA[6

:31]

(2,4

,11,

18,2

4)

REG

Ab(3

,17)

BWE2

b(2

,4)

PCC

VPP

(13)

BALE

A(4

,18) PC

CEN

b(1

1,14

,24)

PBC

E2Ab

(4)

PCO

ENb

(24)

PBC

E1Ab

(4)

BWE3

b(2

,4)

PCC

VCC

(13,

14)

BPO

EAb

(4)

BWE1

b(2

,4)

SW4_

BRES

ETA

(6)

BWE0

b(2

,4,1

8)

PCEE

Nb

(24)

SW4_

BVS1

(6)

SW4_

BBVD

1(6

)

SW4_

BRD

Y(6

)SW

4_BC

D2b

(6)

ATM

_RXC

LAV

(5,6

,17,

18)

SW4_

BWAI

TAb

(6)

SW4_

BCD

1b(6

)

SW4_

BVS2

(6)

SW4_

BWP

(6)

SW4_

BBVD

2(6

)

SPKR

OU

T(3

,17)

PCC

ENb

(11,

14,2

4)

PCC

VCC

(13,

14)

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

RN

28x

10K

1234678910 5

J11

PCM

CIA

CO

NN

ECTO

R29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 20 19 46 47 48 49 50 53 54 55 56 7 42 61 15 9 44 45 58

30 31 32 2 3 4 5 6 64 65 66 37 38 39 40 41 16 33 59 60 62 63 43 57 36 67 17 51 18 52

1 34 35 68

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

CE1

CE2

REG

WE/

PCM

OE

IOR

DIO

WR

RES

ET

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

RD

Y/BS

YW

PW

AIT

INPA

CK

BVD

2BV

D1

VS1

VS2

CD

1C

D2

VCC

1VC

C2

VPP1

VPP2

GN

D1

GN

D2

GN

D3

GN

D4

U16

A74

LVC

H32

373A

A5 A6 B5 B6 C5

C6

D5

D6 E5 E6 F5 F6 G5

G6

H6

H5A4 A3 H4

H3

A2 A1 B2 B1 C2

C1

D2

D1

E2 E1 F2 F1 G2

G1

H1

H2

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

LE1

OE1

LE2

OE2

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

U16

C74

LVC

H32

373A

F4 L3 L4 P3

K3 K4 M3

M4

N3

N4

R3

R4

P4C3

C4 F3

B3 B4 D3

D4

E3 E4 G3

G4

VCC

VCC

VCC

VCC

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

U20

E74

LCX1

257

14G

ND

VCC

C14

10.

1uF

U18

B74

LVC

H16

2244

4 10 15 21 28 34 39 45

7 18 31 42

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

U19

B74

LVC

HR

1622

45A

4 10 15 21 28 34 39 45

7 18 31 42

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

U18

A74

LVC

H16

2244

47 46 44 43 141 40 38 37 48 36 35 33 32 2530 29 27 26 24

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

1A0

1A1

1A2

1A3

OE1

2A0

2A1

2A2

2A3

OE2

3A0

3A1

3A2

3A3

OE3

4A0

4A1

4A2

4A3

OE4

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

3Y0

3Y1

3Y2

3Y3

4Y0

4Y1

4Y2

4Y3

C14

90.

1uF

C15

30.

1uF

C14

70.

1uF

R52

75C

154

0.1u

F

R51

10.0

K

C14

20.

1uF

U20

B74

LCX1

25

56

4

C13

80.

1uF

RN

1 8x10

K

1234678910 5

C14

60.

1uF

R49

10.0

K

C14

80.

1uF

RP1

7

8x10

K

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

C14

30.

1uF

C13

90.

1uF

U20

C74

LCX1

2512

11

13

U16

B74

LVC

H32

373A

J5 J6 K5 K6 L5 L6 M5

M6

N5

N6 P5 P6 R5

R6 T6 T5J4 J3 T4 T3

J2 J1 K2 K1 L2 L1 M2

M1

N2

N1

P2 P1 R2

R1

T1 T2

3D1

3D2

3D3

3D4

3D5

3D6

3D7

3D8

4D1

4D2

4D3

4D4

4D5

4D6

4D7

4D8

LE3

OE3

LE4

OE4

3Q1

3Q2

3Q3

3Q4

3Q5

3Q6

3Q7

3Q8

4Q1

4Q2

4Q3

4Q4

4Q5

4Q6

4Q7

4Q8

+S1

QM

B-01

30 O

hm

U20

A74

LCX1

25

23

1

C15

50.

1uFC

144

0.1u

F

R53

1.00

K

U19

A74

LVC

HR

1622

45A

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 261 2448 25

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

DIR

1

DIR

2

OE1

OE2

C14

00.

1uF

C15

00.

1uF

C15

10.

1uF

C15

20.

1uF

C14

50.

1uF

C15

70.

1uF

C15

6

0.1u

F

R50

10.0

K

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

This reset (RST_T1A) is

active on low-to-high

edge. Normal state after

reset is low.

*232-1

S2 T

ABLE

S2

OFF

4

ON

21 3

232-2

*ATM

*MII2

*T1/MII2

PCMCIA

ADTECH

10BT

* = default

Soft

Switch

Disable

Enable

DU

ET A

DS

A

Con

trol

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1125

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

MD

4M

D3

MD

2

MD

6M

D7

MD

5

MD

0M

D1

AD3

AD6

AD1

AD5

AD2

AD7

AD4

AD0

BA21

BA22

BA23

BA24

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BD0

BD1

BD2

BD3

BD7

BD6

BD5

BD4

TDI

TMS

TDO

TCK

ALE_

ATM

25(7

)

CS_

ATM

25B

(7)

WR

_ATM

25B

(7)

RD

_ATM

25B

(7)

RST

_25B

(7)

MD

[0:7

](8

,16)

AD[0

:7]

(7,8

,16)

155M

PSEL

(8)

CS_

ATM

155B

(8)

WR

_B(8

,16)

RD

_B(8

)

RST

_155

B(8

)

T1A_

CS~

(16)

RST

_T1A

(16)

BA[2

1:31

](2

,4,1

0,18

,24)

BD[0

:7]

(2,4

,10,

18,2

4)

OE~

(2,3

,4,1

7)C

S5b

(3,1

7,24

) RPO

RIb

(3,1

4,15

,17,

18)

RW

b(3

,4,1

7,18

)TS

b(3

,4,1

7) WE0

b(2

,3,4

,17)

HR

ESET

b(3

,15,

17,1

8,24

)PC

CEN

b(1

0,14

,24)

Switc

h_1

(6)

Switc

h_2

(6)

Switc

h_3

(6)

Switc

h_4

(6)

R/M

IIRXE

NC

-1(1

4,21

)

RST

R/M

IIb-1

(21)

BSYS

CLK

1(1

9)

R/M

IIRXE

NC

-2(1

4,22

)R

STR

/MIIb

-2(2

2)

TAb

(3,1

7,18

,24)

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

R60

10.0

K

TP23

TP22

C15

9.0

1uF

R61

10.0

K

U22

BEP

M31

28

51 58 130

123

115 50 95 73 24 76 144

33 77 64 3 135

26 13 94 17 124

52 105

85 57 114

59 129

VCC

INT

VCC

INT

VCC

INT

VCC

INT

VCC

IOVC

CIO

VCC

IOVC

CIO

VCC

IOVC

CIO

VCC

IO

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

J12

1x3

Hea

der

0.1

CTR

1 2 3

TP24

C15

80.

1uF

C16

1.0

1uF

R62

10.0

K

TP25

C16

3.0

1uF

J13

2x5

Hea

der

0.1

CTR

12

34

56

78

910

C16

5.0

1uF

R54

10.0

K

U22

AEP

M31

28

699380828365966315 16 18 21 22 23 25 27 28 29 30

72

5 6 7 8 9 10 11 14 38 141

142

136

137

139

614540100

678179789798 86

140

5571117

68

134

127

116

113

7074119

60

53 125

88102

8456

143

110

118

109

89 410

4 20

111

87

91

101

128

112

126 1 2 12 19 34 35 36 43 46 47 48 49 66 75 90 103

108

120

121

122

31 32 37 39 41 42 44 54 92 99 106

107

131

132

133

138

AD_A

TM0

AD_A

TM1

AD_A

TM2

AD_A

TM3

AD_A

TM4

AD_A

TM5

AD_A

TM6

AD_A

TM7

ADD

R_P

Q21

ADD

R_P

Q22

ADD

R_P

Q23

ADD

R_P

Q24

ADD

R_P

Q25

ADD

R_P

Q26

ADD

R_P

Q27

ADD

R_P

Q28

ADD

R_P

Q29

ADD

R_P

Q30

ADD

R_P

Q31

ALE_

ATM

25

BDAT

0BD

AT1

BDAT

2BD

AT3

BDAT

4BD

AT5

BDAT

6BD

AT7

CE1

CE2

CLK

FUN

C_S

EL0

FUN

C_S

EL1

FUN

C_S

EL2

IPAS

EL0

IPAS

EL1

MD

0M

D1

MD

2M

D3

MD

4M

D5

MD

6M

D7

MU

XSEL

nCS

nCS_

ATM

25nC

S_AT

M15

5nC

S_Fr

amer

nMII_

RX_

EN

nOE

nPO

RES

ET

nRD

_ATM

25nR

D_D

ual

nRES

ET_A

TM25

nRES

ET_A

TM15

5nR

ESET

_Fra

mer

nRES

ET_M

II

nTS

nWE

nWR

_ATM

25nW

R_D

ual

PDSE

L0PD

SEL1

RD

_nW

R

SPAR

E0SP

ARE1

SPAR

E2

TCK

TDI

TDO

TMS

nMII_

RX_

EN_2

nRES

ET_M

II_2

FUN

C_S

EL3

TP4

CLK

IN

TA OE1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Spar

e3Sp

are4

Spar

e5Sp

are6

Spar

e7Sp

are8

Spar

e9Sp

are1

0Sp

are1

1Sp

are1

2Sp

are1

3Sp

are1

4Sp

are1

5Sp

are1

6Sp

are1

7Sp

are1

8

R57

10.0

K

C16

20.

1uF

R55

10.0

K

R58

10.0

K

R56

10.0

K

S2

4 Po

sitio

n sw

itch5

321

678

4

C16

40.

1uF

C16

00.

1uF

R59

10.0

K

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DU

ET A

DS

A

blan

k

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1225

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

NO L

OAD

NO L

OAD

NOTE

: If

no

DUET

, vo

ltag

e won't

be r

ight

...

NOTE

: If

no

DUET

, vo

ltag

e won't

be r

ight

...

DU

ET A

DS

A

Pow

er

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1325

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

PCCV

PP0

PCCV

PP1

PCCV

CC1

PCVC

C0PC

VCC

0(2

4) PCC

VCC

1(2

4)

PCC

VPP1

(24)

PCC

VPP0

(24)

PCC

VPP

(10)

PCC

VCC

(10,

14)

VDB

VCC

VPP

VCC

V3U

3

A

VPPI

N

V3U

3_VD

DH

V3U

3

V1U

8

VCC

VCC

VCC

VCC

VCC

R26

084

9

C16

90.

1uF

+C

172

100u

F10

V

1 2

C37

60.

1uF

+C

171

1uF

16V

J14

1x3

TER

M B

LK R

/A5.

08M

M C

TR 1 2 3

clockwise

3

2 Wiper

CW

1CC

W

RV4

1K

3 1

2

U27

G74

AC14

714

GN

DVC

C

Q1

MM

DF3

N03

HD

2 3 457

1

68

+C

182

10uF

16V

R26

710

.0K

C17

0.0

1uF

F2 SMD

150/

33

L13

8000

mA

300

Z @

100

MH

z

6

3

5

4

1 2

8 7

U23

UM

IC29

501-

3.3B

U 5

2 1 6 3

4

FLG

VIN

ENAB

LETA

BG

ND

VOU

T

JP2

Jum

per .

2TH

12

D4

1SM

C5.

0AT3

5.0V

12

+C

184

10uF

16V

C17

7.0

1uF

C18

7

0.1u

F

TP15 1

JP13

Jum

per .

2TH

12

JP6

Jum

per .

2TH

12

JP7

Jum

per .

2TH

12

+C

173

10uF

16V

JP12

Jum

per .

2TH

12+

C17

410

uF16

VC

176

0.1u

F

C17

9.0

1uF

MH

312

5mil

Dril

l NPT

No

Rin

g

R70

5.11

K

R67 124K

R63

402

U26

LTC

1315

24 18 5 6 3 42 8 17 13 141 7

11 12 9 10

23 19 20

22 16

21 15

AVC

CIN

BVC

CIN

AVC

C0

AVC

C1

AEN

0AE

N1

ASH

DN

BSH

DN

BVPP

OU

TBD

RV5

BDR

V3

AVPP

INBV

PPIN

BVC

C0

BVC

C1

BEN

0BE

N1

AVPP

OU

TAD

RV5

ADR

V3

GN

DG

ND

VCC

VCC

D7

1SM

C12

AT3

12V

12

+C

183

1uF

16V

D3

20V

MBR

D62

0CT

6A

31

4

+C

372

100u

F10

V

1 2

Q2

MM

DF3

N03

HD

2345 7

1

6 8

C16

6

1000

pF

JP5

Jum

per .

2TH

12

C18

9

100p

FC

0G

+C

175

10uF

16V

C19

00.

1uF

C17

810

00pF

MH

412

5mil

Dril

l NPT

No

Rin

g

F1 SMD

260

+C

375

100u

F10

V

1 2

TAB

conn

ecte

dto

pin

2

U24

MIC

2950

0

1 4 2

3VI

N

TAB

GN

D

VOU

T

JP8

Jum

per .

2TH

12

D10

MM

BD91

4LT1

13

GND

GND

GND

GND

S3

Toggle Switch

1 32

45

67

+C

180

68uF

20V

+C

168

100u

F10

V

1 2

TP8 1

JP11

Jum

per .

2TH

12

C36

9.0

1uF

C37

30.

1uF

D9 M

MBD

914L

T1

1 3

R65 124K

D6 20

VM

BRD

620C

T

6A

31

4

MH

212

5mil

Dril

l NPT

No

Rin

g

C18

50.

1uF

C36

80.

1uF

U25

MIC

3915

1-1.

8BU

2 6 3

4

1

5

VIN

TAB

GN

D

VOU

T

ENAB

LE

FLG

J15

1x2

TER

M B

LK5.

08M

M C

TR 1 2

C37

40.

1uF

U27

B

74AC

14

34

C16

7.0

1uF

C18

8

0.01

uFX7

R1K

V

MH

112

5mil

Dril

l NPT

No

Rin

g

clockwise

3

2 Wiper

CW

1CC

W

RV3

1K

3 1

2

R26

110

.0K

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

RS23

2 PO

RT 2

ENA

BLED

SDRA

M E

NABL

ED

ETHE

RNET

ENA

BLED

RUN

FLAS

H EN

ABLE

D

5V P

OW

ER

RESE

RVED

INFR

A-RE

D EN

ABLE

D

RS23

2 PO

RT 1

ENA

BLED

SIG

NAL

LAM

P

PCM

CIA

ENAB

LED

PC9

PB28

100B

aseT

-2

PC8

USB

Enab

led

100B

aseT

-1

PB29

PC14

DU

ET A

DS

A

Res

et &

LED

's

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1425

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

CHIN

Sb

RSE

N2b

(19,

24)

ETH

ENb

(20,

24)

RU

N(1

5)

RES

ERVE

D(2

4)

SDR

AMEN

(2,2

4)

PCC

ENb

(10,

11,2

4)

IRD

ENb

(19,

24)

RSE

N1b

(19,

24)

CH

INSb

(5,1

5)

FEN

b(2

4)SGLA

MP

b(2

4)

RPO

RIb

(3,1

1,15

,17,

18)

PCC

VCC

(10,

13)

RPO

RI

(24)

R/M

IIRXE

NC

-1(1

1,21

)R

/MIIR

XEN

C-2

(11,

22)

nUSB

EN(2

3,24

)

PB28

(5,1

7,18

)PB

29(5

,17,

18)

PC8

(5,1

7,18

)PC

9(5

,17,

18) PC

14(5

,17,

18)

VCC

V3U

3

V3U

3

VCC

V3U

3V3

U3

V3U

3

V3U

3

VCC

VCC

U31

A74

LS24

4

2 4 6 8 11 13 15 17

18 16 14 12 9 7 5 3

1 19

A0 A1 A2 A3 B0 B1 B2 B3

YA0

YA1

YA2

YA3

YB0

YB1

YB2

YB3

1G 2GU30

A74

LS24

4

2 4 6 8 11 13 15 17

18 16 14 12 9 7 5 3

1 19

A0 A1 A2 A3 B0 B1 B2 B3

YA0

YA1

YA2

YA3

YB0

YB1

YB2

YB3

1G 2G

D26

HSM

Y-C

650

Yello

w

D22

HSM

Y-C

650

Yello

w

R79

150

U29

B

74AC

05

34

D14

HSM

Y-C

650

Yello

w

TP12

U27

D

74AC

14

98

D24

HSM

Y-C

650

Yello

w

D23

HSM

Y-C

650

Yello

w

U28

DS1

818

2 31

VCC

GN

DR

ST

TP10

U29

G74

AC05

147

VCC

GN

D

R82

150

R74

1.00

K

D19

HSM

Y-C

650

Yello

w

C19

3 0.1u

F

D11

HSM

G-C

650

Gre

en

U29

C

74AC

05

56

R71

150

R85

150

TP11

D13

MM

BD91

4LT1

13

D28

HSM

Y-C

650

Yello

w

U31

B74

LS24

410

20G

ND

VCC

D16

HSM

Y-C

650

Yello

w

R83

150

U27

C

74AC

14

56

R75

1.00

K

R87

150

R89

150

D20

HSM

Y-C

650

Yello

w

R91

150

TP5

D27

HSM

Y-C

650

Yello

w

TP13

U29

D

74AC

05

98

R72

150

D12

HSM

G-C

650

Gre

en

TP14

R77

150

C19

5

0.1u

F

D17

HSM

Y-C

650

Yello

w

D30

HSM

Y-C

650

Yello

w

U27

E

74AC

14

1110

R80

150

U29

E

74AC

05

1110

D21

HSM

Y-C

650

Yello

w

D25

HSM

Y-C

650

Yello

w

U20

D74

LCX1

259

8

10

D29

HSM

Y-C

650

Yello

w

D15

HSM

G-C

650

Gre

en

R78

150

U29

A

74AC

05

12

R76

51.1

K

+C

191

100u

F10

V

1 2

D18

HSM

Y-C

650

Yello

w

U30

B74

LS24

410

20G

ND

VCC

R84

150

R86

150

U29

F

74AC

05

1312

R81

150

R88

150

R73

1.00

K

R90

150

C19

4

0.1u

F

R92

150

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EPP

BD

M_C

LOC

KIS

P_EP

P_I/F

EPP

Com

plia

nt12

84A

Para

llel -

OnC

E

BD

M C

onn

Seria

lEP

P

BU

S_SW

ITC

H

1284

TR

AN

SCEI

VER

"TO

CH

IP"

SER

IAL

PLD

EPP

ENb

/ SER

IAL_

EN

DU

ET A

DS

A

HO

ST &

BD

M In

terf

ace

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1525

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

DB6

/IDEN

T

PP_A

D5

F_D

B2

PP_A

D[0

:7]

BDM

_DSC

K/SE

R_T

CK

PP_A

D7

PP_A

D2

F_D

B5PP

_AD

1

BDM

_DSC

K

IRQ

-

PP_A

D0

SRES

ETb

PP_I

NTb

PP_A

D2

HR

ESET

b

SER

IAL_

ENb

F_D

B1

PP_A

D6

Writ

e-

RPO

RIb

PP_W

Eb

DB4

/TR

ST_I

N

FREE

ZE1

VFLS

1

BDM

_DSD

I

F_IN

b

F_W

Eb

DB7

PP_A

D7

Sele

ct_5

V_O

UT

F_D

STR

b

EPP_

ISPT

DO

DB0

/RES

ET

DB3

/TD

I_IN

F_D

B4

PP_B

USY

_OU

T

PP_A

D4

DB5

/DE_

IN

BDM

_DSD

I/SER

_TD

I

PP_I

NbC

HIN

Sb

CO

N_D

SCK

EPP_

ISPT

MS

DB1

/TM

S_IN

EPP_

ENb

EPP_

ISPT

DI

PP_V

FLSP

0

F_D

B3

BDM

_DSD

O/S

ER_T

DO

PP_A

D3

SRES

ETb

PP_A

D4

F_AS

TRb

PP_A

D5

DB2

/TC

K_IN

EPP_

ISPT

CK

PP_A

D1

F_R

STb

EPP_

CLK

F_D

B6

PP_D

STR

b

Res

et-

PP_AD[0:7]

PP_A

D3

PP_D

STR

b

F_D

B7

PP_A

D6

PP_I

Nb

F_D

B0

PP_V

FLSP

0

CO

N_D

SDI

Dst

robe

-

HR

ESET

b

CO

N_D

SDO

PP_A

D0

Astro

be-

PP_W

Eb

PP_B

USY

_OU

T

RPO

RIb

RU

N

BDM

_DSD

O

PP_I

NTb

EPP_

ENb_

SW

EPP_

ENb_

SW

VFLS

R2b

PP_D

IR

F_IN

TbF_

VFLS

P0F_

VFLS

P1

F_SE

LEC

TF_

BUSY

PP_V

FLSP

1

PP_V

FLSP

1

FREE

ZE0

Wai

t-/TD

O_O

UT

IN-

VFLS

0VF

LS1PP

_RST

b

EPP_

CLK

PP_A

STR

b

PP_A

STR

b

VFLS

0

PP_R

STb

PP_I

NTb

(17)

DSC

K(3

)

CH

INSb

(5,1

4)

PP_A

STR

b(1

7)

PP_R

STb

(17)

PP_V

FLSP

0(1

7)

RU

N(1

4)

EPP_

CLK

(17)

PP_B

USY

_OU

T(1

7)

RPO

RIb

(3,1

1,14

,17,

18)

PP_A

D[0

:7]

(17)

DSD

I(3

)

PP_W

Eb(1

7)

SRES

ETb

(3,1

7,18

,24)

DSD

O(3

)

PP_D

STR

b(1

7)

VFLS

0(3

,17)

VFLS

1(3

,17)

HR

ESET

b(3

,11,

17,1

8,24

)

PP_V

FLSP

1(1

7)

BDM

_DSD

O(1

7)BD

M_D

SDI

(17)

BDM

_DSC

K(1

7)

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3V3

U3

VCC

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

VCC

C19

7 1nF1 2

L26

FB1

2

L17

FB1

2

R10

1

1.00

K

R10

61.

00K

C22

50.

1uFC

212 1nF

1 2

R10

210

0

C23

50.

1uF

L31

FB1

2

C22

80.

1uF

L22

FB1

2

D32

HSM

G-C

650

Gre

en

U32

AEP

M31

28AT

4 15 73 62 87 90 88

4441

1089 812

7

100

99

98 97

969493 9

225 242123

2013

37 25

64

30

17

6 1

50 525648

58

46 4763

57 2729 28

49

1954 68

75 83 69

9236

14

32

79 76 71 8581

84

8077727061

16

60

67

42

2

40

3531

55

45

TDI

TMS

TDO

TCK

IN/G

CLK

1IN

/OE2

/GC

LK2

IN/O

E1

(C)G

IO41

(C)G

IO39

(A)G

IO14

IN/G

CLR

(B)G

IO16

(A)G

IO13

(B)G

IO17

(A)G

IO3

(A)G

IO4

(A)G

IO5

(A)G

IO6

(A)G

IO7

(A)G

IO8

(A)G

IO9

(B)G

IO15

(C)G

IO23

(B)G

IO19

(C)G

IO21

(C)G

IO24

(C)G

IO22

(C)G

IO25

(B)G

IO12

(C)G

IO29

(C)G

IO20

(G)G

IO57

(D)G

IO34

(C)G

IO27

(B)G

IO18

(A)G

IO2

(E)G

IO47

(F)G

IO48

(F)G

IO51

(E)G

IO45

(F)G

IO53

(E)G

IO43

(E)G

IO44

(G)G

IO56

(F)G

IO52

(D)G

IO37

(D)G

IO35

(D)G

IO36

(E)G

IO46

(C)G

IO26

(F)G

IO49

(G)G

IO59

(H)G

IO64

(H)G

IO70

(G)G

IO60

(A)G

IO10

(D)G

IO30

(B)G

IO11

(D)G

IO32

(H)G

IO67

(H)G

IO65

(G)G

IO62

(H)G

IO72

(H)G

IO69

(H)G

IO71

(H)G

IO68

(H)G

IO66

(G)G

IO63

(G)G

IO61

(F)G

IO55

(C)G

IO28

(F)G

IO54

(G)G

IO58

(E)G

IO40

(A)G

IO1

(E)G

IO38

(D)G

IO31

(D)G

IO33

(F)G

IO50

(E)G

IO42

R94

1.00

K C20

7 1nF1 2

U35

B74

CBT

LV32

5716

8VC

CG

ND

C21

6 1nF1 2

C23

30.

1uF

DIP

8

20 M

hz

J17

SOC

KET

for O

SC

1 2 3 4

8 7 6 5

NC

NC

NC

GN

D

VCC

NC

NC

OU

T

L27

FB1

2

C20

4 1nF1 2

C22

0 1nF1 2

L18

FB1

2

C22

60.

1uF

C21

7 1nF1 2

C20

0 1nF1 2

C22

90.

1uF

C21

3 1nF1 2

L23

FB1

2

U35

A74

CBT

LV32

57

2 3 5 6 11 10 14 13 1 15

4 7 9 12

1B1

1B2

2B1

2B2

3B1

3B2

4B1

4B2

S OE

1A 2A 3A 4A

R10

3

0

L14

FB1

2

C19

9 1nF1 2

C23

40.

1uF

RN

38x

10K

1234678910 5

R96

150

L28

FB1

2

C20

9 1nF1 2

C20

1 1nF1 2

C20

8 1nF1 2

J21

2x5

Hea

der

0.1

CTR

12

34

56

78

910

C20

3 1nF1 2

L19

FB1

2

R10

4

0

C22

1 1nF1 2

C23

00.

1uF

C21

1 1nF1 2

L24

FB1

2

R93

1.00

K

L15

FB1

2

R95

10.0

K

C21

4 1nF1 2

C22

30.

1uF

J18

DB2

5

13251224112310229218207196185174163152141

2627

R97

150

L29

FB1

2

C21

8 1nF1 2

J19

1x2

Hea

der

0.1

CTR

12

L20

FB1

2C19

8 1nF1 2

R98

10.0

K

C23

10.

1uF

C20

2 1nF1 2

C19

60.

1uF

C22

2 1nF1 2

L25

FB1

2

J16

2x5

Hea

der

0.1

CTR

12

34

56

78

910

C20

5 1nF1 2

J20

1x2

Hea

der

0.1

CTR

12

L16

FB1

2

C21

0 1nF1 2

R99

10.0

K

C22

40.

1uF

C20

6 1nF1 2

D31

HSM

G-C

650

Gre

en

L30

FB1

2

U33

A74

LVX

1612

84

29 28 27 26 19 25 41 40 38 37 36 35 33 32 47 46 45 44 43

20 21 22 23 30 24 8 9 11 12 13 14 16 17 1 48 2 3 4 5 6

C14

C15

C16

C17

PLH

inH

LHin B1 B2 B3 B4 B5 B6 B7 B8 Y9 Y10

Y11

Y12

Y13

A14

A15

A16

A17

PLH

HLH

A1 A2 A3 A4 A5 A6 A7 A8 HD

DIR

A9 A10

A11

A12

A13

C22

70.

1uF

C21

5 1nF1 2

L21

FB1

2

R10

0

1.00

K

R10

51.

00K

C21

9 1nF1 2

U33

B

74LV

X161

284

7 18 31 42

10 15 34 39

VCC

1VC

C2

VDD

1VD

D2

GN

DG

ND

GN

DG

ND

U32

BEP

M31

28AT

39 91 3 18 34 51 66 82

38 86 11 26 33 43 53 59 65 74 78 95

VCC

INT1

VCC

INT2

VCC

IO1

VCC

IO2

VCC

IO3

VCC

IO4

VCC

IO5

VCC

IO6

GN

DIN

T1G

ND

INT2

GN

DIO

1G

ND

IO2

GN

DIO

3G

ND

IO4

GN

DIO

5G

ND

IO6

GN

DIO

7G

ND

IO8

GN

DIO

9G

ND

IO10

C23

20.

1uF

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

1:2

TDMA

outp

ut

1:1

T10

W13

T15

W10

V14

W15

PC5

PA5

PA9

PC4

PA7

PA8

This reset (RST_T1A) is

active on low-to-high

edge. Normal state after

reset is low.

DU

ET A

DS

A

T1&

E1

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1625

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

MD

3M

D2

AD7

MD

7

MD

4

MD

1

AD4

AD5

MD

0

AD0

MD

6M

D5

AD1

AD2

AD3

AD6

MD

[0:7

](8

,11)

AD[0

:7]

(7,8

,11)

SW3_

T1_L

1RxD

A(6

)SW3_

T1_L

1TSY

NC

A(6

)

SW3_

T1_L

1TXD

A(6

)

SW3_

T1_L

1RSY

NC

A(6

)

T1_L

1TC

LKA

(5,1

7,18

)

IRQ

3B(3

,7,8

,17,

18)T1

A_C

S~(1

1)

WR

_B(8

,11)

RST

_T1A

(11)

T1_L

1RC

LKA_

___E

THTX

CK_

SW3

(5,1

7,18

)

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

....

L33

PE-6

5854

12345 6 7 8

C25

0

.01u

F

C24

7

0.1u

F

C24

50.

1uF

L35

3 pi

n FB

13

2

C24

8

0.1u

F

C23

6

0.1u

F

+

C23

910

uF16

V

C24

9

0.1u

F

C25

1

.01u

F

U36

BD

S215

5L18 31 83816144

302419 8480604520R

VDD

TVD

D

DVD

D4

DVD

D3

DVD

D2

DVD

D1

RVS

S4R

VSS3

RVS

S1

DVS

S4D

VSS3

DVS

S2D

VSS1

RVS

S2

C24

2.0

1uF

+C

246

68uF

20V

R10

947

0

C25

2

.01u

F

L34

3 pi

n FB

13

2

R11

551

.1

D33

MM

BD91

4LT1

13

R11

110

.0K

C24

1.0

1uF

R10

74.

7

R11

210

.0K

R10

84.

7

D34

MM

BD91

4LT1

13

JP9

Jum

per .

2TH

12

C23

80.

1uF

L36

3 pi

n FB

13

2

J22

RJ4

5Sh

ield

ed

8 7 6 5 4 3 2 19 10

P8 P7 P6 P5 P4 P3 P2 P1GN

DA

GN

DB

C24

40.1

uF

U36

AD

S215

5L

37 9856 57 58 59 62 63 64 6566 67 68 69 70 71 72 73

85

99

221

6

35 4838 39 50

47

42 43 90 9186 87 16 17 2140 4651 88 100

11 12 1452 55

74 7775

3 13

41

53 79

82

89 9225

29 3233 34 49 78 93 94

95

96 97

2 4 5 7 8 910 15 23 36 54 76 26 27 28

TSYN

C

RSY

NC

D0/

AD0

D1/

AD1

D2/

AD2

D3/

AD3

D4/

AD4

D5/

AD5

D6/

AD6

D7/

AD7

A0 A1 A2 A3 A4 A5 A6 ALE(

AS)/A

7

RD

ATA

RLO

S/LO

TC

XTAL

D

RC

HBL

K

RC

L

TLIN

K

TSIG

TPO

SITN

EGI

TDAT

A

TSER

TNEG

OTP

OSO

RN

EGO

RPO

SO

RPO

SIR

NEG

I

RTI

P

RR

ING

MC

LK

TCLK

I

TCLK

TSYS

CLK

RC

LKI

RSY

SCLK

BTS

LIU

C

TSTR

ST

TSSY

NC

MU

X

RD

/DS

WR

/R/W

CS

BPC

LK8X

CLK

TCLK

O

TCH

CLK

RLC

LK

RC

LK

RC

LKO

RC

HC

LKIN

T

TTIP

TRIN

G

TCH

BLK

TLC

LK

TESO

RLI

NK

RSI

GF

RSI

G

RSE

R

RM

SYN

CR

FSYN

C

JTM

SJT

CLK

JTR

ST

JTD

I

UO

P0U

OP1

JTD

O

UO

P2U

OP3

ESIB

S0ES

IBS1

ESIB

RD

NC

NC

NC

U37

2.04

8MH

z50

PPM

123

4N

CG

ND

OU

TVD

D

R11

451

.1

..

.

..

..

T2 PE-6

5865

143 2

161 678

9 10 11

C23

7.4

7uF

MPF

100V

10%

L32

3 pi

n FB

13

2

R11

310

.0K

D36

MM

BD91

4LT1

13

D35

MM

BD91

4LT1

13

C24

30.1

uF

+

C24

010

uF16

V

R11

047

0

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BDM

SIG

NALS

T11

P19

T5 U12

DU

ET A

DS

A

Logi

c A

naly

zer

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1725

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

D0

D1

D2

D3

D4

D5

D6

D7

D8

D10

D11

D15

D9

D14

D12

D13

D28

D17

D18

D24

D16

D25

D21

D29

D26

D27

D19

D20

D30

D31

D23

D22

A31

A25

A14

A23

A5A2

A20

A9A0 A10

A30

A24

A22

A1

A19

A8

A17

A29

A18

A21

A13

A27

A7

A28

A4 A12

A15

A26

A6A3

A16

A11

PA12

PC4

PC8

PC7

PA6

PA5

PA9

PA13

PA2

PC6

PA11

PA7

PC5

PA3

PC9

PA14

PA8

PC12

PC10

PC11

PA4

PC14

PA1

PA0

PC15

PA10

PC13

PA15

PB22

PB14

PB30

PD14

PD10

PD15

PB25

PD11

PB29

PB19

PD7

PB18

PD9

PB15

PD6

PB31

PB26

PD3

PB23

PD4

PB17

PD12

PB16

PB20

PB21

PD5

PB24

PB28

PD13

PB27

PD8

PE31

PE18

PE29

PE20

PE19

PE27

PE14

PE17

PE23

PE15

PE26

PE25

PE28

PE22

PE24

PE16

PE21

PE30

PP_A

D[7

:0]

PP_A

D3

PP_A

D6

PP_A

D4

PP_A

D1

PP_A

D5

PP_A

D2

PP_A

D7

PP_A

D0

MO

DC

K1(3

,24)

A[0:

31]

(2,3

,4,2

4)D

[0:3

1](2

,3,4

)

REG

Ab(3

,10)

TSIZ

1(3

)

DR

MC

S1b

(3,2

4)

TEAb

(3,4

)

WE0

b(2

,3,4

,11)

WE2

b(2

,3,4

)

FCSb

(3,2

4)

WE3

b(2

,3,4

)

BS3A

b(3

)

CS5

b(3

,11,

24)

BS0A

b(3

,18)

BCSR

CSb

(3,2

4)

WE1

b(2

,3,4

)G

PL5B

b(3

,18)

VF1

(3)

BGb

(3)

AT0

(3)

BRb

(3)

VF0

(3)

VF2

(3)

AT3

(3)VF

LS0

(3,1

5)

BUR

ST(3

)

VFLS

1(3

,15)

BIb

(3)

TSb

(3,4

,11)

RW

b(3

,4,1

1,18

)

BBb

(3)

TAb

(3,1

1,18

,24)

AT2

(3)

CS7

b(3

,18,

24)

CS6

b(3

,18,

24)

BS1A

b(3

)BS

2Ab

(3)

BCE1

Ab(3

,4,1

8,24

)

BRES

ETA_

___A

TM_R

XCLK

_SW

4(3

,6,9

,18)

TEXP

(3)

BWAI

TAb_

___A

TM_R

XSO

C_S

W4

(3,6

,18)

SRES

ETb

(3,1

5,18

,24)

IRQ

2b(3

,18)

HR

ESET

b(3

,11,

15,1

8,24

)

AT1

(3)

ALEA

(3,4

)

MO

DC

K1(3

,24)

GPL

4Ab

(3,1

8)

POEA

b(3

,4)EX

TCLK

(3)

RPO

RIb

(3,1

1,14

,15,

18)

SPKR

OU

T(3

,10)

WAI

TBb

(3)

IRQ

3b(3

,7,8

,16,

18)

RST

CN

Fb(3

,24)

MO

DC

K2(3

,24)

GPL

4Bb

(3,1

8)

T1_L

1TXD

A___

_ETH

RX

D_S

W3

(5,6

,18)

PC14

(5,1

4,18

)USB

RXN

(5,6

,18)

GPL

5Ab

(3,1

8)

GPL

2b(2

,3,4

)R

/MIIR

XDV-

1(5

,18,

21)

PC8

(5,1

4,18

)T1

_L1R

XDA_

___E

THTX

D_S

W3

(5,6

,18)

OE~

(2,3

,4,1

1)

R/M

IIRXD

0-1

(5,1

8,21

)

ATM

_RXC

LAV

(5,6

,10,

18)

nUSB

OE

(5,1

8,23

)

R/M

IIRXD

1-1

(5,1

8,21

)

T1_L

1RSY

NC

A___

_ETH

CR

S_SW

3(5

,6,1

8)T1

_L1T

CLK

A(5

,16,

18)

USB

TXP

(5,1

8,23

)

DR

MW

b(2

,3,4

)

CLK

2(5

,18,

23)

BCE2

Ab(3

,4,1

8,24

)

USB

TXN

(5,1

8,23

)

GPL

3b(2

,3,4

)

T1_L

1TSY

NC

A___

_ETH

CO

L_SW

3(5

,6,1

8)

R/M

IITXD

3-1

(5,1

8,21

)

R/M

IITXD

0-1

(5,1

8,21

)

R/M

IIRXE

RR

-1(5

,18,

21)

PC9

(5,1

4,18

)

IRD

TXD

(5,1

8,19

)

R/M

IITXE

RR

-1(5

,18,

21)

T1_L

1RC

LKA_

___E

THTX

CK_

SW3

(5,1

6,18

)

IRD

RXD

(5,6

,18)

USB

RXD

(5,6

,18)

R/M

IITXD

2-1

(5,1

8,21

)U

SBR

XP(5

,6,1

8)

BSYS

CLK

4(1

9)

BRD

Y___

_ATM

_RXD

7_SW

4(3

,6,1

8)BB

VD2_

___A

TM_R

XD6_

SW4

(3,6

,18)

BCD

1b__

__AT

M_R

XD4_

SW4

(3,6

,18)

BBVD

1___

_ATM

_RXD

5_SW

4(3

,6,1

8)

BWP_

___A

TM_R

XD2_

SW4

(3,6

,18)

BCD

2b__

__AT

M_R

XD3_

SW4

(3,6

,18)

BVS2

____

ATM

_RXD

1_SW

4(3

,6,1

8)BV

S1__

__AT

M_R

XD0_

SW4

(3,6

,18)

R/M

IITXD

1-1

(5,1

8,21

)

SDR

MC

Sb(2

,3)

DR

MC

S2b

(3,2

4)

ATM

_RXA

DD

R0

(5,7

,8,9

,18)

IRQ

1b(3

,18)

ATM

_TXS

OC

(5,7

,8,9

,18)

ATM

_TXA

DD

R1

(5,7

,8,9

,18)

PB27

(5,1

8)

ATM

_TXD

5(5

,7,8

,9,1

8)

PB29

(5,1

4,18

)

ATM

_TXC

LK(5

,9,1

8)

ATM

_TXD

2(5

,7,8

,9,1

8)

R/M

IIRXD

3-1

(5,1

8,21

)

IRQ

7b(3

,18)

ATM

_TXA

DD

R0

(5,7

,8,9

,18)

PB28

(5,1

4,18

)

MPC

MD

C(5

,18,

20,2

1,22

)AT

M_T

XAD

DR

4(5

,7,8

,9,1

8)

ATM

_RXE

N(5

,7,8

,9,1

8)

ATM

_TXD

7(5

,7,8

,9,1

8)

ATM

_TXD

3(5

,7,8

,9,1

8)

RSR

XD1_

___A

TM_T

XAD

DR

3_SW

1(5

,6,1

8)

ATM

_TXD

6(5

,7,8

,9,1

8)

PB30

(5,1

8)

NM

Ib(3

,18,

24)

PB26

(5,1

8)

RSD

TR1b

____

ATM

_TXA

DD

R2_

SW1

(5,6

,18)

R/M

IITXC

LK-1

(5,1

8,21

)

ATM

_TXD

4(5

,7,8

,9,1

8)

RST

XD1_

___A

TM_R

XAD

DR

3_SW

1(5

,6,1

8)AT

M_T

XEN

(5,7

,8,9

,18) AT

M_T

XCLA

V(5

,6,1

8)

ATM

_RXA

DD

R1

(5,7

,8,9

,18)

ATM

_TXD

0(5

,7,8

,9,1

8)AT

M_R

XAD

DR

2(5

,7,8

,9,1

8)

ATM

_RXA

DD

R4

(5,7

,8,9

,18)

ATM

_TXD

1(5

,7,8

,9,1

8)

BDM

_DSC

K(1

5)BD

M_D

SDI

(15)

EPP_

CLK

(15)

BDM

_DSD

O(1

5)PP

_DST

Rb

(15)

PP_W

Eb(1

5)

PP_R

STb

(15)

PP_V

FLSP

0(1

5)

PP_A

STR

b(1

5)

R/M

IIRXC

LK-1

(5,1

8,21

)R

/MIIC

RS-

1(3

,21)

MPC

MD

IO(3

,18,

20,2

1,22

)R

/MIIT

XEN

-1(3

,21)

R/M

IICO

L-1

(3,2

1)

CLK

6(5

,6,1

8)

R/M

IITXD

3-2

(5,1

8,22

)

R/M

IIRXD

0-2_

___R

SRXD

2_SW

2(5

,6,1

8)

R/M

IITXE

N-2

(5,1

8,22

)

CLK

5(5

,6,1

8)

R/M

IITXD

0-2

(5,1

8,22

)R

/MIIT

XD1-

2(5

,18,

22)

R/M

IITXE

RR

-2__

__R

STXD

2_SW

2(5

,6,1

8)

R/M

IIRXD

V-2

(5,1

8,22

)R

/MIIR

XD3-

2(5

,18,

22)

R/M

IICO

L-2

(5,1

8,22

)

R/M

IIRXC

LK-2

____

RSD

TR2b

_SW

2(5

,6,1

8)

R/M

IICR

S-2

(5,1

8,22

)

R/M

IIRXE

RR

-2__

__ET

HTX

EN_S

W3

(5,6

,18)

R/M

IIRXD

2-1

(5,1

8,21

)

R/M

IIRXD

2-2

(5,1

8,22

)

R/M

IIRXD

1-2

(5,1

8,22

)

RPO

RIb

(3,1

1,14

,15,

18)SR

ESET

b(3

,15,

18,2

4)VF

LS1

(3,1

5)VF

LS0

(3,1

5)PP

_VFL

SP1

(15)

PP_I

NTb

(15)

FRZ

(3,1

8)

PP_B

USY

_OU

T(1

5)

PP_A

D[7

:0]

(15)

HR

ESET

b(3

,11,

15,1

8,24

)

TP69

TP72

TP55

TP71

TP56

TP64

TP73

TP57

TP68

TP70

TP58

J30 2

x 19

Rec

epta

cle

MIC

TOR

VER

T

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

J28

2 x

19 R

ecep

tacl

eM

ICTO

R V

ERT

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

J26

2 x

19 R

ecep

tacl

eM

ICTO

R V

ERT

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

TP59

J25

2 x

19 R

ecep

tacl

eM

ICTO

R V

ERT

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

TP61

TP65

TP67

TP63

TP60

TP66

TP62

J23

2 x

19 R

ecep

tacl

eM

ICTO

R V

ERT

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

J27

2 x

19 R

ecep

tacl

eM

ICTO

R V

ERT

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

J24

2 x

19 R

ecep

tacl

eM

ICTO

R V

ERT

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

J29

2 x

19 R

ecep

tacl

eM

ICTO

R V

ERT

383634

37353331292725232119171513119753

3230282622201816141086421

243940414243 12

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FRO

M B

CSR

CPM

signals

CPU

signals

Center

Bottom

Top

Center

Bottom

Top

DU

ET A

DS

A

Expa

nsio

n C

onne

ctor

s

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1825

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

PB27

PC11

PC12

EXP_

BD[0

:7]

PC6PB

29

BA30

PB18

PC13PB

21

PC15PB

14

BA19

PB24

PC4

EXP_

A[16

:31]

PC7PB

20

PB26

PC9PB

15

PB30

PB31

BA25

BA28

BA26

PB19

PB16

PC8

PC10PB

28

BA24

BA[1

6..3

1]

PB17

PB25

PB23

BA29

PC14

PC5

BA31

BA18

PB22

EXP_

A25

EXP_

A18

EXP_

A16

EXP_

A26

EXP_

A19

EXP_

A17

EXP_

A27

EXP_

A24

IPA5

IPA6

IPA2

IPA3

IPA0

BWAI

TA

IPA1

IPA7

EXP_

A24

EXP_

A16

EXP_

A18

EXP_

A17

EXP_

A30

EXP_

A27

EXP_

A31

EXP_

A21

EXP_

A19

EXP_

A22

EXP_

A25

EXP_

A23

EXP_

A29

EXP_

A28

EXP_

A20

EXP_

A26

PA6

PD15

PA7

PD14

PD4

PA13

PA1

PD6

PA0

PD13

PA5

PA10

PA12

PD12

PA15

PA3

PD3

PA14

PA4

PD8

PA2

PD5

PA8

PA9

PA11

PD7

PD9

PD10

PD11

PE14

PE15

PE16

PE18

PE17

PE19

PE21

PE20

PE22

PE24

PE23

PE25

PE27

PE26

PE28

PE30

PE29

PE31

IPA4

EXP_

A21

EXP_

A20

EXP_

A22

EXP_

A23

EXP_

A29

EXP_

A30

EXP_

A28

EXP_

A31

BA23

BA21

BA22

BA16

BA17

BA20

BA27

BD0

EXP_

BD7

EXP_

BD6

BD2

EXP_

BD3

BD[0

..7]

EXP_

BD3

EXP_

BD0

EXP_

BD2

EXP_

BD5

EXP_

BD4

BD7

EXP_

BD5

EXP_

BD2

EXP_

BD1

BD6

BD4

EXP_

BD0

BD5

BD1

EXP_

BD1

EXP_

BD7

EXP_

BD4

EXP_

BD6

BD3

EXP_

DIR

EXP_

OEb

ATM

_TXC

LAV

(5,6

,17)

PB27

(5,1

7)

PC8

(5,1

4,17

)

RSR

XD1_

___A

TM_T

XAD

DR

3_SW

1(5

,6,1

7)

ATM

_RXA

DD

R0

(5,7

,8,9

,17)

PC9

(5,1

4,17

)

RST

XD1_

___A

TM_R

XAD

DR

3_SW

1(5

,6,1

7)

ATM

_RXA

DD

R1

(5,7

,8,9

,17)

USB

RXP

(5,6

,17)

PB26

(5,1

7)

ATM

_RXA

DD

R4

(5,7

,8,9

,17)

R/M

IITXD

2-1

(5,1

7,21

)

USB

RXN

(5,6

,17)

BA[1

6..3

1](2

,4,1

0,11

,24)

PB28

(5,1

4,17

)

T1_L

1RSY

NC

A___

_ETH

CR

S_SW

3(5

,6,1

7)

R/M

IIRXD

3-1

(5,1

7,21

)

R/M

IITXD

3-1

(5,1

7,21

)

BD[0

..7]

(2,4

,10,

11,2

4)

PB29

(5,1

4,17

)

T1_L

1TSY

NC

A___

_ETH

CO

L_SW

3(5

,6,1

7)

ATM

_TXA

DD

R0

(5,7

,8,9

,17)

PC14

(5,1

4,17

)AT

M_R

XCLA

V(5

,6,1

0,17

)

PB30

(5,1

7) USB

TXN

(5,1

7,23

)

ATM

_TXA

DD

R1

(5,7

,8,9

,17)

ATM

_RXA

DD

R2

(5,7

,8,9

,17)

R/M

IITXC

LK-1

(5,1

7,21

)

USB

TXP

(5,1

7,23

)

ATM

_TXA

DD

R4

(5,7

,8,9

,17)

RSD

TR1b

____

ATM

_TXA

DD

R2_

SW1

(5,6

,17)

EXP_

OEb

(24)

GPL

5Ab

(3,1

7)BDR

MW

b(4

)

BS0A

b(3

,17)

BBVD

1___

_ATM

_RXD

5_SW

4(3

,6,1

7)

GPL

4Bb

(3,1

7)

BRES

ETA_

___A

TM_R

XCLK

_SW

4(3

,6,9

,17)

BVS1

____

ATM

_RXD

0_SW

4(3

,6,1

7)

GPL

4Ab

(3,1

7)

TAb

(3,1

1,17

,24)

CS6

b(3

,17,

24)

BBVD

2___

_ATM

_RXD

6_SW

4(3

,6,1

7)

BED

OO

Eb(4

)

BVS2

____

ATM

_RXD

1_SW

4(3

,6,1

7)

CS7

b(3

,17,

24)BR

W2b

(4,2

4)

BRD

Y___

_ATM

_RXD

7_SW

4(3

,6,1

7)

BTSb

(4)

BWP_

___A

TM_R

XD2_

SW4

(3,6

,17)

BGPL

2b(4

)

GPL

5Bb

(3,1

7)

BWAI

TAb_

___A

TM_R

XSO

C_S

W4

(3,6

,17)

BCD

2b__

__AT

M_R

XD3_

SW4

(3,6

,17)

BWE0

b(2

,4,1

0) BSYS

CLK

3(1

9)

BGPL

3b(4

)USB

RXD

(5,6

,17)

CLK

2(5

,17,

23)IR

DTX

D(5

,17,

19)

R/M

IIRXE

RR

-1(5

,17,

21)

T1_L

1TC

LKA

(5,1

6,17

)

R/M

IIRXD

0-1

(5,1

7,21

)

ATM

_TXD

0(5

,7,8

,9,1

7)AT

M_T

XD1

(5,7

,8,9

,17)R

/MIIR

XDV-

1(5

,17,

21)

R/M

IIRXD

1-1

(5,1

7,21

)

IRD

RXD

(5,6

,17) R/M

IITXD

1-1

(5,1

7,21

)

ATM

_TXD

2(5

,7,8

,9,1

7)

T1_L

1RC

LKA_

___E

THTX

CK_

SW3

(5,1

6,17

)

nUSB

OE

(5,1

7,23

)

ATM

_TXS

OC

(5,7

,8,9

,17)

ATM

_TXD

7(5

,7,8

,9,1

7)AT

M_T

XD6

(5,7

,8,9

,17)

ATM

_TXD

5(5

,7,8

,9,1

7)R/M

IITXE

RR

-1(5

,17,

21)

T1_L

1TXD

A___

_ETH

RX

D_S

W3

(5,6

,17)

T1_L

1RXD

A___

_ETH

TXD

_SW

3(5

,6,1

7)

R/M

IITXD

0-1

(5,1

7,21

)

ATM

_TXD

4(5

,7,8

,9,1

7)

ATM

_TXC

LK(5

,9,1

7)AT

M_T

XEN

(5,7

,8,9

,17)

ATM

_RXE

N(5

,7,8

,9,1

7)AT

M_T

XD3

(5,7

,8,9

,17)

R/M

IITXD

0-2

(5,1

7,22

)R

/MIIT

XD1-

2(5

,17,

22)

CLK

6(5

,6,1

7)C

LK5

(5,6

,17)

R/M

IITXD

3-2

(5,1

7,22

)R

/MIIT

XEN

-2(5

,17,

22)

R/M

IITXE

RR

-2__

__R

STXD

2_SW

2(5

,6,1

7)R

/MIIR

XD0-

2___

_RSR

XD2_

SW2

(5,6

,17)

R/M

IIRXD

1-2

(5,1

7,22

)R

/MIIR

XCLK

-2__

__R

SDTR

2b_S

W2

(5,6

,17)

R/M

IIRXD

2-2

(5,1

7,22

)R

/MIIR

XD3-

2(5

,17,

22)

R/M

IIRXD

V-2

(5,1

7,22

)R

/MIIR

XER

R-2

____

ETH

TXEN

_SW

3(5

,6,1

7)R

/MIIC

OL-

2(5

,17,

22)

R/M

IICR

S-2

(5,1

7,22

)R/M

IIRXD

2-1

(5,1

7,21

)R/M

IIRXC

LK-1

(5,1

7,21

)

BCD

1b__

__AT

M_R

XD4_

SW4

(3,6

,17)

IRQ

7b(3

,17)

IRQ

2b(3

,17)

IRQ

3b(3

,7,8

,16,

17)

NM

Ib(3

,17,

24)

FRZ

(3,1

7) IRQ

1b(3

,17) M

PCM

DIO

(3,1

7,20

,21,

22)

MPC

MD

C(5

,17,

20,2

1,22

)

SRES

ETb

(3,1

5,17

,24)

HR

ESET

b(3

,11,

15,1

7,24

)

BCE2

Ab(3

,4,1

7,24

)BA

LEA

(4,1

0)

BCE1

Ab(3

,4,1

7,24

)

RPO

RIb

(3,1

1,14

,15,

17)

SW_M

OD

CK1

(3,2

4)SW

_MO

DC

K2(2

4)

RW

b(3

,4,1

1,17

)

MPC

MD

C(5

,17,

20,2

1,22

)

V3U

3

V3U

3

V3U

3

VCC

VCC

VPPI

N

V3U

3

V3U

3

J32B

3x32

Fem

ale

Euro

0.1

CTR

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

C26

00.

1uF

U38

B74

LVC

HR

1622

45A

4 10 15 21 28 34 39 45

7 18 31 42

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

C25

30.

1uF

U39

A74

LVC

H16

2244

47 46 44 43 141 40 38 37 48 36 35 33 32 2530 29 27 26 24

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

1A0

1A1

1A2

1A3

OE1

2A0

2A1

2A2

2A3

OE2

3A0

3A1

3A2

3A3

OE3

4A0

4A1

4A2

4A3

OE4

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

3Y0

3Y1

3Y2

3Y3

4Y0

4Y1

4Y2

4Y3

C25

40.

1uF

C25

50.

1uF

J31B

3x32

Fem

ale

Euro

0.1

CTR

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

C25

60.

1uF

J32A

3x32

Fem

ale

Euro

0.1

CTR

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

J32C

3x32

Fem

ale

Euro

0.1

CTR

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32 D

1D

2

J31C

3x32

Fem

ale

Euro

0.1

CTR

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32 D

1D

2

R11

61.

00K

C25

70.

1uF

C25

80.

1uF

J31A

3x32

Fem

ale

Euro

0.1

CTR

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

U38

A74

LVC

HR

1622

45A

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 261 2448 25

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

DIR

1

DIR

2

OE1

OE2

U39

B74

LVC

H16

2244

4 10 15 21 28 34 39 45

7 18 31 42

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

C25

90.

1uF

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Clock Generator is the source

Capacitor-Resistor located in the end of the trace

1 6 2 7 3 8 4 9 5

NO LOAD

NO LOAD

NO LOAD

NO LOAD

NO LOAD

NO LOAD

IRD

TXD

INFR

A-R

ED P

OR

T

IRD

ENb

NO

LO

AD

IRD

RX

D

NO

LO

AD

Plac

e C

284,

C28

5 ne

ar U

43

DU

ET A

DS

A

RS2

32, I

nfra

Red

, Sys

CLK

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

1925

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

SYSC

LK_C

HIP

_PW

R

RSE

N1b

(14,

24)

RSE

N2b

(14,

24)

SW1_

RSR

XD1

(6) SW

1_R

SDTR

1b(6

)

SW2_

RSR

XD2

(6) SW

2_R

SDTR

2b(6

)

SYSC

LK(3

)

BSYS

CLK

2(2

)BS

YSC

LK3

(18)

CLK

1(2

4)

BSYS

CLK

4(1

7)

BSYS

CLK

1(1

1)

SW1_

RST

XD1

(6)

SW2_

RST

XD2

(6)

IRD

ENb

(14,

24)

SW5_

IRD

RXD

(6)

IRD

TXD

(5,1

7,18

)

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

R12

810

0

C26

81n

F1.

5KV

1 2

L40

FB1

2

L47

3 pi

n FB

13

2

C27

61n

F1.

5KV

1 2

C28

712

0pF

C0G

RP1

8

4x22

1 2 3 45678

C26

20.

1uF

R13

12.

00K

RS-

232

PHY

RS-232 Levels

TTLLevels

U41

MAX

3241

ECAI

28 2524 1 2

27 326

14 13 12

9 10 11

21 20 19 18 17 16 15 23

4 5 6 7 8

22

C1+

DG

ND

C1-

C2+

C2-

V+ V-

VCC

T1IN

T2IN

T3IN

T1O

UT

T2O

UT

T3O

UT

R1O

UTB

R2O

UTB

R1O

UT

R2O

UT

R3O

UT

R4O

UT

R5O

UT

EN

R1I

NR

2IN

R3I

NR

4IN

R5I

N

SHD

N

R12

347

C26

91n

F1.

5KV

1 2

L41

FB1

2

+C

281

10uF

16V

U43

GP2

W00

04YP

2 3 4

5

1

6

TxD

RxD

SD/M

OD

E

VCCIN

A

GN

D

C27

50.

1uF

C28

812

0pF

C0G

C26

40.

1uF

C27

01n

F1.

5KV

1 2

C28

20.

1uF

RP1

9

4x22

1 2 3 45678

J33A

RS2

32 D

B9

A5A9A4A8A3A7A2A6A1 A10

A11

R12

42.

00K

C26

30.

1uF

L43

FB1

2

C27

10.

1uF

C28

912

0pF

C0G

C26

61n

F1.

5KV

1 2

C28

3.0

1uF

L44

FB1

2

U42

AC

Y230

9

2 3 14 15 6 7 10 11 16

91 8

CLK

A1C

LKA2

CLK

A3C

LKA4

CLK

B1C

LKB2

CLK

B3C

LKB4

CLK

OU

T

S1REF

S2

R13

0

33.2

R12

110

.0K

L46

FB1

2

RS-

232

PHY

RS-232 Levels

TTLLevels

U40

MAX

3241

ECAI

28 2524 1 2

27 326

14 13 12

9 10 11

21 20 19 18 17 16 15 23

4 5 6 7 8

22

C1+

DG

ND

C1-

C2+

C2-

V+ V-

VCC

T1IN

T2IN

T3IN

T1O

UT

T2O

UT

T3O

UT

R1O

UTB

R2O

UTB

R1O

UT

R2O

UT

R3O

UT

R4O

UT

R5O

UT

EN

R1I

NR

2IN

R3I

NR

4IN

R5I

N

SHD

N

C28

01n

F1.

5KV

1 2

C29

012

0pF

C0G

C28

612

0pF

C0G

C26

71n

F1.

5KV

1 2

C28

40.

1uF

L42

FB1

2C

272

0.1u

F

J33B

RS2

32 D

B9

B5B9B4B8B3B7B2B6B1 B10

B11

R27

610

.0K

C27

71n

F1.

5KV

1 2

L45

FB1

2

R12

510

0

L37

FB1

2

R27

510

.0K

U42

B

CY2

309

4125

13VD

DG

ND

GN

DVD

D

C27

40.

1uF

C26

50.

1uF

C27

81n

F1.

5KV

1 2R

126

100

R11

910

.0K

C29

112

0pF

C0G

R12

010

.0K

L38

FB1

2

C27

30.

1uF

R12

710

0

C26

10.

1uF

C27

91n

F1.

5KV

1 2

R12

210

.0K

L39

FB1

2

R12

910

0+

C28

54.

7uF

10V

1 2

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MPC

MD

C

Tx /

Rx

ETH

CO

L

FDX

ETH

RXC

K

LIN

K

IRQ

3b_I

RQ

7b

MIR

RXD

0

ETH

TXEN

nETH

RST

ETH

TXD

MPC

MD

IO

ETH

TXC

K

ETH

CR

S

PHY

ADDR

ESS

TABL

E

ARJ1

FAST

ETH

ERN

ET1

- PH

Y A

DD

RESS

000

10

RJ2

RJ3

RJ4

RJ5

BB

BB

DU

ET A

DS

A

10B

aseT

ETH

ERN

ET G

PSI

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

2025

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

ETH

RXE

NN

OR

MAL

ETH

RXE

R

CO

L

PHY3

AD2

PHY3

AD3

SCR

M3

ISO

LATE

_TE3

PHY3

AD1

PHY3

AD4

PHY3

AD0

MPC

MD

IO(3

,17,

18,2

1,22

)SW3_

ETH

TXEN

(6)

MPC

MD

C(5

,17,

18,2

1,22

)

GPS

ICLK

(21)nE

THR

ST(2

4)SW3_

ETH

TXD

(6) SW

3_ET

HR

XD0

(6)

IRQ

3b_I

RQ

7b(3

,21,

22)SW

3_ET

HTX

CK

(6)

SW3_

ETH

RXC

K(6

)

SW3_

ETH

CO

L(6

)SW

3_ET

HC

RS

(6)

ETH

ENb

(14,

24)

AVD

TT1

A

A

A

V3U

3

V3U

3

A

AVD

TT1

AVD

TT1

A

A

V3U

3

V3U

3

V3U

3

C30

50.

1uF

R15

433

0

R14

675

R13

710

.0K

R15

710

.0KB

A

RJ1

10K

1

2

3

+C

298

10uF

16V

C29

50.

1uF

R13

822

R15

315

0R

152

10K

D38 HSM

Y-C

650

Yello

w

C30

10.

1uF

R15

015

0

R13

922

L48

NFM

60R

13

2

R15

110

K

R14

810

K

C29

20.

1uF

R14

375

J34 R

J45

Shie

lded

8 7 6 5 4 3 2 19 10


DA

GN

DB

R14

06.

81K

C30

00.

1uF

R14

475

***

** *

* *

**

**

NC

1N

C2

T3 TG22

-350

6

1 235 67 10 1112

14 1516 8 9

R13

349

.9

+C

297

10uF

16V

BA

RJ5

10K

1

2

3

R14

178

.7

C30

20.

1uF

C30

40.

1uF

R14

70

D37 H

SMH

-C65

0R

ed

C29

40.

1uF

R13

249

.9

R14

910

K

U44

AD

M91

61

16 17 18 19 20 21 22 38 26 27 28 29 37 31 34 24 25 32 14 36 35 40 10 45

4 3 8 7 48 47 11 12 13 42 43

TXER

/TXD

4TX

D3

TXD

2TX

D1

TXD

0

TXEN

TXC

LK/IS

OLA

TE

RXE

R/R

XD4/

RPT

RR

XD3/

PHYA

D3

RXD

2/PH

YAD

2R

XD1/

PHYA

D1

RXD

0/PH

YAD

0

RXD

V/TE

STM

OD

ER

XEN

RXC

LK/S

CR

AMEN

/10B

TSER

MD

CM

DIO

MD

INTR

CAB

STS/

LIN

KSTS

CO

L/R

MII

CR

S/PH

YAD

4

RES

ETPW

RD

WN

SD

RX-

/FXR

D-

RX+

/FXR

D+

TX-/F

XTD

-

TX+/

FXTD

+

BGR

ES

BGR

ESG

FDX/

CO

L/O

P0SP

EED

/OP1

LIN

K/AC

T/O

P2 XT2

XT1

BA

RJ4

10K

1

2

3

R13

410

.0K

R15

510

.0K

R14

575

C30

30.

1uF

R13

510

.0K

BA

RJ3

10K

1

2

3

C29

30.

1uF

R15

610

.0K

C29

610

00pF

2KV

20%

C29

90.

1uF

R14

278

.7

D39

HSM

G-C

650

Gre

en

R13

610

.0K

RP2

04x

22

12345 6 7 8

U44

BD

M91

61

15 33 44

23 30 39 41

5 6 46

1 2 9

DG

ND

1D

GN

D2

DG

ND

3

DVD

D1

DVD

D2

DVD

D3

DVD

D4

AGN

DR

AGN

DT

AGN

DS

AVD

DR

1AV

DD

R2

AVD

DT

BA

RJ2

10K

1

2

3

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MPC

MD

C

Tx /

Rx

LIN

K

*

25M

Hz

* Not used in RMII mode

** Only used during power up in RMII mode

** No data transfer in RMII mode

*

100M

bps

R/M

IICR

S-1

R/M

IICO

L-1

*R

/MIIT

XD3-

1

25M

Hz

**

R/M

IITXE

N-1

RST

R/M

IIb-1

FDX

50M

Hz

** **

R/M

IIRXD

2-1

**

R/M

IIRXE

RR

-1

*

R/M

IIRXD

1-1

FAST

ETH

ERN

ET1

- PH

Y A

DD

RESS

000

00

*

R/M

IITXD

0-1

R/M

IITXD

2-1

R/M

IITXD

1-1

25M

Hz

R/M

IIRXC

LK-1

IRQ

3

R/M

IIRXD

3-1

R/M

IIRXE

NC

-1

R/M

IIRXD

V-1

R/M

IITXE

RR

-1

R/M

IIRXD

0-1

MPC

MD

IO

50M

Hz

B

PHY

ADDR

ESS

TABL

ERJ10

RJ8

RJ7

RJ9

BB

BRJ6

B

RJ12

PHY

CLOC

K TA

BLE

B*

RJ11

B*

AA

CLK

25MHZ

MII

50MHZ

RMII

* =

defa

ult

R/M

IITXC

LK-1

MII

RMII

DU

ET A

DS

A

FAST

ETH

ERN

ET R

/MII

#1

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

2125

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

PHY1

AD0-

1

nMD

INTR

1SC

RM

1

PHY1

AD3-

1R

PTR

1

PHY1

AD2-

1

MIIC

LK1

TEST

MO

D1

RM

IICLK

1

50M

HZ_

CLK

_VD

D

25M

HZ_

CLK

_VD

D

ISO

LATE

1

PHY1

AD4-

1

PHY1

AD1-

1

RM

II1

RM

IICLK

2(2

2)

MIIC

LK2

(22)

GPS

ICLK

(20)

R/M

IITXD

3-1

(5,1

7,18

)

R/M

IITXD

0-1

(5,1

7,18

)R

/MIIT

XD1-

1(5

,17,

18)R

/MIIT

XER

R-1

(5,1

7,18

)

R/M

IICO

L-1

(3,1

7)

R/M

IIRXD

0-1

(5,1

7,18

)R

/MIIR

XDV-

1(5

,17,

18)

R/M

IICR

S-1

(3,1

7)

R/M

IIRXD

3-1

(5,1

7,18

)R/M

IIRXE

RR

-1(5

,17,

18)

R/M

IIRXD

2-1

(5,1

7,18

)R

/MIIR

XD1-

1(5

,17,

18)

R/M

IITXE

N-1

(3,1

7)R/M

IIRXC

LK-1

(5,1

7,18

)

R/M

IIRXE

NC

-1(1

1,14

)

MPC

MD

IO(3

,17,

18,2

0,22

)

MPC

MD

C(5

,17,

18,2

0,22

)

IRQ

3b_I

RQ

7b(3

,20,

22)

RST

R/M

IIb-1

(11)

R/M

IITXD

2-1

(5,1

7,18

)

R/M

IITXC

LK-1

(5,1

7,18

)

R/M

II-2

(22)

V3U

3

A

V3U

3

AVD

TT2

V3U

3

V3U

3

A

V3U

3

V3U

3

V3U

3

V3U

3

A

AVD

TT2

A

A

V3U

3

A

AVD

TT2

A

A

V3U

3

V3U

3

V3U

3

V3U

3

C31

30.

1uF

J35 R

J45

Shie

lded

8 7 6 5 4 3 2 19 10


DA

GN

DB

C32

00.

1uF

R17

933

0

BAR

J12

Zero

Ohm

1 3

2

U46

E74

LCX1

257

14G

ND

VCC

BA

RJ6

10K

1

2

3

R17

075

L51

Ferri

te B

ead

640m

A

12

R18

5 0

C31

90.

1uF

U46

A

74LC

X125

23

1

C32

50.

1uF

R16

76.

81K

C31

70.

1uF

U48

50.0

MH

z50

PPM

123

4N

C/E

DG

ND

OU

TVD

D

RP2

14x

221 2 3 4

5678

R18

7 0

C32

60.

1uF

RP2

24x

22

12345 6 7 8

C32

310

00pF

2KV

20%

U47

A

74LC

X125

23

1

C31

60.

1uF

R18

6 0

R15

810

K

BA

RJ7

10K

1

2

3

U46

B

74LC

X125

56

4

C30

70.

1uF

R18

010

K

C31

50.

1uF

R17

510

K

U49

25.0

MH

z50

PPM

123

4N

C/E

DG

ND

OU

TVD

D

R18

110

.0K

R16

975

C30

60.

1uF

C32

210

00pF

2KV

20%

BA

RJ2

410

K

1

2

3

R18

8 0

C31

40.

1uF

R18

91.

00K

C30

80.

1uF

R17

415

0

U47

B

74LC

X125

56

4

R18

210

.0K

R19

01.

00K

***

** *

* *

**

**

NC

1N

C2

T4 TG22

-350

6

1 235 67 10 1112

14 1516 8 9R

165

78.7

C32

10.

1uF

D43

HSM

G-C

650

Gre

en

R17

175

U45

AD

M91

61

16 17 18 19 20 21 22 38 26 27 28 29 37 31 34 24 25 32 14 36 35 40 10 45

4 3 8 7 48 47 11 12 13 42 43

TXER

/TXD

4TX

D3

TXD

2TX

D1

TXD

0

TXEN

TXC

LK/IS

OLA

TE

RXE

R/R

XD4/

RPT

RR

XD3/

PHYA

D3

RXD

2/PH

YAD

2R

XD1/

PHYA

D1

RXD

0/PH

YAD

0

RXD

V/TE

STM

OD

ER

XEN

RXC

LK/S

CR

AMEN

/10B

TSER

MD

CM

DIO

MD

INTR

CAB

STS/

LIN

KSTS

CO

L/R

MII

CR

S/PH

YAD

4

RES

ETPW

RD

WN

SD

RX-

/FXR

D-

RX+

/FXR

D+

TX-/F

XTD

-

TX+/

FXTD

+

BGR

ES

BGR

ESG

FDX/

CO

L/O

P0SP

EED

/OP1

LIN

K/AC

T/O

P2 XT2

XT1

U46

C

74LC

X125

1211

13

BA

RJ8

10K

1

2

3

R16

149

.9

L49

NFM

60R

13

2

JP10

Jum

per .

2TH

12

R16

3

22

R18

310

.0K

R17

710

K

D41 H

SMY-

C65

0Ye

llow

R17

815

0

R16

010

K U27

A

74AC

14

12

+C

311

10uF

16V

C32

70.

1uF

C31

80.

1uF

C31

010

00pF

2KV

20%

R17

615

0

R16

249

.9

R16

4

22D

42

HSM

G-C

650

Gre

en

+C

312

10uF

16V

U47

D

74LC

X125

98

10

D40 HSM

H-C

650

Red

R17

20

C32

90.

1uF

BA

RJ9

10K

1

2

3

R16

678

.7

U46

D

74LC

X125

98

10

L50

Ferri

te B

ead

640m

A

12

R17

310

K

U27

F

74AC

14

1312

U47

E74

LCX1

257

14G

ND

VCC

R15

910

K

R16

875

BAR

J11

Zero

Ohm

1 3

2

R18

4 0

U45

BD

M91

61

15 33 44

23 30 39 41

5 6 46

1 2 9

DG

ND

1D

GN

D2

DG

ND

3

DVD

D1

DVD

D2

DVD

D3

DVD

D4

AGN

DR

AGN

DT

AGN

DS

AVD

DR

1AV

DD

R2

AVD

DT

C32

40.

1uF

C30

90.

1uF

C32

80.

1uF

BA

RJ1

010

K

1

2

3

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

R/M

IITXD

3-2

R/M

IICR

S-2

*

MPC

MD

IO

R/M

IITXE

RR

-2

FAST

ETH

ERN

ET2

- PH

Y A

DD

RESS

000

01

*

IRQ

3


** Only used during power up in RMII mode

** No data transfer in RMII mode

R/M

IICO

L-2

Tx /

Rx

RST

R/M

IIb-2

R/M

IIRXD

0-2

100M

bps

* *

R/M

IIRXD

V-2

R/M

IIRXE

RR

-2

R/M

IITXD

0-2

R/M

IITXC

LK-2

R/M

IITXE

N-2

50M

Hz

**

R/M

IIRXD

3-2

**

** *

MPC

MD

C

R/M

IIRXE

NC

-2

FDX

R/M

IIRXD

1-2

*

25M

Hz

R/M

IIRXD

2-2

LIN

K

R/M

IITXD

1-2

*R

/MIIT

XD2-

2

R/M

IIRXC

LK-2

B

PHY

ADDR

ESS

TABL

ERJ19

RJ17RJ16

RJ18

BB

BA

RJ15

DU

ET A

DS

A

FAST

ETH

ERN

ET R

/MII

#2

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

2225

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

LIN

K2

RM

IICLK

2

TEST

MO

D2

MIIC

LK2

nMD

INTR

2

RPT

R2

ISO

LATE

2

PHY2

AD3

SCR

M2

PHY2

AD2

PHY2

AD0

PHY2

AD1

PHY1

AD4-

2R

MII2

MPC

MD

IO(3

,17,

18,2

0,21

)SW3_

R/M

IITXD

2-2

(6)

R/M

IITXD

1-2

(5,1

7,18

)

RM

IICLK

2(2

1)

SW2_

R/M

IITXE

RR

-2(6

)

MIIC

LK2

(21)

R/M

IITXD

0-2

(5,1

7,18

)

R/M

IITXD

3-2

(5,1

7,18

)

MPC

MD

C(5

,17,

18,2

0,21

)

R/M

IITXE

N-2

(5,1

7,18

)

R/M

IIRXD

2-2

(5,1

7,18

)

SW2_

R/M

IIRXC

LK-2

(6)

R/M

IICR

S-2

(5,1

7,18

)

SW3_

R/M

IIRXE

RR

-2(6

)

R/M

IIRXD

1-2

(5,1

7,18

)

R/M

IICO

L-2

(5,1

7,18

)R/M

IIRXD

3-2

(5,1

7,18

)

SW3_

R/M

IITXC

LK-2

(6)

SW2_

R/M

IIRXD

0-2

(6)

R/M

IIRXD

V-2

(5,1

7,18

)

IRQ

3b_I

RQ

7b(3

,20,

21) R

/MIIR

XEN

C-2

(11,

14)

RST

R/M

IIb-2

(11)

R/M

II-2

(21)R

MIIC

LK2

(21)

AVD

TT3

V3U

3V3

U3

V3U

3

AVD

TT3

A

AVD

TT3

A

A

A

V3U

3A

V3U

3

A

V3U

3

V3U

3

C33

30.

1uF

C33

410

00pF

2KV

20%

C33

20.

1uF

R20

610

K

BA

RJ1

610

K

1

2

3

D44 H

SMH

-C65

0R

ed

RP2

34x

221 2 3 4

5678

BA

RJ1

910

K

1

2

3

R19

878

.7R

201

75

R21

210

K

D45 HSM

Y-C

650

Yello

w

R19

210

K

D47

HSM

G-C

650

Gre

en

R19

549

.9

BA

RJ1

710

K

1

2

3

C33

70.

1uF

R21

010

K

***

** *

* *

**

**

NC

1N

C2

T5 TG22

-350

6

1 235 67 10 1112

14 1516 8 9

R21

410

.0K

+C

335

10uF

16V

R19

4

22

C33

00.

1uF

R20

810

K

BA

RJ1

810

K

1

2

3

R19

978

.7

RP2

44x

22

12345 6 7 8

C33

80.

1uF

R19

7

22

R21

115

0

R19

649

.9

BA

RJ1

510

K

1

2

3

U50

AD

M91

61

16 17 18 19 20 21 22 38 26 27 28 29 37 31 34 24 25 32 14 36 35 40 10 45

4 3 8 7 48 47 11 12 13 42 43

TXER

/TXD

4TX

D3

TXD

2TX

D1

TXD

0

TXEN

TXC

LK/IS

OLA

TE

RXE

R/R

XD4/

RPT

RR

XD3/

PHYA

D3

RXD

2/PH

YAD

2R

XD1/

PHYA

D1

RXD

0/PH

YAD

0

RXD

V/TE

STM

OD

ER

XEN

RXC

LK/S

CR

AMEN

/10B

TSER

MD

CM

DIO

MD

INTR

CAB

STS/

LIN

KSTS

CO

L/R

MII

CR

S/PH

YAD

4

RES

ETPW

RD

WN

SD

RX-

/FXR

D-

RX+

/FXR

D+

TX-/F

XTD

-

TX+/

FXTD

+

BGR

ES

BGR

ESG

FDX/

CO

L/O

P0SP

EED

/OP1

LIN

K/AC

T/O

P2 XT2

XT1

R20

06.

81K

R20

715

0D

46

HSM

G-C

650

Gre

en

U50

BD

M91

61

15 33 44

23 30 39 41

5 6 46

1 2 9

DG

ND

1D

GN

D2

DG

ND

3

DVD

D1

DVD

D2

DVD

D3

DVD

D4

AGN

DR

AGN

DT

AGN

DS

AVD

DR

1AV

DD

R2

AVD

DT

BA

RJ2

510

K

1

2

3

U47

C

74LC

X125

1211

13

C34

00.

1uF

R21

633

0

C34

30.

1uF

C33

90.

1uF

R20

375

R21

310

.0K

J36 R

J45

Shie

lded

8 7 6 5 4 3 2 19 10


DA

GN

DB

L52

NFM

60R

13

2

R20

915

0

R20

275

R19

310

K

C34

10.

1uF

R20

475

R21

510

.0K

C33

10.

1uF

R20

50

C34

20.

1uF

R19

110

K

+C

336

10uF

16V

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

USB

RX

N

1.5A

USB

RX

P

USB

RX

D

nUSB

LOW

SPD

USB

VC

C

nUSB

OE

USB

TXN

USB

TXP

nUSB

HIS

PD

SPA

RES

USB

CLK

Plac

e C

346

near

U52

nUSB

LOW

SPD

Plac

e C34

5 ne

ar U

51

nUSB

EN

USB

POWER

GN

DC

HA

SSIS

GN

DC

HA

SSIS

GN

DC

HA

SSIS

DU

ET A

DS

A

USB

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

2325

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

D-

D+

nUSB

OE

(5,1

7,18

)

nUSB

LOW

SPD

(24)

USB

TXN

(5,1

7,18

)

SW5_

USB

RXD

(6)

nUSB

EN(1

4,24

)

SW5_

USB

RXP

(6) SW

5_U

SBR

XN(6

)

nUSB

FU

LLSP

D(2

4)

CLK

2(5

,17,

18)

USB

VCC

(24)

USB

TXP

(5,1

7,18

)

VCC

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

VCC

S2

D2

D2

G2Q

5-2

MM

DF4

N01

HD

4 356

12 3

4

J38

USB

Ser

ies-

BR

/A

1

23

4

56

R22

4

24.3

S D

G

Q6A M

MD

F2P0

2HD

2

718

R22

8

1.00

K

S D

G

Q4A M

MD

F2P0

2HD

2

718

C34

50.

1uF

R22

7 0

R22

6

10.0

K

R22

31.

5K

R21

710

.0K

C34

60.

1uF

F3 SMD

150/

33

R26

815

K

34

21

J37

USB

Ser

ies-

AR

/A

1

2

3

4

56

R26

915

K

+C

344

4.7u

F10

V

1 2

G1

S1

D1

D1

Q5-

1

MM

DF4

N01

HD

2 1

8 7

R22

010

.0K

D48 H

SMG

-C65

0G

reen

U51

PDIU

SBP1

1AD

SO14

1

2 3 4 5

6 78

910 11

1213

14

MO

DE

OE

RC

V

VP VM

SUSP

ND

GN

D

NC

SPEE

DD

-

D+

VPO

VMO

VCC

R21

910

.0K

U52

25 p

pm48

MH

z

123

4

OE

GN

D

OU

TVc

c

SD

GQ

6BM

MD

F2P0

2HD

4

5 36

R22

21.

5K

R21

810

.0K

R22

5

24.3

R22

133

2

S D

G Q4B

MM

DF2

P02H

D

4

536

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

Helen Converse

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TMS

TCK

TDI

TDO

TRST

GND

NC NC ENAB

LE

VCC

S-RESET

ABORT

BOTH = HARD-RESET

MOD CK1

MOD CK2

DU

ET A

DS

A

BC

SR

6767

Old

Mad

ison

Pik

eS

uite

490

C

Hun

tsvi

lle, A

L 35

806-

2194

Har

dwar

e Te

amTh

ursd

ay, O

ctob

er 0

2, 2

003

2425

Net

wor

king

Com

mun

icat

ion

Syst

ems

Div

isio

n

Title

Size

DO

CN

umbe

r:Re

v

Date

:Pa

ge

ofDe

sign

er:

FPD

5

FPD

2

BCSR

3R0

BRW

2b

A19

PCEE

Nb

BCSR

3R0

BREV

3

BCSR

3R1

DR

MPD

1

PCC

VCC

1

DBR

EV0

DBI

D3

ISPT

DO

A20

DBR

EV2

ETH

ENb

DBI

D3

SGLA

MP

b

SRES

ETb

LBU

FEN

b

BCSR

3R13

RSE

N1b

DBI

D1

FCS2

b

ISPI

NTD

I

BCSR

CSb

DR

MPD

1

A30

PCO

ENb

PCR

Wb

DBR

EV0

PCC

ENb

FPD

7

NM

IbBA9

EXTO

LI1

ISPT

CK

BREV

2

DR

AMEN

b

BA28

BREV

2

FPD

6

FCS3

b

ISPT

MS

EXTO

LI0

BREV

0

RST

CN

Fb

BCSR

3CSb

FCS1

b

DBI

D0

BREV

1

BREV

1

RSE

N2b

EXTO

LI2

DR

MPD

2

BA29

DBI

D1

DR

MPD

3

DBI

D5

RPO

RI

BCE2

Ab

DBI

D2

HR

ESET

b

DBI

D2

PCC

VPP0

BCE1

Ab

BCSR

3R1

FPD

4

BCSR

3R1

DBI

D4

IRD

ENb

BREV

3

DBI

D5

DBR

EV1

DBI

D4

DBI

D3

PCVC

C0

DR

MC

S2b

DR

MPD

4

MO

DC

K1

DR

VCN

Fb

FPD

1

PCC

VPP1

FCS4

b

BCSR

2R4

DBR

EV2

BTE

Ab

BREV

0

DBI

D0

DBI

D4

FPD

3

FOEb

BCSR

3R13

CLK

1

DR

MPD

2

BREV

2

DBR

EV1

UBU

FEN

b

BCSR

3R0

BA27

DBI

D2

BREV

1

DBI

D0

FEN

b

FCSb

DBI

D5

BREV

0

SDR

AMEN

BCSR

3R13

BCSR

2R4

TAb

DR

MC

S1b

EXTO

LI3

FPD

6

BA10

FPD

7

DBI

D1

ISPI

NTD

IIS

PTD

O

ISPT

CK

ISPT

MS

MO

DC

K2

BD9

BD8

BD7

BD6

BD0

BD14

BD2

FPD

2

BD11

BD7

BD13

BD4

BD11

BD13

BD5

BD4

FPD

4

BD15

FPD

1

BD13

BD9

BD2

BD12

FPD

3

BD15

BD5

BD8

BD1

BD12

BD2

BD7

DR

MPD

1

FPD

4

FPD

3

BD3

BD11

BD1

FPD

2

BD9

FPD

1

BD0

BD15

BD6

BD1

BD3

BD12

BD4

BD14

BD8

BD10

BD3

BD0

BD6

BD5

BD10

BD10

BD14

EXTO

LI0

EXTO

LI3

EXTO

LI0

EXTO

LI1

EXTO

LI2

EXTO

LI2

EXTO

LI1

DBR

EV1

DBR

EV2

DBR

EV0

EXTO

LI3

BCSR

2R4

DR

MPD

2

DR

MPD

4D

RM

PD3

FPD

5

BREV

3

HR

ESET

b(3

,11,

15,1

7,18

)

IRD

ENb

(14,

19)

A19

(3,4

,17)

nUSB

FU

LLSP

D

(23)

USB

VCC

(23)

BA10

(2,4

,10)

A20

(2,3

,4,1

7)

CLK

1(1

9)

nUSB

EN(1

4,23

)

BCSR

CSb

(3,1

7)

CS5

b(3

,11,

17)

SGLA

MP

b(1

4)

RES

ERVE

D(1

4)

BA27

(2,4

,10,

11,1

8)BA

28(2

,4,1

0,11

,18)

LBU

FEN

b(4

)

NM

Ib(3

,17,

18)

TAb

(3,1

1,17

,18) BT

EAb

(4)

BA29

(2,4

,10,

11,1

8)

RST

CN

Fb(3

,17)

RSE

N1b

(14,

19)

SRES

ETb

(3,1

5,17

,18)

BCE2

Ab(3

,4,1

7,18

)

PCVC

C0

(13)

BRW

2b(4

,18)

FEN

b(1

4)

PCC

VCC

1(1

3)

CS6

b(3

,17,

18)

MO

DC

K2(3

,17)

BA9

(2,4

,10)

RSE

N2b

(14,

19)

RPO

RI

(14)

PCO

ENb

(10)

PCR

Wb

(10)

PCC

ENb

(10,

11,1

4)

FCS1

b(2

)

PCC

VPP1

(13)

FPD

[1:4

](2

)

FCS2

b(2

)

SDR

AMEN

(2,1

4)

PCC

VPP0

(13)

nUSB

LOW

SPD

(23)

ETH

ENb

(14,

20)

UBU

FEN

b(4

)

FCS3

b(2

)

DR

MC

S1b

(3,1

7)

A30

(3,4

,17)

BD[0

:31]

(2,4

,10,

11,1

8)

DR

MC

S2b

(3,1

7)

PCEE

Nb

(10)

FCS4

b(2

)

CS7

b(3

,17,

18)

MO

DC

K1(3

,17)

FOEb

(2)

FCSb

(3,1

7)BCE1

Ab(3

,4,1

7,18

)

EXP_

OEb

(18)

nETH

RST

(20)

SW_M

OD

CK1

(3,1

8)SW

_MO

DC

K2(1

8)

FPD

[1:7

](2

)

V3U

3V3

U3

V3U

3V3

U3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

V3U

3

RN

68x

10K

1234678910 5C

365

0.1u

F

U53

AM

4A3-

192/

96-6

VC

26 110 30 100

116

112 32 16 5

104 18 98 28 102 22 46

7

8 9 10 11 12

15

1719

20

21 23

2729 5657 5860 61 62 6566 68 7071

72

75 76 77 7831 33 3839 4041 42 43 4445

4647 485354

55 79 80 81 82 85 86 87 89 9192

939497

99105

118

119

120

124

125

126

127

128

129

130

132

133

134

137

138

140

142

143

144

111 2 34 35 107 49 52

59 67 69 88 90 101

103

113

114

115

117

131

139

141

121 74 1063

BD0

BD1

BD2

BD3

BD4

BD5

BD6

BD7

BD8

BD9

BD10

BD11

BD12

BD13

BD14

Rst

1R

st0

DR

MPD

2

A30

A20

A19

BA29

R_P

OR

I

DR

MPD

1

NM

I~

BA10

PCR

_W

BA9

SRes

et~

Mod

ck2

F_PD

4

Ras

2DD

~

F_PD

1

Ras

2~

LBU

FEn~

Ras

1DD

~

DR

VCN

F~

DR

MA1

0

PccV

cc1

RS_

En2~

Dra

mEn

~

DR

MA9

HR

eset

~

Mod

emEn

~U

SBSP

DD

RM

H_W

~

PccV

pp1

F_O

E~

RST

CN

F~U

UFE

N~

F_C

s2~

F_EN

~

F_PD

3

F_C

s1~

F_C

s3~

IRD

_En~

F_C

s4~

F_C

s~

CE1

A~

BCSR

Cs~

TA~

BR_W

2

F_PD

2

VDO

EN~

TPFL

DL~

VDO

RST

~SG

LAM

P~Pc

cEn~

EthE

n~BC

SREn

~TP

SQEL

~

Usb

Vcc1

Ras

1~

Mod

In

DR

MC

s2~

DR

MC

s1~

Bcsr

3Cs~

Bcsr

2Cs~

CE2

A~

Abr1

Abr0

CLK

1

BA27

BA28

PCEE

n~

nETH

RST

UBU

FEn~

PccV

pp0

FCfg

En~

PCO

En~

MD

M_A

UD

~

Mod

ck1

Sdra

mEn

~Pc

Vcc0

VDO

EXTC

K

RS_

En1~

Usb

Vcc0

BTEA

~

TDI

TMS

TCK

TDO

SPAR

E_C

LK0

SPAR

E_C

LK1

SPAR

E_0

SPAR

E_1

SPAR

E_2

SPAR

E_3

SPAR

E_4

EXP_

OEb

SPAR

E_6

SPAR

E_7

SPAR

E_8

SPAR

E_9

SPAR

E_12

SPAR

E_13

SPAR

E_10

SPAR

E_11

SPAR

E_C

LK2

NC

NC

0

BD15

TP29

S4

4 Po

sitio

n sw

itch5

321

678

4

R23

810

.0K

C36

30.

1uF

C34

90.

1uF

TP28

TP44

TP48

R24

20

C35

00.

1uF

TP20

TP27

R23

910

.0K

TP43

TP46

C34

80.

1uF

C35

90.

1uF

R27

210

K

TP26

R25

30

C35

60.

1uF

TP42

RN

78x

10K

1234678910 5C

361

0.1u

F

TP41

R24

010

.0K

U54

B74

LVC

H16

2244

4 10 15 21 28 34 39 45

7 18 31 42

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

RN

48x

10K

12346789

105

TP40

R25

20

R24

10

TP39

TP54

R27

310

K

TP45

R25

60

R25

40

TP33

TP38

R29

40

R25

50

TP47

S7 2 Po

sitio

n sw

itch21

34

R24

40

R24

50

C36

20.

1uF

TP37

C36

00.

1uF

R24

90

TP36

TP52

U54

A74

LVC

H16

2244

47 46 44 43 141 40 38 37 48 36 35 33 32 2530 29 27 26 24

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

1A0

1A1

1A2

1A3

OE12A

02A

12A

22A

3O

E2 3A0

3A1

3A2

3A3

OE34A

04A

14A

24A

3O

E4

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

3Y0

3Y1

3Y2

3Y3

4Y0

4Y1

4Y2

4Y3

TP35

TP50

U55

B74

LVC

H16

2244

4 10 15 21 28 34 39 45

7 18 31 42

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

VCC

VCC

VCC

VCC

TP51

C36

40.

1uF

C35

10.

1uF

C36

70.

1uF

TP34

TP49

R24

30

TP32

R25

00

C35

50.

1uF

S6PU

SH S

W B

LAC

K 134

TP53

TP31

RN

88x

10K

1234678910 5R

251

0

C35

80.

1uF

R24

60

C36

60.

1uF

TP30

U53

BM

4A3-

192/

96-6

VC

13 25 51 63 83 96

1 14 108

24 36 37 50 64 73 84 95 136

109

123

122

135

VCC

_0VC

C_1

VCC

_2VC

C_3

VCC

_4VC

C_5

GN

D_0

GN

D_1

GN

D_2

GN

D_3

GN

D_4

GN

D_5

GN

D_6

GN

D_7

GN

D_8

GN

D_9

GN

D_1

0G

ND

_11

GN

D_1

2G

ND

_13

VCC

_6VC

C_7

RN

58x

10K

1234678910 5

S5PU

SH S

W R

ED

134

R24

70

C34

70.

1uF

R24

80

C35

70.

1uF

J39

2x5

Hea

der

0.1

CTR

12

34

56

78

910

R23

710

.0K

U55

A74

LVC

H16

2244

47 46 44 43 141 40 38 37 48 36 35 33 32 2530 29 27 26 24

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

1A0

1A1

1A2

1A3

OE12A

02A

12A

22A

3O

E2 3A0

3A1

3A2

3A3

OE34A

04A

14A

24A

3O

E4

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

3Y0

3Y1

3Y2

3Y3

4Y0

4Y1

4Y2

4Y3

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130(800) 521-6274

JAPAN:

Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong852-26668334

TECHNICAL INFORMATION CENTER:

(800) 521-6274

HOME PAGE:

www.motorola.com/semiconductors

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

© Motorola, Inc. 2004

MPC885ADSUG

Information in this document is provided solely to enable system and software implementers to use

Motorola products. There are no express or implied copyright licenses granted hereunder to design

or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products

for any particular purpose, nor does Motorola assume any liability arising out of the application or

use of any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated

for each customer application by customer’s technical experts. Motorola does not convey any

license under its patent rights nor the rights of others. Motorola products are not designed,

intended, or authorized for use as components in systems intended for surgical implant into the

body, or other applications intended to support or sustain life, or for any other application in which

the failure of the Motorola product could create a situation where personal injury or death may

occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,

affiliates, and distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was

negligent regarding the design or manufacture of the part.

Fre

esc

ale

Se

mic

on

du

cto

r, I



nc

...

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NRDateRevision

DUET ADS Board

SchematicsFirst Prototype RevisionRelease Information

April 3 2003

SDRAM, FLASHMPC885 CPU03

0201

06

0405

09

0708

12

1011

15

1314

18

1617

21

1920

24

2223

25

BUFFERSMPC885 CPM, PWR, GND, I2C

ATM25 (8 bit)ATM155 (8 bit)ADTECH (8 bit)PCMCIAControl

PowerReset & LED'sHOST & BDM InterfaceT1&E1Logic AnalyzerExpansion ConnectorsRS232, InfraRed, Sys CLK10BaseT ETHERNET GPSIFAST ETHERNET R/MII #1FAST ETHERNET R/MII #2USBBCSRblank

blank

CPM switching LOGIC

NR June 27 2003 REVIEW Revision

Revision History

A August 11 2003 Revision A

DUET ADSA

Revision History

6767 Old Madison PikeSuite 490

C

Huntsville, AL 35806-2194

Hardware TeamThursday, October 02, 2003 1 25

Networking Communication Systems Division

Title

Size DOCNumber:

Rev

Date: Page ofDesigner:

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EDOOEb

BS1

BSYSCLK2

WE0b

SDRAMEN

VPP

SDRMCSb

WE1b

DRMWb

BA01

GPL2b

SDRAM

WE2b

A10BS0

(GPL0b)

WE3b

GPL3b

FLASH

BA0

For 8M SDRAM (factory default)connect A10 to BA0 RJ20 1-2

For 8M SDRAM (factory default) A8NOT connected to BA01 RJ21 3-2

A8

A10

A9

DUET ADSA

SDRAM, FLASH


C




Title

Size DOCNumber:

Rev


D16

D28

D7

A26

FPD1

D5

A24

D19

D6

D25

FPD2

D2

D13

D29

A29

D30

FPD4

D14

A27

D4

D23

A28

D27

FPD3

D17

D21

D15

A22

D22

D24

D18

D3

FPD5

D26A23

D1

D12

D8

FPD6

D11

A21

D9

D0

D31

A20

D10

A25

FPD7

D20

BA29

BA21BA20

BA25BA24

BA13

BA19

BA9

BA18

BA11

BA8

BA23

BA16

BA26

BA14

BA10

BA28

BA22

BA12

BA7

BA17

BA15

BA27

BD21

BD0

BD7

BD25

BD11

BD31

BD13

BD10

BD6

BD17

BD9

BD28

BD30

BD3

BD1

BD27BD26

BD8

BD16

BD19BD18

BD20

BD4

BD2

BD23

BD29

BD22

BD24

BD15

BD12

BD5

BD14

A[20:29](3,4,17,24)

FPD[1:7] (24)

D[0:31] (3,4,17)

BD[0:31](4,10,11,18,24)

FCS1b (24)

FCS4b (24)

BWE2b (4,10)

BA[7:29] (4,10,11,18,24)

BWE1b (4,10)BWE0b (4,10,18)

BWE3b (4,10)

FCS2b (24)

FOEb (24)

FCS3b (24)

WE1b(3,4,17)

BSYSCLK2(19)

GPL2b(3,4,17)

WE0b(3,4,11,17)

WE3b(3,4,17)

SDRMCSb(3,17)OE~(3,4,11,17)

GPL3b(3,4,17)

SDRAMEN(14,24)

WE2b(3,4,17)

A10(3,4,17)DRMWb(3,4,17)

A8(3,4,17)

A9(3,4,17)

A10(3,4,17)

V3U3

V3U3

VPP

VCC

C18.01uF

C20.01uF

C22.01uF

J280 Pin SIMM Socket

7069686766656463

6261605958575655

89

101112131415

1617181920262728

5251504948474645444342414039383736353433323130

24232221

562953

73747576777879

4

7

272

371

1255480

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7




A0A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22

CE0CE1CE2CE3

WE0WE1WE2WE3

PD1PD2PD3PD4PD5PD6PD7

OE

NC1

VCC1VCC2

VPP1VPP2

GND1GND2GND3GND4

C110.1uF

BA

RJ20 10K1

2

3

C130.1uF

C150.1uF

U1B

MT48LC2M32B2TG-6

1

3

6

912

15

29

32

35

38

43

41

44

46

49

55

52

58

84

81

8672

75

78

Vdd

VddQ

VssQ

VddQVssQ

Vdd

Vdd

VssQ

VddQ

VssQ

Vdd

VddQ

Vss

VssQ

VddQ

VddQ

VssQ

Vss

VssQ

VddQ

VssVss

VddQ

VssQ

C210.1uF

SDRAM

U1AMT48LC2M32B2TG-6

24

75

8

1110

13

14

16

17181920

212223

24

252627

28

30

313334363739404245

504847

5153

5654

59

57

60616263646566

67

68

6970

71

74

79

82

76

73

85

80

77

83

DQ0DQ1

DQ3DQ2

DQ4

DQ6DQ5

DQ7

NC6

DQM0

WECASRASCS

NC(A11)BA0BA1

A10(AP)

A0A1A2

DQM2

NC5

DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24

DQ27DQ26DQ25

DQ28DQ29

DQ31DQ30

DQM3

NC4

A3A4A5A6A7A8A9

CKE

CLK

NC3NC2

DQM1

DQ8

DQ11

DQ13

DQ9

NC1

DQ15

DQ12

DQ10

DQ14

C190.1uF

BA

RJ21 10K1

2

3 C12.01uF

C40.1uF

C10.01uF

C170.1uF

C90.1uF

C14.01uF

C5.01uF

C16.01uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPL4BbGPL5Bb

CS6b

SRESETb

BS2Ab

ATMRXCLK

CS5

TRSTb

DSCK

GPL3b

DRMWb

TEAb

BS1Ab

TMS

TAb

RPORIb

GPL5Ab

DSDO

DRMCS1b

MODCK1

BCSRCSb

BGb

RWb

BS0Ab

TSb

IRQ3b

CS7b

BRb

HRESETb

BURST

BBb

SDRMCSb

POEA

RSTCONF_B

BIb

GPL2b

DRMCS2b

GPL4Ab

BS3Ab

IRQ1bNMIb

AS_B

MODCK2

IRQ2b

FRZ

IRQ7b

FCSb

EDOOE

DSDI

ALEABCE1Ab

EXTAL

XTAL

SYSCLK

CLK4IN (EXTCLK)

TEXP

BCE2Ab

Place R17 veryclose to pinA5.

CLK4IN tracesshould be placedon outer layersonly.

CLK4IN trace Z shouldbe 50 ohms.

CLKOUT tracesshould be placedon outer layersonly.

CLKOUT trace Z shouldbe 50 ohms.

External clockSMB jack

No Load R17for on boardoscillator.

IRQ3/IRQ7 TABLER7 ATM/T1

YES

NO

R8 ENET

YES

NO NO

YES

NO

YES

IRQ3

IRQ3

IRQ3

N/A

NC

IRQ7

IRQ3

N/A

ATM/T1

ENET

No Load R17for on boardoscillator.

Oscillator socket

CLKOUT

1.8V

NO LOAD

NO LOAD

Default

DUET ADSA

MPC885 CPU


C




Title

Size DOCNumber:

Rev


AT0AT3

A23

D2

D0

A3

D26

D16

A28

A26

A22

A8A7

D11

D8

D6

A25

A20

A13

A10

A0

AT2

VF0

D22

A31

A9

D28

D23

D19

D12

D1

D21

A24

A19

D27

D17

D13

A14

A11

A6

VF2

D5

A5

VFLS0VFLS1

D15

D9

A12

A4

A1

D4

A16

D24

D10

D18

D3

A21

A15

D20

A27

D31

A18

D29

A17

VF1

D30

D25

D14

D7

A30A29

A2

CLK4IN

BCE1Ab (4,17,18,24)

BCD2b____ATM_RXD3_SW4(6,17,18)

VFLS1(15,17)

DSDI (15)

SPKROUT(10,17)

VF0(17)

AT3(17)

VF2(17)


BWP____ATM_RXD2_SW 4(6,17,18)

WAITBb (17)

BS0Ab (17,18)

AT2(17)

SRESETb (15,17,18,24)

DRMWb (2,4,17)

BBVD1____ATM_RXD5_SW4(6,17,18)

BIb (17)

GPL5Bb (17,18)

GPL3b (2,4,17)

WE0b (2,4,11,17)

VF1(17)

BBb (17)

D[0:31](2,4,17)

GPL2b (2,4,17)

FRZ (17,18)

BVS1____ATM_RXD0_SW4(6,17,18)

BURST (17)

WE1b (2,4,17)

BS2Ab (17)

DSDO (15)

BCE2Ab (4,17,18,24)

RPORIb (11,14,15,17,18)

A[0:31](2,4,17,24)

GPL4Bb (17,18)

WE2b (2,4,17)

DSCK (15)

POEAb (4,17)

AT1 (17)

WE3b (2,4,17)

BWAITAb____ATM_RXSOC_SW4(6,17,18)

RSTCNFb (17,24)

BS3Ab (17)

VFLS0(15,17)

GPL4Ab (17,18)

BRESETA____ATM_RXCLK_SW 4 (6,9,17,18)

BS1Ab (17)

TAb (11,17,18,24)

AT0(17)

BGb (17)

IRQ7b (17,18)


BVS2____ATM_RXD1_SW4(6,17,18)

GPL5Ab (17,18)

BRDY____ATM_RXD7_SW4(6,17,18)

BRb (17)

R/MIICRS-1 (17,21)

R/MIICOL-1 (17,21)

TEXP (17)

IRQ3b_IRQ7b (20,21,22)

IRQ3b (7,8,16,17,18)

TEAb (4,17)

ALEA (4,17)

OE~ (2,4,11,17)

HRESETb (11,15,17,18,24)

TSb (4,11,17)

SYSCLK (19)

EXTCLK (17)

FCSb (17,24)

MODCK1 (17,24)

IRQ1b (17,18)

CS7b (17,18,24)

RWb (4,11,17,18)

IRQ2b (17,18)

MODCK2 (17,24)

DRMCS2b (17,24)

CS6b (17,18,24)

BCSRCSb (17,24)

CS5b (11,17,24)

DRMCS1b (17,24)

SDRMCSb (2,17)

NMIb (17,18,24)

MPCMDIO (17,18,20,21,22)R/MIITXEN-1 (17,21)

SW_MODCK1(18,24)

REGAb (10,17)TSIZ1 (17)

V3U3

V3U3V3U3

V3U3

V3U3

V3U3

V1U8

V3U3

V3U3

V3U3

V3U3

R28110.0K

R1010.0K

Y1

10.000MHz50ppm@25C1

2

TP6

1

R27010.0K

RN10 8x10K

1234678910 5U2E74LCX08

714 GNDVCC

R258

22

DIP8

J5SOCKET for OSC

1

4

8

5

NC

GND

VCC

OUT

R15

0

R27110.0K

C310.1uF

R52.21K

C37118pFC0G

R26410M

R263

1.00K

TP3

J3A

DUETPBGA357IC Socket

M16N18N19M19M17M18L16L19L17L18K19K18K17K16J19J17J18J16E19H18H17G19F17G17H16F19D19H19E18G18F18D18

P2M1L1K2N1K4H3F2P1L4L3L2N3N2K3K1J2

M4J1J3H2H1J4

M3G2G1G3M2H4F1E1F3

B8A8

A10B9C9C8D9A9

C7

A2

B1C1F4E3D2D1E2D3

C5B5A7

B18E16C17B19

C3

D8

E17G16

D6A6

D13B14C14A15D14C16A16D15B16

N4P3B10A11D10P4

B13C13B17A18D16A17A14A13B11C11D11A12C12B12D7D12C10

U17V18T16T17W18

D17C18C19F16

B7B15C15

B6C6

A3B4B3D4

E4C2

B2

C4

A5

G4

A4

D5

T11P19T5U12

R16N17

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31

IPB7_PTR_AT3IPB6_DSDI_AT0IPB5_LWP1_VF1IPB4_LWP0_VF0IPB3_LWP2_VF2IPB2_IOIS16B_B_AT2IPB1_IWP1_VFLS1IPB0_IWP0_VFLS0

KR_B_IRQ4_B

WAITA_B

IPA0IPA1IPA2_IOIS16A_BIPA3IPA4IPA5IPA6IPA7

BADDR28BADDR29BADDR30

WE0_B_BSB0_B_IORD_BWE1_B_BSB1_B_IOWR_BWE2_B_BSB2_B_PCOE_BWE3_B_BSB3_B_PCWE_B

WAITB_B

ALEB_DSCK_AT1

TSIZ1TSIZ0_REG_B

OP2_MODCK1_STS_BOP3_MODCK2_DSDO

WR_BCS0_BCS1_BCS2_BCS3_BCS4_BCS5_B

CS6_CE1B_BCS7_B_CE2B_B

IRQ0_BIRQ1_B

RSV_B_IRQ2_BCR_B_IRQ3_B

FRZ_B_IRQ6_BIRQ7_B

GPLA4_BGPLA5_B

GPLA0_B_GPLB0_BOE_B_GPLAB1_B

GPLAB2_B_CS2_BGPLAB3_B_CS3_B

GPLB4_BBDIP_B_GPLB5_B

BB_BBG_BBR_BTS_BTA_B

TEA_BAS_BBI_B

BURST_B

TCK/DSCKTMS

TDI/DSDITDO/DSDO

TRST_B

BSA0_BBSA1_BBSA2_BBSA3_B

ALEACE1A_BCE2A_B

OP0OP1

SRESET_BHRESET_B

PORESET_BRSTCONF_B

GNDSYNGNDSYN1

VDDLSYN

TEXP

CLK4IN

CLKOUT

XTAL

EXTAL

SPARE1SPARE2SPARE3SPARE4

TEST_MODENC

RP1

4x22

1234 5

678

TP21

R9

22

TP7

1

R257

301

U2A74LCX08

1

23

TP1

R2821.00K

R265

10.0K

TP2

C25.01uF

U2B74LCX08

4

56

R259

0

C300.1uF

TP4

L1

8200uH50mA10%

12

R14

0

U2C74LCX08

10

98

R121.00K

R8 0

C29.01uF

CTRGND

GND

GND

221111-1GND

J6

SMB Jack Vertical

2135

4

C37018pFC0G

R16

0

R62.21K

R7 0

U2D74LCX08

13

1211

+ C2310uF16V

RN9 8x10K

1 2 3 4 6 7 8 9 105

R1749.9

C240.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BCSR

BCSR

Flash/PCMCIA

Flash/PCMCIAFlash/PCMCIA

Flash/PCMCIA

5-Volt tolerant I/O 5-Volt tolerant I/O

5-Volt tolerant I/O

5-Volt tolerant I/O

5-Volt tolerant I/O

EDOOEALEAOP1

BCSRSDRAM

BCSR

DUET ADSA

BUFFERS


C




Title

Size DOCNumber:

Rev


D2BD19

BD7

D3

BD5

D30

D16

BD8

BD6

BD3

BD0

BD9

D4D5

BD12

D31

BD21D21D6

BD11

BD14BD29

D20

BD15

BD18

D27

BD31

BD13

D7

BD30

BD10D10D9 D25

D22

D12

D23

BD27

BD22

D24

BD23

D15

D13

D18

BD16

BD26D11

D14

D8

D26

D29

BD20

BD2

D28

D19

BD24

BD1D0

BD25

BD28

D17 BD17

BD4

D1

A23

A24A25

A22

A11

A17

A26

A30

A21

A27

A15

A20A19

A8

A28

A10

A31

A13 A29A12

A18

A9

A16

A14

BA14

BA10BA9

BA15

BA13

BA8

BA11

BA12

BA26

BA30

BA24

BA31

BA17

BA20

BA22

BA19

BA16

BA21

BA28

BA25

BA29

BA18

BA27

BA23

A6A7 BA6

BA7

D[0:31](2,3,17)

A[6:31](2,3,17,24)

BD[0:31] (2,10,11,18,24)

WE2b(2,3,17)

UBUFENb(24)

GPL3b(2,3,17)

WE0b(2,3,11,17)

WE3b(2,3,17)

LBUFENb(24)

WE1b(2,3,17)

GPL2b(2,3,17)

BWE2b (2,10)

BWE0b (2,10,18)

BWE3b (2,10)

BWE1b (2,10)

BGPL3b (18)BGPL2b (18)

BEDOOEb (18)BALEA (10,18)BPOEAb (10)

POEAb(3,17)ALEA(3,17)

OE~(2,3,11,17)

TSb(3,11,17)TEAb(3,17)

DRMWb(2,3,17)

RWb(3,11,17,18)

BRW2b (18,24)

BDRMWb (18)

BTSb (18)BTEAb (24)

BA[6:31] (2,10,11,18,24)

BCE1Ab(3,17,18,24)BCE2Ab(3,17,18,24)

PBCE1Ab (10)PBCE2Ab (10)

V3U3

V3U3V3U3

V3U3

V3U3

V3U3

V3U3

C560.1uF

TP19

RP14 4x0 ohm1234 5

678

TP17

RP4 4x0 ohm1234 5

678

U3A74LVC32245

A2A1B2B1C2C1D2D1

E2E1F2F1G2G1H1H2

A5A6B5B6C5C6D5D6

E5E6F5F6G5G6H6H5

A3

H3

A4

H4

1B11B21B31B41B51B61B71B8

2B12B22B32B42B52B62B72B8

1A11A21A31A41A51A61A71A8

2A12A22A32A42A52A62A72A8

DIR1

DIR2

OE1

OE2

TP18

R18

1.00K

U4C74LVC32244

B3B4D3D4E3E4G3G4

C3C4F3F4

K3K4M3M4N3N4R3R4

L3L4P3P4

GNDGNDGNDGNDGNDGNDGNDGND

VCCVCCVCCVCC


VCCVCCVCCVCC

C420.1uF

C440.1uF

U3B74LVC32245

J2J1K2K1L2L1M2M1

N2N1P2P1R2R1T1T2

J5J6K5K6L5L6M5M6

N5N6P5P6R5R6T6T5

J3

T3

J4

T4

3B13B23B33B43B53B63B73B8

4B14B24B34B44B54B64B74B8

3A13A23A33A43A53A63A73A8

4A14A24A34A44A54A64A74A8

DIR3

DIR4

OE3

OE4

C380.1uF

C470.1uF

U4A74LVC32244

A5A6B5B6C5C6D5D6A3A4

A2A1B2B1C2C1D2D1

E5E6F5F6G5G6H6H5H4H3

E2E1F2F1G2G1H1H2

1A11A21A31A42A12A22A32A41OE2OE

1Y11Y21Y31Y42Y12Y22Y32Y4


3Y13Y23Y33Y44Y14Y24Y34Y4

RP7 4x0 ohm

1234 5

678

C500.1uF

R211.00K

C540.1uF

C410.1uF

RP8 4x0 ohm1234 5

678

RP15 4x0 ohm

1234 5

678

C460.1uFC53

0.1uF

C390.1uF

U3C74LVC32245

B3B4D3D4E3E4G3G4

C3C4F3F4

K3K4M3M4N3N4R3R4

L3L4P3P4


VCCVCCVCCVCC


VCCVCCVCCVCC

C520.1uF

RP3 4x0 ohm

1234 5

678

TP16

RP16 4x0 ohm1234 5

678

C480.1uF

C350.1uF

C400.1uF

U6A74LVCH162244

47464443

1

4140383748

36353332

25

3029272624

2356891112

1314161719202223

1A01A11A21A3

OE1

2A02A12A22A3OE2

3A03A13A23A3

OE3

4A04A14A24A3OE4

1Y01Y11Y21Y32Y02Y12Y22Y3

3Y03Y13Y23Y34Y04Y14Y24Y3

C450.1uFC51

0.1uF

C360.1uF

R201.00K

RP11 4x0 ohm

1234 5

678

C490.1uF

C430.1uF

U4B74LVC32244

J5J6K5K6L5L6M5M6J3J4

J2J1K2K1L2L1M2M1

N5N6P5P6R5R6T6T5T4T3

N2N1P2P1R2R1T1T2


5Y15Y25Y35Y46Y16Y26Y36Y4


7Y17Y27Y37Y48Y18Y28Y38Y4

C370.1uF

RP10 4x0 ohm1234 5

678

U6B74LVCH162244

410152128343945

7183142


VCCVCCVCCVCC

RP5 4x0 ohm

1234 5

678

C330.1uF

C550.1uF

C340.1uF

RP13 4x0 ohm

1234 5

678

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

J3 decoupling capacitors1.8V VDDL decoupling capacitors

place C57, C58, C59, C160, C61, C62 very near the VDDLpins/plane

R/MII-RXD0-1mii1-RMII1-RXD0 =

MII_MDC

l1a-L1TCLKAETHRCK-10btETHTCK-10bit l1a-L1RCLKAETHTX-10bt l1a-L1RXDA

l1a-L1TXDAETHRX-10btMII1-TXERR

IRDTXDIRDRXDUSBOEUSBRXD

utp-RXADDR[2] utp-TXADDR[2] - slaveutp-RXCLAV - slaveutp-TXCLAV

mii1-RMII1-TXD0, MII1-TXD0

utp-RXADDR[0] utp-TXADDR[0] - slaveutp-RXADDR[1] utp-TXADDR[1] - slaveutp-RXADDR[4] utp-TXADDR[4] - slaveMII1-RXD3utp-TXADDR[0] utp-RXADDR[0] - slaveutp-TXADDR[1] utp-RXADDR[1] - slaveutp-TXADDR[4] utp-RXADDR[4] - slaveutp-TXADDR[2] utp-RXADDR[2] - slaveutp-TXADDR[3] utp-RXADDR[3] - slaveutp-RXADDR[3] utp-TXADDR[3] - slave

I2CSCLI2CSDASPIMISOSPIMOSISPICLK

mii1-RMII1-REFCLK MII1-TXCLK

l1a-L1RSYNCA ERENA-10btl1a-L1TSYNCA ECLSN-10btUSBTXNUSBTXP

USBRXNUSBRXPMII1-TXD2MII1-TXD3

utp-RXCLAV utp-TXCLAV - slave?

ATMTXSOCATMTXD7ATMTXD6ATMTXD5ATMTXD4

ATMTXCLKATMTXENBATMRXENBATMTXD3ATMTXD2ATMTXD1ATMTXD0

mii2-RMII2-TXD0, MII2-TXD0mii2-RMII2-TXD1, MII2-TXD1mii2-RMII2-REF_CLK MII2-TXCLKMII2-TXD2MII2-TXD3mii2-RMII2-TXEN, MII2-TXENMII2-TXERRmii2-RMII2-RXD0, MII2-RXD0mii2-RMII2-RXD1, MII2-RXD1MII2-RXCLK RSDTR2bMII2-RXD2MII2-RXD3mii2-RMII2-CRS_DV, MII2-RXDVmii2-RMII2-RXERR, MII2-RXERR ETENA-10btMII2-COLMII2-CRSMII1-RXD2MII1-RXCLK

PA7

PC4

PA8

PC5

PA9

I2Coff-boardconnections

DUET ADSA

MPC885 CPM, PWR, GND, I2C


C




Title

Size DOCNumber:

Rev


PE21

PE23

PE20

I2CSDAI2CCSL

R/MIIRXD1-1(17,18,21)

R/MIIRXDV-1(17,18,21)R/MIIRXD0-1(17,18,21)

R/MIIRXERR-1(17,18,21)R/MIITXD1-1(17,18,21)

nUSBOE(17,18,23)

USBTXP (17,18,23)

USBRXD(6,17,18)

USBTXN (17,18,23)

USBRXP (6,17,18)USBRXN (6,17,18)

R/MIIRXD3-2 (17,18,22)R/MIIRXD2-2 (17,18,22)

R/MIIRXD1-2 (17,18,22)

R/MIICOL-2 (17,18,22)R/MIICRS-2 (17,18,22)

R/MIITXEN-2 (17,18,22)

R/MIITXD1-2 (17,18,22)R/MIITXD0-2 (17,18,22)

CLK5 (6,17,18)R/MIITXD3-2 (17,18,22)

MPCMDC (17,18,20,21,22)

R/MIIRXCLK-1 (17,18,21)

R/MIITXERR-1(17,18,21)R/MIITXD3-1 (17,18,21)R/MIITXD2-1 (17,18,21)

R/MIITXD0-1(17,18,21)

R/MIITXCLK-1(17,18,21)

R/MIIRXD3-1(17,18,21)

R/MIIRXD2-1 (17,18,21)

R/MIIRXERR-2____ETHTXEN_SW3 (6,17,18)

R/MIIRXCLK-2____RSDTR2b_SW2 (6,17,18)

R/MIITXERR-2____RSTXD2_SW2 (6,17,18)

RSTXD1____ATM_RXADDR3_SW1(6,17,18)

RSDTR1b____ATM_TXADDR2_SW1(6,17,18)RSRXD1____ATM_TXADDR3_SW1(6,17,18)

R/MIIRXD0-2____RSRXD2_SW2 (6,17,18)

ATM_TXCLAV(6,17,18)

ATM_TXD7 (7,8,9,17,18)ATM_TXD6 (7,8,9,17,18)ATM_TXD5 (7,8,9,17,18)ATM_TXD4 (7,8,9,17,18)

ATM_TXD0 (7,8,9,17,18)ATM_TXD1 (7,8,9,17,18)

ATM_TXD3 (7,8,9,17,18)ATM_TXD2 (7,8,9,17,18)

ATM_RXADDR0(7,8,9,17,18)ATM_RXADDR1(7,8,9,17,18) ATM_TXEN (7,8,9,17,18)

ATM_RXEN (7,8,9,17,18)

ATM_TXSOC (7,8,9,17,18)

ATM_RXCLAV (6,10,17,18)

ATM_TXADDR1(7,8,9,17,18)ATM_TXADDR0(7,8,9,17,18)

ATM_TXADDR4(7,8,9,17,18)

ATM_RXADDR2(7,8,9,17,18)

ATM_RXADDR4(7,8,9,17,18)

T1_L1RCLKA____ETHTXCK_SW3(16,17,18)

T1_L1RSYNCA____ETHCRS_SW3 (6,17,18)

T1_L1RXDA____ETHTXD_SW3(6,17,18)

T1_L1TSYNCA____ETHCOL_SW3 (6,17,18)

T1_L1TXDA____ETHRXD_SW3(6,17,18)

T1_L1TCLKA(16,17,18)

R/MIIRXDV-2 (17,18,22)

PC8 (14,17,18)PC9 (14,17,18)

PC14 (14,17,18)

IRDTXD(17,18,19)IRDRXD(6,17,18)

PB26(17,18)PB27(17,18)PB28(14,17,18)PB29(14,17,18)PB30(17,18)

CLK2(17,18,23)

CLK6 (6,17,18)

ATM_TXCLK (9,17,18)

CHINSb (14,15)

V1U8

V3U3_VDDH

V3U3_VDDH

V3U3_VDDH

V3U3_VDDH

V3U3

V1U8 V1U8 V1U8 V1U8 V1U8 V1U8

C730.1uF

R23

22

C740.1uF

C820.1uF

C690.1uF

C800.1uF

C700.1uF

C670.1uF

J3C

DUETPBGA357Socket IC

G6G7G8G9G10G11G12G13H7H8H9H10H11H12H13H14J7J8J9J10J11J12J13K7K8K9K10K11K12K13L7L8L9L10L11L12L13M7M8M9M10M11M12M13N7N8N9N10N11N12N13N14P7P13

E7E8

E10E12E13E15

F5F6F7F8F9

F10F11F12F13F14F15G5

G14H6

H15J6

J14K5K6

K14L6

L14L15M5M6

M14N6

N15P5P6P8P9

P10P11P12P14P15R5R7R8

R11R13R14

E5E6E9

E11E14G15

H5J5

J15K15

L5M15

N5R6R9

R10R12R15

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

VDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDHVDDH

VDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDLVDDL

+ C6610uF16V

C720.1uF

C680.1uF

C790.1uF

C600.1uF

C750.1uF

C780.1uF

+ C6310uF16V

C590.1uF

C760.1uF

C570.1uF

R26610.0K

+ C6410uF16V

J3B

DUETPBGA357Socket IC

U3U1T4

W2U4

W13U13V14

W15T15

W17W9P16

W11P17N16

U18U10V11

W12T12V13T13U14V15

W16U16V17R17U19V19T19P18

V3

W10T10U11V12W14T14U15V16T18V10R18R19

V7W6T7W8R1T6R4V9V1V2V8T3T1V4V5T8W7U9

W3R3U2T2R2U5U6U7U8

W4

W5V6

T9

PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15

PB14PB15PB16PB17PB18PB19PB20PB21PB22PB23PB24PB25PB26PB27PB28PB29PB30PB31

PC4PC5PC6PC7PC8PC9

PC10PC11PC12PC13PC14PC15

PE14PE15PE16PE17PE18PE19PE20PE21PE22PE23PE24PE25PE26PE27PE28PE29PE30PE31

PD7PD8PD9

PD10PD11PD12PD13PD14PD15

PD4

PD6PD5

PD3

C610.1uF

C580.1uF

C620.1uF

C810.1uF

C710.1uF

J71x3 Header0.1 CTR

1 2 3

+ C6510uF16V

C770.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ETHTCK

RSTXD2

PC4

RSTXD1

ERENA

L1RSYNCA

10BT/TDMA & MII2

L1RXDA

PA8

RXADDR3

MII2_RXCLK

TXADDR2

RSRXD1

PE21

PE20

RSDTR1

L1TXDA

MII2_TXERR

L1TSYNCA

ETHTX

PB25

232-2/MII2

PE23

PB23

MII2_RXD0

ETHRX

RSDTR2RSRXD2

ECLSN

PA9

TXADDR3

ADTECH(hi-phy >4)/232-1

PC5

PB24

Switch 1

Switch 2

Switch 3

MII_RXERR-2

ETHTXEN

Switch 5

E2D1D2E3F4C1B1

UTOPIA/PCMCIA

Switch 4

B6A2

D3

SEL1 low = A to B1

SEL1 high = A to B2

SEL2 low = A to B1

SEL2 high = A to B2

SEL1 low = A to B1

SEL1 high = A to B2

SEL2 high = A to B2

SEL2 low = A to B1

SEL1 high = A to B2

SEL1 low = A to B1

NO LOADSEL2 low = A to B1

SEL2 high = A to B2

DUET ADSA

CPM switching LOGIC


C




Title

Size DOCNumber:

Rev


IAP0

IAP3

IAP1

IAP7IAP6

IAP4

WAITA_B

IAP5

IAP2

OP0

SW1_ATM_TXADDR3 (7,8,9)SW1_ATM_RXADDR3 (7,8,9)

Switch_2(11)

Switch_1(11)

Switch_3(11)

SW1_ATM_TXADDR2 (7,8,9)

SW1_RSDTR1b (19)

R/MIITXERR-2____RSTXD2_SW2(5,17,18)

SW2_RSTXD2 (19)

T1_L1TXDA____ETHRXD_SW3(5,17,18)

SW3_T1_L1TXDA (16)

T1_L1RSYNCA____ETHCRS_SW3(5,17,18)T1_L1RXDA____ETHTXD_SW3(5,17,18)

SW1_RSTXD1 (19)

T1_L1TSYNCA____ETHCOL_SW3(5,17,18)

SW3_ETHCOL (20)

SW1_RSRXD1 (19)

SW3_ETHRXD0 (20)

SW3_ETHCRS (20)

SW2_RSRXD2 (19)

SW3_T1_L1RXDA (16)

SW3_ETHTXD (20)

SW2_R/MIITXERR-2 (22)SW2_R/MIIRXCLK-2 (22)

SW3_T1_L1RSYNCA (16)

SW2_RSDTR2b (19)

SW2_R/MIIRXD0-2 (22)

R/MIIRXD0-2____RSRXD2_SW2(5,17,18)R/MIIRXCLK-2____RSDTR2b_SW2(5,17,18)

RSTXD1____ATM_RXADDR3_SW1(5,17,18)RSRXD1____ATM_TXADDR3_SW1(5,17,18)

RSDTR1b____ATM_TXADDR2_SW1(5,17,18)

SW3_T1_L1TSYNCA (16)

SW3_R/MIIRXERR-2 (22)

SW3_ETHTXEN (20)

R/MIIRXERR-2____ETHTXEN_SW3(5,17,18)


SW4_BRESETA (10)Switch_4(11)

SW4_ATM_RXSOC (7,8,9)

BRESETA____ATM_RXCLK_SW4(3,9,17,18)

SW4_BWAITAb (10)

CLK6(5,17,18)CLK5(5,17,18)

SW3_R/MIITXCLK-2 (22)

SW3_ETHRXCK (20)

SW3_R/MIITXD2-2 (22)

SW3_ETHTXCK (20)

SW4_BVS1 (10)SW4_BVS2 (10)SW4_BWP (10)SW4_BCD2b (10)SW4_BCD1b (10)SW4_BBVD2 (10)SW4_BBVD1 (10)SW4_BRDY (10)

SW4_ATM_RXD7 (7,8,9)SW4_ATM_RXD6 (7,8,9)


SW4_ATM_RXD2 (7,8,9)



BVS1____ATM_RXD0_SW4(3,17,18)BVS2____ATM_RXD1_SW4(3,17,18)

BCD2b____ATM_RXD3_SW4(3,17,18)BWP____ATM_RXD2_SW 4(3,17,18)

BBVD1____ATM_RXD5_SW4(3,17,18)BCD1b____ATM_RXD4_SW4(3,17,18)

BRDY____ATM_RXD7_SW4(3,17,18)BBVD2____ATM_RXD6_SW4(3,17,18)

ATM_RXCLAV(5,10,17,18)ATM_TXCLAV(5,17,18)

SW4_ATM_TXCLAV (7,8,9)SW4_ATM_RXCLAV (7,8,9)

USBRXD(5,17,18)

USBRXN(5,17,18)USBRXP(5,17,18)

IRDRXD(5,17,18)

SW5_USBRXD (23)SW5_USBRXP (23)SW5_USBRXN (23)SW5_IRDRXD (19)

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

TP89

TP80

U8CIDTQS3VH16233

43 441314 VCC GND

GNDVCC

TP97

TP81

C870.1uF

U8BIDTQS3VH16233

28

22

23

42

41

16

17

39

38

19

20

36

35

29

1540183721342431

33

32

25

26

TEST2

14B1

14B2

9B1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

13B1

13B2

SEL2

9A10A11A12A13A14A15A16A

15B1

15B2

16B1

16B2

U9AIDTQS3VH16233

27

8

9

56

55

2

3

53

52

5

6

50

49

30

154

451

7481045

47

46

11

12

TEST1

6B1

6B2

1B1

1B2

2B1

2B2

3B1

3B2

4B1

4B2

5B1

5B2

SEL1

1A2A3A4A5A6A7A8A

7B1

7B2

8B1

8B2

TP96

C860.1uF

U9BIDTQS3VH16233

28

22

23

42

41

16

17

39

38

19

20

36

35

29

1540183721342431

33

32

25

26

TEST2

14B1

14B2

9B1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

13B1

13B2

SEL2

9A10A11A12A13A14A15A16A

15B1

15B2

16B1

16B2

U10AIDTQS3VH16233

27

8

9

56

55

2

3

53

52

5

6

50

49

30

154

451

7481045

47

46

11

12

TEST1

6B1

6B2

1B1

1B2

2B1

2B2

3B1

3B2

4B1

4B2

5B1

5B2

SEL1

1A2A3A4A5A6A7A8A

7B1

7B2

8B1

8B2

C880.1uF

R283

10.0K

R28510.0K

U10CIDTQS3VH16233

43 441314 VCC GND

GNDVCC

R28610.0K

C830.1uF

TP94

U8AIDTQS3VH16233

27

8

9

56

55

2

3

53

52

5

6

50

49

30

154

451

7481045

47

46

11

12

TEST1

6B1

6B2

1B1

1B2

2B1

2B2

3B1

3B2

4B1

4B2

5B1

5B2

SEL1

1A2A3A4A5A6A7A8A

7B1

7B2

8B1

8B2

TP78

C840.1uF

TP86

R28410.0K

U10BIDTQS3VH16233

28

22

23

42

41

16

17

39

38

19

20

36

35

29

1540183721342431

33

32

25

26

TEST2

14B1

14B2

9B1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

13B1

13B2

SEL2

9A10A11A12A13A14A15A16A

15B1

15B2

16B1

16B2

R29310.0K

TP87TP88

TP79

TP95

U9CIDTQS3VH16233

43 441314 VCC GND

GNDVCC

C850.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

See User Manual for Layout Rules1. Traces between 98408 and PE-67583 should be short2. Traces between PE-67583 and RJ-45 should be short3. Add surface ground fill between TX and RX pairs4. No power and ground planes under transformer and RJ-45

planeplane

TxLED

add this text to silkscreen

add this text to silkscreen

RxLED

FIDUCIALSFOR U11

DUET ADSA

ATM25


C




Title

Size DOCNumber:

Rev


AD4

AD2AD1

AD5

AD3

AD0

AD6

RESET~

RD~CS~

WR~

AD7

ALE

INT~

V3U3_ATM25 AVDD_ATM25

ATM_TXD1(5,8,9,17,18)ATM_TXD2(5,8,9,17,18)

ATM_TXD4(5,8,9,17,18)

ATM_TXD0(5,8,9,17,18)

ATM_TXD7(5,8,9,17,18)ATM_TXD6(5,8,9,17,18)

ATM_TXD3(5,8,9,17,18)

ATM_TXD5(5,8,9,17,18)

ATM_TXEN(5,8,9,17,18)

ATM_TXCLK_ATM25(9)ATM_TXSOC(5,8,9,17,18)

ATM_RXEN(5,8,9,17,18)

ATM_RXCLK_ATM25(9)

RST_25B(11)

RD_ATM25B(11)CS_ATM25B(11)

WR_ATM25B(11)

ALE_ATM25(11)

ATM_RXADDR1(5,8,9,17,18)ATM_RXADDR0(5,8,9,17,18)


SW4_ATM_RXSOC(6,8,9)

IRQ3B(3,8,16,17,18)

SW4_ATM_TXCLAV(6,8,9)

SW4_ATM_RXD4(6,8,9)

SW4_ATM_RXD6(6,8,9)SW4_ATM_RXD7(6,8,9)



SW4_ATM_RXD5(6,8,9)

AD[0:7](8,11,16)

SW4_ATM_RXCLAV(6,8,9)

V3U3

V3U3

V3U3 V3U3

V3U3

AVDD

AVDD

AAnalog1

AAnalog1

AAnalog1

AAnalog1

AAnalog1

AAnalog1

C95.01uF

R2982.5

C1000.1uF

+ C9810uF16V

J8RJ45

Shielded

87654321

9

10

P8P7P6P5P4P3P2P1

GNDA

GNDB

R34

33.2

C109

470pFC0G

R26619

C92.01uF

R24

499

C96.01uF

C1050.1uF

R35

499

L3

3 pin FB

1 3

2

C90.01uF

C97.01uF

C111

470pFC0G

R3063.4

C1010.1uF

LPF

TRANSMIT CHANNEL

RECEIVE CHANNEL

LPF

T1

PE-67583

1

3

5

4

2

6

11 13

16

15

14

7

8

10

9

12

TX+

MID1

AGND1

MID2

TX-

NC1

NC2 MID3

RX+

RX-

MID4

RJ_TX+

RJ_TX-

RJ_RX+

RJ_RX-

AGND2

C91.01uF

R25

47

L2

3 pin FB

1 3

2

C1060.1uF

R3363.4

R36

0

C1030.1uF

+ C9910uF16V

C93.01uF

C1070.1uF

U11B

IDT77V107

78818386

6234368

77808287

2526325063

94

91

98

1

AVDDAVDDAVDDAVDD

VDDVDDVDDVDD

AGNDAGNDAGNDAGND

GNDGNDGNDGNDGND

VDD

GND

VDD

GNDC1020.1uF

D1

HSMG-C650Green

C1080.1uF

FID2

1.2mm Mask0.6mm Pad

C1130.1uF

U12

32.0MHz100PPM

12

34

NCGND

OUTVCC

U11AIDT77V107

565553

6766656462616059

27

242122

3940414244454647

3736353433

28

302931

54

5758

92

93

85

84

69

79

549

717273

5270

3

2

4

51

74888990

95

9697

75

789

1011121314

1516171819

20

38

48

99100

76

RDWRINT

AD7AD6AD5AD4AD3AD2AD1AD0

TXCLK

TXCLAVTXENTXSOC

RXDATA7RXDATA6RXDATA5RXDATA4RXDATA3RXDATA2RXDATA1RXDATA0

RXADDR4RXADDR3RXADDR2RXADDR1RXADDR0

RXCLK

RXCLAVRXENRXSOC

RESET

CSALE

TXD-

TXD+

RXD+

RXD-

RCO

OSC

NCNC

NCNCNC

NCNC

TxREF

RxREF

TxLED

RxLED

NCNCNCNC

NC

NCNC

DA

TXDATA0TXDATA1TXDATA2TXDATA3TXDATA4TXDATA5TXDATA6TXDATA7

TXADDR0TXADDR1TXADDR2TXADDR3TXADDR4

TXPARITY

RXPARITY

RPLI

M1M0

SE

D2

HSMG-C650Green

L43.3uH500mA

FID1

1.2mm Mask0.6mm Pad

C112.01uF

C1100.1uF

R3210.0K

C94.01uF

JP1

Jumper .2TH1 2

C1040.1uF

R27

47

R3110.0K

R28

33.2

C89.01uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FIDUCIALSFOR U13

Decoupling capacitors for VDD pins

Design the PCB with separate PWR planesfor the Transmitter and Receiver.

Connections between U13 pins 47/48 andU14 pins 8/7 should be of minimumlength.

8

3

RX PWR Plane

9

TX PWR Plane

50 ohm Microstrip should be used.

5

1

6

2

4

7

Place contiguous GND under U13.

place C123 and C124near U15

place U15 near U13

place C120near U13

VDD_CS_1 Plane

VDD_TPE_1 Plane

VDD_CR_1 Plane

VDD_RPE_1 Plane

VDD_SP_1 Plane

no load

Default-Load A

DUET ADSA

ATM155


C




Title

Size DOCNumber:

Rev


TDOT_1TDOC_1

RDIC_1SD_1

RDIT_1

19_44MHZ_2

VDD_TPE_1

VDD_CR_1

VDD_RPE_1

VDD_CS_1

VDD_SP_1

VCC_RX_1

VCC_TX_1

19_44MHZ_1

MD6

MD2MD1

MD3

MD7

MD0

MD5MD4

AD3AD2

AD0AD1

AD5AD4

AD6

ATM_TXD2(5,7,9,17,18)ATM_TXD1(5,7,9,17,18)

ATM_TXD3(5,7,9,17,18)

ATM_TXD0(5,7,9,17,18)

ATM_TXD7(5,7,9,17,18)

ATM_TXD4(5,7,9,17,18)

ATM_TXD6(5,7,9,17,18)ATM_TXD5(5,7,9,17,18)

ATM_TXEN(5,7,9,17,18)

ATM_TXCLK_ATM155(9)

ATM_TXSOC(5,7,9,17,18)

ATM_RXEN(5,7,9,17,18)

CS_ATM155B(11)

RST_155B(11)

WR_B(11,16)RD_B(11)

ATM_RXADDR1(5,7,9,17,18)


SW4_ATM_TXCLAV(6,7,9)

IRQ3B(3,7,16,17,18)

AD[0:6](7,11,16)

MD[0:7](11,16)

ATM_RXCLK_ATM155(9)

SW4_ATM_RXSOC(6,7,9)

SW4_ATM_RXD3(6,7,9)

SW4_ATM_RXD5(6,7,9)

SW4_ATM_RXD1(6,7,9)

SW4_ATM_RXD4(6,7,9)

SW4_ATM_RXD6(6,7,9)

SW4_ATM_RXD0(6,7,9)

SW4_ATM_RXD7(6,7,9)

SW4_ATM_RXD2(6,7,9)

ATM_RXADDR0(5,7,9,17,18)

155MPSEL(11)SW4_ATM_RXCLAV(6,7,9)

V3U3

VDD155

VDD155

VDD155

VDD155

VDD155

VDD155V3U3

VDD155

VDD155

VDD155

VDD155

VDD155

VDD155

VDD155

VDD155

VDD155

VDD155

U15

19.44MHz20PPM

12

34 NC

GNDOUTVDD

+ C12510uF16V

L7 3 pin FB1 3

2

C1280.1uF

+ C11910uF16V

FID3

1.2mm Mask0.6mm Pad

C1320.1uF

+ C12110uF16V

R39

130

U13B

UPD98404

12736607395

108119129

1637717286

102109110124143144

394549

53

35

3233

58

4246

5056

38

293034

57

VDDVDDVDDVDDVDDVDDVDDVDDVDD

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

VDD-TPEVDD-TPEVDD-TPE

VDD-RPE

VDD-SP

VDD-CSVDD-CS

VDD-CR

GND-TPEGND-TPE

GND-RPEGND-RPE

GND-SP

GND-CSGND-CSGND-CS

GND-CR

+ C13110uF16V

FID4

1.2mm Mask0.6mm Pad

C1300.1uF

SerialPMD

CPUManagementInterface

UtopiaRx

UtopiaTx

ParallelPMD

JTAGPort

U13A

UPD98404

9897

100

7980818283

8788899091929394

40414344

4847

118117116115114113112111

107106105104103

120123121122

130131132133134135136137

138139140141142

128125127126

78

9996

101

66656463

2423

6261

222120191817

84

77

856768

2526

2831

59

6970

51525455

101112131415747576

789

43526

R/W_B/WR_BDS_B/RD_B

PHINT_B

MADD1MADD2MADD3MADD4MADD5

MD0MD1MD2MD3MD4MD5MD6MD7

TFKTTFKCTCOTTCOC

TDOCTDOT

TDI7TDI6TDI5TDI4TDI3TDI2TDI1TDI0

TADD4TADD3TADD2TADD1TADD0

TCLKFULL_B/TCLAVTENBL_BTSOC

RDO0RDO1RDO2RDO3RDO4RDO5RDO6RDO7

RADD0RADD1RADD2RADD3RADD4

RCLKEMPTY_B/RCLAVRENBL_BRSOC

MADD0

ACK_B/RDY_BCS_B

RESET_B

RPD5RPD4RPD3RPD2

TPD7TPD6

RPD1RPD0

TPD5TPD4TPD3TPD2TPD1TPD0

MADD6

MSEL

UMPSELRPD6RPD7

TPCTFC

REFCLKAIN1

RPC

PSEL0PSEL1

RCITRCICRDITRDIC

PHYALM0PHYALM1PHYALM2

TFSSTxFPTCL

RxFPRCL

PMDALM

TEST0TEST1TEST2

JDIJDOJMSJCK

JRST_B

C1140.1uF

R37

130

R42

82.5

C1240.1uF

R4682.5

C1160.1uF

L8

3 pin FB

1 3

2

R4482.5

L11

3 pin FB

1 3

2

R41

130

R47

0

C123.01uF

C120

0.1uF

C1150.1uF

R3882.5

B

ARJ22

Zero Ohm

13

2

R43

130

L5 3 pin FB1 3

2

C1340.1uF

C1180.1uF

L9

3 pin FB

1 3

2

+ C12710uF16V

Quantizer

Driver

Preamp

LED

Photodiode

Duplex OpticalReceptacle

U14HFBR-5805

1

234

5

6

78

9

10 11

VEE_RX

RDRDSD

VCC_RX

VCC_TX

TDTD

VEE_TX

MT_

HO

LE1_

GN

D

MT_

HO

LE2_

GN

D

R45

130

+ C13310uF16V

L6 3 pin FB1 3

2

C1350.1uF

C1170.1uF

L10

3 pin FB

1 3

2

C1360.1uF

C1220.1uF

R4082.5

L12

3 pin FB

1 3

2

C1370.1uF

C1260.1uF

+C12910uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

UTOPIA TX

Adtech TX

PD9

PD15PD13

PD6PD4

PD3

PD14PD12PD7PD5

IAP0

IAP7

WAIT_A

IAP4IAP6

PB17

OP0

IAP1IAP2

IAP5

UTOPIA RX

IAP3

Adtech RX

PB20SW_PB26

SW_PB24PB15

PB21

PB22

PD10

PD11

PB18PB14

PC15

PB16

SW_PB25

NO L

OAD

NO L

OAD

DUET ADSA

ADTECH


C




Title

Size DOCNumber:

Rev


TxD4TxD2 TxD3

TxD6

TxD1

TxD7TxD5

TxD0

RxD0

RxD5

RxD2RxD1RxD3

RxD7RxD6RxD4

TxSOC

RxSOC

ATMRX_CLK_PWR ATMTX_CLK_PWR

ATM_RXCLK_ADTECH

ATM_TXCLK_ADTECH

TxADDR0_masterTxADDR2_master

TxADDR3_masterTxCLAV0_master

TxADDR4_master

TxADDR1_master

TxEN_master

RxEN_master

RxADDR4_masterRxADDR2_masterRxADDR0

RxCLAV0_masterRxADDR3_master

RxADDR1_master

ATM_TXD0(5,7,8,17,18)ATM_TXD3 (5,7,8,17,18)

ATM_TXD5(5,7,8,17,18)ATM_TXD7(5,7,8,17,18)

ATM_TXD6 (5,7,8,17,18)

ATM_TXSOC (5,7,8,17,18)

ATM_TXD4 (5,7,8,17,18)ATM_TXD2(5,7,8,17,18)

ATM_TXD1 (5,7,8,17,18)

SW4_ATM_RXD4 (6,7,8)SW4_ATM_RXD3 (6,7,8)SW4_ATM_RXD1 (6,7,8)

SW4_ATM_RXSOC (6,7,8)




ATM_TXCLK_ATM25 (7)ATM_TXCLK_ATM155 (8)

ATM_RXCLK_ATM25 (7)ATM_RXCLK_ATM155 (8)


ATM_TXCLK(5,17,18)

ATM_TXADDR0(5,7,8,17,18)SW1_ATM_TXADDR2 (6,7,8)

SW1_ATM_TXADDR3(6,7,8)SW4_ATM_TXCLAV(6,7,8)

ATM_TXADDR4 (5,7,8,17,18)

ATM_TXADDR1 (5,7,8,17,18)

ATM_TXEN (5,7,8,17,18)

ATM_RXEN (5,7,8,17,18)

ATM_RXADDR4 (5,7,8,17,18)ATM_RXADDR2(5,7,8,17,18)ATM_RXADDR0(5,7,8,17,18)

SW1_ATM_RXADDR3(6,7,8)SW4_ATM_RXCLAV(6,7,8)

ATM_RXADDR1 (5,7,8,17,18)

V3U3

V3U3

V3U3

V3U3

C384.01uF

C377120pFC0G

U59ACY2309

231415

671011

16

9

1

8

CLKA1CLKA2CLKA3CLKA4

CLKB1CLKB2CLKB3CLKB4

CLKOUT

S1

REF

S2

U59B

CY2309

4125

13 VDDGNDGND

VDDC3790.1uF

L53 3 pin FB1 3

2

R29110.0K

+ C38210uF16V

R27710.0K

R28810.0K

C381120pFC0G

TX DATA 0135791113151719212325272931

494745434139373533

TX DATA 2

TX DATA 5TX DATA 7TX DATA 8

TX DATA 1TX DATA 3TX DATA 4TX DATA 6

GND

TX DATA 10

TX DATA 13GND

TX DATA 15TX PARITYTX ADDR 0

GNDTX ADDR 3TX CLAV 0TX CLAV 1TX CLAV 3

GNDPTX ADDR 0PTX ADDR 2PTX ADDR 3PTX CLAV 0

GNDPTX CLAV 3PTX CLOCK

GNDTX DATA 9TX DATA 11TX DATA 12TX DATA 14GNDTX SOC

20

38

3032

50

2

22

44

40

16

26

12

28

48

42

14

36

46

18

8

24

34

64

10

TX ADDR 1TX ADDR 2TX ADDR 4GNDTX CLAV 2TX ENABLETX CLOCK

GND

GND

PTX ADDR 1

PTX ADDR 4PTX CLAV 1PTX CLAV 2PTX ENABLE

J10txADTECH Header Shrouded

0.1 CTR

R27810.0K

C380.01uF

RX DATA 0135791113151719212325272931

494745434139373533

RX DATA 2

RX DATA 5RX DATA 7RX DATA 8

RX DATA 1RX DATA 3RX DATA 4RX DATA 6

GND

RX DATA 10

RX DATA 13GND

RX DATA 15RX PARITYPRX ADDR 0

GNDPRX ADDR 3PRX CLAV 0PRX CLAV 1PRX CLAV 3

GNDRX ADDR 0RX ADDR 2RX ADDR 3RX CLAV 0

GNDRX CLAV 3RX CLOCK

GNDRX DATA 9RX DATA 11RX DATA 12RX DATA 14GNDRX SOC

20

38

3032

50

2

22

44

40

16

26

12

28

48

42

14

36

46

18

8

24

34

64

10

PRX ADDR 1PRX ADDR 2PRX ADDR 4GNDPRX CLAV 2PRX ENABLEPRX CLOCK

GND

GND

RX ADDR 1

RX ADDR 4RX CLAV 1RX CLAV 2RX ENABLE

J9 rxADTECH Header Shrouded

0.1 CTR

R279510

U58ACY2309

231415

671011

16

9

1

8



CLKOUT

S1

REF

S2

C3830.1uF

L54 3 pin FB1 3

2

R292510

U58B

CY2309

4125

13 VDDGNDGND

VDD

RP25

4x22

12345

678

R29010.0K

R28910.0K

RP26

4x22

12345

678

+ C37810uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DUET ADSA

PCMCIA


C




Title

Size DOCNumber:

Rev


PCCA1

PCCD3

BWE3b

PCCA10

PCCD14

BD12

PCCA7

BA20

PCCD10

PCCD10

BPOEAb

BD15

PCCD8

PCCA16

BWE0b

PCCA25

PCCA10

PCCD6

PCCA11

BALEA

BA21

PCCD7

PCCA16

BA29

PCCA19

PCCA21BA19

PCCA22

BD2

PCCD1

CVS1

PCCENb

PCCA8

PCCA22

BPOEAb

BD13

PCCA2

BA24

PCCD2

BA11

CRDY

BD9

CINPACKb

PCCA3

BA22

CINPACKb

BBVD2

BRDY

BD14

PCCA17

BA16

PCCD13

CCD2b

BA8

PCCA11

BWP

PCCA17

PCCA6PCCD5

PCCD11

PCCA18

PCCD15

CCD2bCCD1b

BCD1b

PCCD7

BD3

CVS1

PCCA1

PCCA19

PCCD1

PCCA12

BCD2b

BVS1

CVS2

CWP

PCCD3

PCCD9

PCCA24

BA27

PCCA14

PCCA6

PCCD4

BA13

PCREGb

PCCD0

PCCD8

BA15

PCCA9

PCCA0

BA6

PCCD12

CVS2

PCCA18

BD5

BD0

PCCA2

BA30

BD4

PCCD2

BA17

PCCA0

BA25

PCCA23

BD10

BA12

PCCA3

PCCA13

CVS2

PCCA[0:25]

BWAITAb

PCCD15

BD11

BA14

BWE2b

PCCA5

PCCA20

BVS2

BA18

PCCA15

PCCA7

BA28

PCCD6

BA10

CCD1b

PCCD12PCCD5

PCCA4

PCCD13

PCCD[0:15]

BD1PCCA14

BD7

BD8

BBVD1

PCCA25

PCCA4 PCCD4

BA9

PCCA9

PCCA12

BA31

CBVD2

PCCA5

PCCA13

BA7

PCCD0

PCCA15

PCCA21

BA23 PCCA8

PCCD9

BWE1b

PCREGb

PCCA23

CVS1

BA26

PCCD11

PCCA20

PCCA24

BD6

PCCD14

CBVD2

CWP

CBVD1

CWAITAb

CBVD1

CWAITAb

BSPKOUT

BD[0:15](2,4,11,18,24)

PCRWb(24)

BA[6:31](2,4,11,18,24)

REGAb(3,17)

BWE2b(2,4)

PCCVPP (13)

BALEA(4,18)

PCCENb(11,14,24)

PBCE2Ab(4)

PCOENb(24)

PBCE1Ab(4)

BWE3b(2,4)

PCCVCC (13,14)

BPOEAb(4)

BWE1b(2,4)SW4_BRESETA(6)

BWE0b(2,4,18)

PCEENb(24)

SW4_BVS1 (6)

SW4_BBVD1 (6)

SW4_BRDY (6)SW4_BCD2b (6)

ATM_RXCLAV (5,6,17,18)SW4_BWAITAb (6)

SW4_BCD1b (6)

SW4_BVS2 (6)

SW4_BWP (6)

SW4_BBVD2 (6)

SPKROUT(3,17)

PCCENb(11,14,24)

PCCVCC (13,14)

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

RN28x10K

12346789

105

J11PCMCIA CONNECTOR

29282726252423221211

8102113142019464748495053545556

7426115

9444558

30313223456

6465663738394041

16335960626343573667

17511852

1343568

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25

CE1CE2REGWE/PCMOEIORDIOWRRESET

D0D1D2D3D4D5D6D7

D8D9

D10D11D12D13D14D15

RDY/BSYWP

WAITINPACK

BVD2BVD1

VS1VS2CD1CD2

VCC1VCC2VPP1VPP2

GND1GND2GND3GND4

U16A74LVCH32373A

A5A6B5B6C5C6D5D6

E5E6F5F6G5G6H6H5

A4A3

H4H3

A2A1B2B1C2C1D2D1

E2E1F2F1G2G1H1H2

1D11D21D31D41D51D61D71D8

2D12D22D32D42D52D62D72D8

LE1OE1

LE2OE2

1Q11Q21Q31Q41Q51Q61Q71Q8

2Q12Q22Q32Q42Q52Q62Q72Q8

U16C74LVCH32373A

F4L3L4P3

K3K4M3M4N3N4R3R4

P4

C3C4F3

B3B4D3D4E3E4G3G4

VCCVCCVCCVCC


VCC

VCCVCCVCC


U20E74LCX125

714 GNDVCC

C1410.1uF

U18B74LVCH162244

410152128343945

7183142


VCCVCCVCCVCC

U19B74LVCHR162245A

410152128343945

7183142


VCCVCCVCCVCC

U18A74LVCH162244

47464443

1

4140383748

36353332

25

3029272624

2356891112

1314161719202223

1A01A11A21A3

OE1

2A02A12A22A3OE2

3A03A13A23A3

OE3

4A04A14A24A3OE4

1Y01Y11Y21Y32Y02Y12Y22Y3

3Y03Y13Y23Y34Y04Y14Y24Y3

C1490.1uF

C1530.1uF

C147 0.1uF

R52 75C1540.1uF

R5110.0K

C1420.1uF

U20B74LCX125

5 6

4

C1380.1uF

RN1

8x10K

12346789

105

C146 0.1uF

R4910.0K

C1480.1uF

RP17

8x10K

12345678

161514131211109

C1430.1uF

C1390.1uF

U20C74LCX125

12 11

13

U16B74LVCH32373A

J5J6K5K6L5L6M5M6

N5N6P5P6R5R6T6T5

J4J3

T4T3

J2J1K2K1L2L1M2M1

N2N1P2P1R2R1T1T2

3D13D23D33D43D53D63D73D8

4D14D24D34D44D54D64D74D8

LE3OE3

LE4OE4

3Q13Q23Q33Q43Q53Q63Q73Q8

4Q14Q24Q34Q44Q54Q64Q74Q8

+S1

QMB-0130 Ohm

U20A74LCX125

2 3

1

C1550.1uF

C1440.1uF

R531.00K

U19A74LVCHR162245A

235689

1112

1314161719202223

4746444341403837

3635333230292726

1

24

48

25

1B11B21B31B41B51B61B71B8

2B12B22B32B42B52B62B72B8

1A11A21A31A41A51A61A71A8

2A12A22A32A42A52A62A72A8

DIR1

DIR2

OE1

OE2

C1400.1uF

C1500.1uF

C1510.1uF

C1520.1uF

C1450.1uF

C157 0.1uF

C156

0.1uF

R5010.0K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

This reset (RST_T1A) isactive on low-to-highedge. Normal state afterreset is low.

*232-1

S2 TABLES2 OFF

4

ON

2

1

3

232-2

*ATM

*MII2

*T1/MII2

PCMCIA

ADTECH

10BT

* = default

SoftSwitch

Disable

Enable

DUET ADSA

Control


C




Title

Size DOCNumber:

Rev


MD4MD3MD2

MD6MD7

MD5

MD0MD1

AD3

AD6

AD1

AD5

AD2

AD7

AD4

AD0

BA21BA22BA23BA24

BA31BA30BA29BA28BA27BA26BA25

BD0BD1BD2BD3

BD7BD6BD5BD4

TDI

TMSTDOTCK

ALE_ATM25 (7)

CS_ATM25B (7)

WR_ATM25B (7)

RD_ATM25B (7)

RST_25B (7)

MD[0:7] (8,16)

AD[0:7] (7,8,16)

155MPSEL (8)

CS_ATM155B (8)

WR_B (8,16)

RD_B (8)

RST_155B (8)

T1A_CS~ (16)

RST_T1A (16)

BA[21:31](2,4,10,18,24)

BD[0:7](2,4,10,18,24)

OE~(2,3,4,17)CS5b(3,17,24)

RPORIb(3,14,15,17,18)RWb(3,4,17,18)

TSb(3,4,17)WE0b(2,3,4,17)

HRESETb(3,15,17,18,24)PCCENb(10,14,24)

Switch_1 (6)Switch_2 (6)Switch_3 (6)Switch_4 (6)

R/MIIRXENC-1 (14,21)

RSTR/MIIb-1 (21)

BSYSCLK1(19)

R/MIIRXENC-2 (14,22)RSTR/MIIb-2 (22)

TAb(3,17,18,24)

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

R6010.0K

TP23

TP22

C159.01uF

R6110.0K

U22BEPM3128

5158

130123115

5095732476

144

3377643135

2613941712452105855711459129

VCCINTVCCINTVCCINTVCCINTVCCIOVCCIOVCCIOVCCIOVCCIOVCCIOVCCIO

GNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

J12

1x3 Header0.1 CTR

123

TP24

C1580.1uF

C161.01uF

R6210.0K

TP25

C163.01uF

J13

2x5 Header0.1 CTR

12345678910

C165.01uF

R5410.0K

U22AEPM3128

699380828365966315

16182122232527282930

72

56789

101114

38141142136137139

6145

40100678179789798

86

140

557111768

134

127

116113

707411960

53125

881028456

143

110118109

894

10420

11187

91

101128

112

126

12

12193435364346474849667590

103108120121122

31323739414244549299106107131132133138

AD_ATM0AD_ATM1AD_ATM2AD_ATM3AD_ATM4AD_ATM5AD_ATM6AD_ATM7ADDR_PQ21

ADDR_PQ22ADDR_PQ23ADDR_PQ24ADDR_PQ25ADDR_PQ26ADDR_PQ27ADDR_PQ28ADDR_PQ29ADDR_PQ30ADDR_PQ31

ALE_ATM25

BDAT0BDAT1BDAT2BDAT3BDAT4BDAT5BDAT6BDAT7

CE1CE2CLKFUNC_SEL0FUNC_SEL1FUNC_SEL2

IPASEL0IPASEL1

MD0MD1MD2MD3MD4MD5MD6MD7

MUXSEL

nCS

nCS_ATM25nCS_ATM155nCS_FramernMII_RX_EN

nOE

nPORESET

nRD_ATM25nRD_Dual

nRESET_ATM25nRESET_ATM155nRESET_Framer

nRESET_MII

nTSnWE

nWR_ATM25nWR_Dual

PDSEL0PDSEL1

RD_nWR

SPARE0SPARE1SPARE2

TCKTDITDOTMS

nMII_RX_EN_2nRESET_MII_2

FUNC_SEL3

TP4CLKIN

TA

OE1

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

Spare3Spare4Spare5Spare6Spare7Spare8Spare9

Spare10Spare11Spare12Spare13Spare14Spare15Spare16Spare17Spare18

R5710.0K

C1620.1uF

R5510.0K

R5810.0K

R5610.0K

S2

4 Position switch

5321

678

4

C1640.1uF

C1600.1uF

R5910.0K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DUET ADSA

blank


C




Title

Size DOCNumber:

Rev


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NO LOAD

NO LOAD

NOTE: If no DUET, voltage won'tbe right...

NOTE: If no DUET, voltage won'tbe right...

DUET ADSA

Power


C




Title

Size DOCNumber:

Rev


PCCVPP0PCCVPP1

PCCVCC1PCVCC0PCVCC0(24)

PCCVCC1(24)

PCCVPP1(24)PCCVPP0(24)

PCCVPP (10)

PCCVCC (10,14)

VDB

VCC

VPP

VCC

V3U3

A

VPPIN

V3U3_VDDH

V3U3

V1U8

VCC

VCC

VCC

VCC

VCC

R260849

C1690.1uF

+ C172100uF10V

12

C3760.1uF

+ C1711uF16VJ14

1x3 TERM BLK R/A5.08MM CTR

123

cloc

kwis

e

3

2

Wipe

r

CW

1 CCW

RV41K

31

2

U27G74AC14

7 14GND VCC

Q1

MMDF3N03HD

2

3

4 5

7

1

6

8

+ C18210uF16V

R26710.0K

C170.01uF

F2

SMD150/33

L13

8000mA300 Z @ 100MHz

6

3

5

4

1

2

87

U23UMIC29501-3.3BU

5

2

163

4

FLG

VIN

ENABLETABGND

VOUT

JP2

Jumper .2TH1 2

D41SMC5.0AT3

5.0V

12

+C18410uF16V

C177.01uF

C187

0.1uF

TP15

1

JP13

Jumper .2TH1 2

JP6Jumper .2TH

1 2

JP7Jumper .2TH

1 2

+ C17310uF16V

JP12

Jumper .2TH1 2

+ C17410uF16V

C1760.1uF

C179.01uF

MH3125mil Drill NPT

No Ring

R70

5.11K

R67

124K

R63402

U26

LTC1315

2418

5634 2

8

171314

17

1112

910

231920

2216

2115

AVCCINBVCCIN

AVCC0AVCC1AEN0AEN1 ASHDN

BSHDN

BVPPOUTBDRV5BDRV3

AVPPINBVPPIN

BVCC0BVCC1BEN0BEN1

AVPPOUTADRV5ADRV3

GNDGND

VCCVCC

D71SMC12AT3

12V

12

+ C1831uF16V

D3

20VMBRD620CT

6A

31

4

+ C372100uF10V

12

Q2

MMDF3N03HD

2

3

4 5

7

1

6

8

C166

1000pF

JP5Jumper .2TH

1 2

C189

100pFC0G

+ C17510uF16V

C1900.1uF

C1781000pF

MH4125mil Drill NPT

No Ring

F1

SMD260

+ C375100uF10V

12

TABconnectedto pin 2

U24MIC29500

1

42

3VIN

TABGND

VOUT

JP8Jumper .2TH

1 2

D10

MMBD914LT1

13

GND

GND

GND

GND

S3

Togg

le S

witc

h 1

3

2

4567

+ C18068uF20V

+ C168100uF10V

12

TP8

1

JP11

Jumper .2TH1 2

C369.01uF

C3730.1uF

D9

MMBD914LT1

13

R65

124K

D6

20VMBRD620CT

6A

31

4

MH2125mil Drill NPT

No Ring

C1850.1uF

C3680.1uF

U25MIC39151-1.8BU

2

63

4

1

5

VIN

TABGND

VOUT

ENABLE

FLG

J151x2 TERM BLK5.08MM CTR

12

C3740.1uF

U27B

74AC14

34

C167.01uF

C188

0.01uFX7R1KV

MH1125mil Drill NPT

No Ring

cloc

kwis

e

3

2

Wipe

r

CW

1 CCW

RV31K

31

2

R26110.0K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RS232 PORT 2 ENABLED

SDRAM ENABLED

ETHERNET ENABLED

RUN

FLASH ENABLED

5V POWER

RESERVED

INFRA-RED ENABLED

RS232 PORT 1 ENABLED

SIGNAL LAMP

PCMCIA ENABLED

PC9

PB28

100BaseT-2

PC8

USB Enabled

100BaseT-1

PB29

PC14

DUET ADSA

Reset & LED's


C




Title

Size DOCNumber:

Rev


CHINSb

RSEN2b(19,24)ETHENb(20,24)

RUN(15)

RESERVED(24)

SDRAMEN(2,24)

PCCENb(10,11,24)

IRDENb(19,24)RSEN1b(19,24)

CHINSb(5,15)

FENb(24)

SGLAMPb(24)

RPORIb (3,11,15,17,18)

PCCVCC (10,13)

RPORI (24)

R/MIIRXENC-1(11,21)R/MIIRXENC-2(11,22)

nUSBEN(23,24)

PB28(5,17,18)PB29(5,17,18)

PC8(5,17,18)PC9(5,17,18)

PC14(5,17,18)

VCC

V3U3

V3U3

VCC

V3U3 V3U3

V3U3

V3U3

VCCVCC

U31A74LS244

2468

11131517

18161412

9753

1

19

A0A1A2A3

B0B1B2B3

YA0YA1YA2YA3

YB0YB1YB2YB3

1G

2G

U30A74LS244

2468

11131517

18161412

9753

1

19

A0A1A2A3

B0B1B2B3

YA0YA1YA2YA3

YB0YB1YB2YB3

1G

2G

D26 HSMY-C650

Yellow

D22 HSMY-C650

Yellow

R79 150

U29B

74AC05

3 4

D14 HSMY-C650

Yellow

TP12

U27D

74AC14

9 8

D24 HSMY-C650

Yellow

D23 HSMY-C650

Yellow

U28DS1818

2

31VCC

GNDRST

TP10

U29G74AC05

14 7VCC GND

R82 150

R741.00K

D19 HSMY-C650

Yellow

C193

0.1uF

D11 HSMG-C650

Green

U29C

74AC05

5 6

R71 150

R85 150

TP11

D13MMBD914LT1

13

D28 HSMY-C650

Yellow

U31B74LS244

1020 GNDVCC

D16 HSMY-C650

Yellow

R83 150

U27C

74AC14

5 6

R751.00K

R87 150

R89 150

D20 HSMY-C650

Yellow

R91 150

TP5

D27 HSMY-C650

Yellow

TP13

U29D

74AC05

9 8

R72 150D12 HSMG-C650

Green

TP14

R77 150

C195

0.1uF

D17 HSMY-C650

Yellow

D30 HSMY-C650

Yellow

U27E

74AC14

11 10

R80 150

U29E

74AC05

11 10

D21 HSMY-C650

Yellow

D25 HSMY-C650

Yellow

U20D74LCX125

9 8

10

D29 HSMY-C650

Yellow

D15 HSMG-C650

Green

R78 150

U29A

74AC05

1 2

R76 51.1K

+ C191100uF10V

12

D18 HSMY-C650

Yellow

U30B74LS244

1020 GNDVCC

R84 150

R86 150U29F

74AC05

13 12

R81 150

R88 150

R731.00K

R90 150C194

0.1uF

R92 150

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EPP

BDM_CLOCKISP_EPP_I/F

EPPCompliant1284A

Parallel - OnCE

BDM Conn

SerialEPP

BUS_SWITCH

1284 TRANSCEIVER

"TO CHIP"

SERIAL

PLD

EPP ENb / SERIAL_EN

DUET ADSA

HOST & BDM Interface


C




Title

Size DOCNumber:

Rev


DB6/IDENT

PP_AD5

F_DB2

PP_AD[0:7]

BDM_DSCK/SER_TCK

PP_AD7

PP_AD2 F_DB5PP_AD1

BDM_DSCK

IRQ-

PP_AD0

SRESETb

PP_INTb

PP_AD2

HRESETb

SERIAL_ENb

F_DB1

PP_AD6

Write-

RPORIb

PP_WEb

DB4/TRST_IN

FREEZE1

VFLS1

BDM_DSDI

F_INb

F_WEb

DB7

PP_AD7

Select_5V_OUT

F_DSTRb

EPP_ISPTDO

DB0/RESET

DB3/TDI_IN

F_DB4

PP_BUSY_OUT

PP_AD4

DB5/DE_IN

BDM_DSDI/SER_TDI

PP_INb

CHINSb

CON_DSCK

EPP_ISPTMS

DB1/TMS_IN

EPP_ENb

EPP_ISPTDI

PP_VFLSP0

F_DB3

BDM_DSDO/SER_TDO

PP_AD3

SRESETb

PP_AD4

F_ASTRb

PP_AD5

DB2/TCK_IN

EPP_ISPTCK

PP_AD1

F_RSTb

EPP_CLK

F_DB6

PP_DSTRb

Reset-

PP

_AD

[0:7

]

PP_AD3

PP_DSTRb

F_DB7

PP_AD6

PP_INb

F_DB0

PP_VFLSP0

CON_DSDI

Dstrobe-

HRESETb

CON_DSDO

PP_AD0

Astrobe-

PP_WEb

PP_BUSY_OUT

RPORIb

RUN

BDM_DSDO

PP_INTb

EPP_ENb_SW

EPP_ENb_SW

VFLSR2b

PP_DIR

F_INTbF_VFLSP0F_VFLSP1

F_SELECTF_BUSY

PP_VFLSP1

PP_VFLSP1

FREEZE0

Wait-/TDO_OUT

IN-

VFLS0VFLS1

PP_RSTb

EPP_CLK

PP_ASTRb

PP_ASTRb

VFLS0

PP_RSTb

PP_INTb(17)

DSCK (3)

CHINSb(5,14)

PP_ASTRb(17)

PP_RSTb(17)

PP_VFLSP0(17)

RUN(14)

EPP_CLK(17)

PP_BUSY_OUT(17)

RPORIb(3,11,14,17,18)

PP_AD[0:7](17)

DSDI (3)

PP_WEb(17)

SRESETb (3,17,18,24)

DSDO (3)

PP_DSTRb(17)

VFLS0(3,17)VFLS1(3,17)

HRESETb(3,11,17,18,24)

PP_VFLSP1(17)

BDM_DSDO (17)BDM_DSDI (17)BDM_DSCK (17)

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3V3U3

VCC

V3U3

V3U3

V3U3

V3U3

V3U3

VCC

C197

1nF

12

L26 FB1 2

L17 FB1 2

R101

1.00K

R1061.00K

C2250.1uF

C212

1nF

12

R102100

C235 0.1uF

L31 FB1 2

C2280.1uF

L22 FB1 2

D32HSMG-C650Green

U32AEPM3128AT

4157362

8790

88

4441

10

89

8

12

7

10099

98

97

96

94

93

9

22

5

2421

23

20

13

37

25

64

30

17

6

1

50

52

56

48

58

46

47

63

57

27

29

28

49

19

54

68

75

83

69

92

36

14

32

79

76

71

8581

84

80

777270

61

16

60

67

42

2

40

35

31

55

45

TDITMSTDOTCK

IN/GCLK1IN/OE2/GCLK2

IN/OE1

(C)GIO41(C)GIO39

(A)GIO14

IN/GCLR

(B)GIO16

(A)GIO13

(B)GIO17

(A)GIO3(A)GIO4

(A)GIO5

(A)GIO6

(A)GIO7

(A)GIO8

(A)GIO9

(B)GIO15

(C)GIO23

(B)GIO19

(C)GIO21(C)GIO24

(C)GIO22

(C)GIO25

(B)GIO12

(C)GIO29

(C)GIO20

(G)GIO57

(D)GIO34

(C)GIO27

(B)GIO18

(A)GIO2

(E)GIO47

(F)GIO48

(F)GIO51

(E)GIO45

(F)GIO53

(E)GIO43

(E)GIO44

(G)GIO56

(F)GIO52

(D)GIO37

(D)GIO35

(D)GIO36

(E)GIO46

(C)GIO26

(F)GIO49

(G)GIO59

(H)GIO64

(H)GIO70

(G)GIO60

(A)GIO10

(D)GIO30

(B)GIO11

(D)GIO32

(H)GIO67

(H)GIO65

(G)GIO62

(H)GIO72(H)GIO69

(H)GIO71

(H)GIO68

(H)GIO66(G)GIO63(G)GIO61

(F)GIO55

(C)GIO28

(F)GIO54

(G)GIO58

(E)GIO40

(A)GIO1

(E)GIO38

(D)GIO31

(D)GIO33

(F)GIO50

(E)GIO42

R941.00K

C207

1nF

12

U35B74CBTLV3257

16 8VCC GND

C216

1nF

12

C2330.1uF

DIP8

20 Mhz

J17

SOCKET for OSC

1234

8765

NCNCNC

GND

VCCNCNCOUT

L27 FB1 2

C204

1nF

12

C220

1nF

12

L18 FB1 2

C2260.1uF

C217

1nF

12

C200

1nF

12

C2290.1uF

C213

1nF

12

L23 FB1 2

U35A74CBTLV3257

2356

11101413

115

4

7

9

12

1B11B22B12B23B13B24B14B2

SOE

1A

2A

3A

4A

R103

0

L14 FB1 2

C199

1nF

12

C2340.1uF

RN38x10K

12346789

105

R96150

L28 FB1 2

C209

1nF

12

C201

1nF

12

C208

1nF

12

J21

2x5 Header0.1 CTR

1 23 45 67 89 10

C203

1nF

12

L19 FB1 2

R104

0

C221

1nF

12

C2300.1uF

C211

1nF

12

L24 FB1 2

R931.00K

L15 FB1 2

R9510.0K

C214

1nF

12

C2230.1uF

J18

DB25

1325122411231022

921

820

719

618

517

416

315

214

1

26

27

R97150

L29 FB1 2

C218

1nF

12

J191x2 Header0.1 CTR

1 2

L20 FB1 2

C198

1nF

12

R9810.0K

C2310.1uF

C202

1nF

12

C196 0.1uF

C222

1nF

12

L25 FB1 2

J16

2x5 Header0.1 CTR

1 23 45 67 89 10

C205

1nF

12

J201x2 Header0.1 CTR

1 2

L16 FB1 2

C210

1nF

12

R9910.0K

C2240.1uF

C206

1nF

12

D31HSMG-C650Green

L30 FB1 2

U33A74LVX161284

292827261925

4140383736353332

4746454443

202122233024

89

111213141617

148

23456

C14C15C16C17

PLHinHLHin

B1B2B3B4B5B6B7B8

Y9Y10Y11Y12Y13

A14A15A16A17PLHHLH

A1A2A3A4A5A6A7A8

HDDIR

A9A10A11A12A13

C2270.1uF

C215

1nF

12

L21 FB1 2

R100

1.00K

R1051.00K

C219

1nF

12

U33B

74LVX161284

718

3142

10153439

VCC1VCC2

VDD1VDD2

GNDGNDGNDGND U32B

EPM3128AT

3991

31834516682

3886

11263343535965747895

VCCINT1VCCINT2

VCCIO1VCCIO2VCCIO3VCCIO4VCCIO5VCCIO6

GNDINT1GNDINT2

GNDIO1GNDIO2GNDIO3GNDIO4GNDIO5GNDIO6GNDIO7GNDIO8GNDIO9

GNDIO10C2320.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1:2TDMA

output

1:1

T10W13T15

W10V14W15

PC5PA5PA9

PC4PA7PA8

This reset (RST_T1A) isactive on low-to-highedge. Normal state afterreset is low.

DUET ADSA

T1&E1


C




Title

Size DOCNumber:

Rev


MD3MD2

AD7

MD7

MD4

MD1

AD4AD5

MD0

AD0

MD6MD5

AD1AD2AD3

AD6

MD[0:7](8,11)

AD[0:7](7,8,11)

SW3_T1_L1RxDA(6)

SW3_T1_L1TSYNCA(6)

SW3_T1_L1TXDA(6)

SW3_T1_L1RSYNCA(6)

T1_L1TCLKA(5,17,18)

IRQ3B(3,7,8,17,18)

T1A_CS~(11)

WR_B(8,11)

RST_T1A (11)


V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

..

..

L33

PE-65854

1

2

3

4 5

6

7

8

C250

.01uF

C247

0.1uF

C2450.1uF

L35 3 pin FB1 3

2

C248

0.1uF

C236

0.1uF

+

C239 10uF 16V

C249

0.1uF

C251

.01uF

U36BDS2155L

1831

83816144

3024

19

84806045

20RVDDTVDD

DVDD4DVDD3DVDD2DVDD1

RVSS4RVSS3

RVSS1

DVSS4DVSS3DVSS2DVSS1

RVSS2

C242 .01uF

+ C24668uF20V

R109 470

C252

.01uF

L34 3 pin FB1 3

2

R11551.1

D33

MMBD914LT1

13

R11110.0K

C241 .01uF

R107 4.7

R11210.0K

R108 4.7

D34

MMBD914LT1

13

JP9Jumper .2TH

1 2

C2380.1uF

L363 pin FB

1 3

2

J22

RJ45Shielded

87654321

9

10

P8P7P6P5P4P3P2P1

GNDA

GNDB

C2440.1uF

U36ADS2155L

37

98

5657585962636465

6667686970717273

85

99

22

1

6

35

48

3839

50

47

4243

9091

8687

16

17

21

40

46

51

88

100

1112

14

52

55

7477

75

313

41

53

79

82

89

9225

29

32

3334

49

78

9394

95

9697

245

7

89

10

1523

365476

262728

TSYNC

RSYNC

D0/AD0D1/AD1D2/AD2D3/AD3D4/AD4D5/AD5D6/AD6D7/AD7

A0A1A2A3A4A5A6ALE(AS)/A7

RDATA

RLOS/LOTC

XTALD

RCHBLK

RCL

TLINK

TSIG

TPOSITNEGI

TDATA

TSER

TNEGOTPOSO

RNEGORPOSO

RPOSIRNEGI

RTIP

RRING

MCLK

TCLKI

TCLK

TSYSCLK

RCLKI

RSYSCLK

BTSLIUC

TSTRST

TSSYNC

MUX

RD/DSWR/R/W

CS

BPCLK8XCLK

TCLKO

TCHCLK

RLCLK

RCLK

RCLKO

RCHCLKINT

TTIP

TRING

TCHBLKTLCLK

TESO

RLINK

RSIGFRSIG

RSER

RMSYNCRFSYNC

JTMSJTCLKJTRST

JTDI

UOP0UOP1

JTDO

UOP2UOP3

ESIBS0ESIBS1ESIBRD

NCNCNC

U37

2.048MHz50PPM

123

4NCGNDOUT

VDD

R11451.1

.

.

.

.

.

.

.

T2

PE-65865

14 3

2

16 1

6

7

89

10

11

C237.47uFMPF100V10%

L32

3 pin FB13

2

R11310.0K

D36

MMBD914LT1

13

D35

MMBD914LT1

13

C2430.1uF

+

C240 10uF 16V

R110 470

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BDM SIGNALS

T11P19T5U12

DUET ADSA

Logic Analyzer


C




Title

Size DOCNumber:

Rev


D0D1D2D3D4D5D6D7D8

D10D11

D15

D9

D14

D12D13

D28

D17D18

D24

D16

D25

D21

D29

D26D27

D19D20

D30D31

D23D22

A31

A25

A14

A23

A5

A2

A20

A9

A0

A10

A30

A24

A22

A1

A19

A8

A17

A29

A18

A21

A13

A27

A7

A28

A4

A12

A15

A26

A6

A3

A16

A11

PA12

PC4

PC8PC7

PA6PA5

PA9

PA13

PA2

PC6

PA11

PA7

PC5

PA3

PC9

PA14

PA8

PC12

PC10PC11

PA4

PC14

PA1PA0

PC15

PA10

PC13

PA15

PB22

PB14 PB30

PD14

PD10

PD15

PB25PD11

PB29

PB19

PD7

PB18

PD9

PB15

PD6

PB31

PB26

PD3

PB23

PD4PB17

PD12

PB16

PB20PB21

PD5

PB24

PB28PD13 PB27

PD8

PE31

PE18

PE29

PE20PE19

PE27

PE14

PE17

PE23

PE15

PE26PE25

PE28

PE22

PE24

PE16

PE21

PE30

PP_AD[7:0]

PP_AD3

PP_AD6

PP_AD4

PP_AD1

PP_AD5

PP_AD2

PP_AD7

PP_AD0

MODCK1 (3,24)

A[0:31](2,3,4,24) D[0:31](2,3,4)

REGAb(3,10) TSIZ1 (3)

DRMCS1b (3,24)

TEAb (3,4)

WE0b (2,3,4,11)

WE2b (2,3,4)

FCSb (3,24)

WE3b (2,3,4)

BS3Ab (3)

CS5b (3,11,24)

BS0Ab (3,18)

BCSRCSb (3,24)

WE1b (2,3,4)GPL5Bb(3,18)

VF1(3)

BGb(3)

AT0(3)

BRb(3)

VF0(3)VF2(3)

AT3(3)

VFLS0(3,15)

BURST(3)

VFLS1(3,15)

BIb(3)

TSb(3,4,11)RWb(3,4,11,18)

BBb(3)

TAb(3,11,18,24)

AT2(3)

CS7b (3,18,24)CS6b (3,18,24)

BS1Ab (3)BS2Ab (3)

BCE1Ab(3,4,18,24)

BRESETA____ATM_RXCLK_SW 4(3,6,9,18)TEXP(3)


SRESETb(3,15,18,24)

IRQ2b (3,18)

HRESETb(3,11,15,18,24)

AT1(3)

ALEA (3,4)

MODCK1(3,24)

GPL4Ab(3,18)

POEAb(3,4)

EXTCLK(3)

RPORIb(3,11,14,15,18) SPKROUT (3,10)

WAITBb(3)

IRQ3b (3,7,8,16,18)

RSTCNFb(3,24)

MODCK2(3,24)

GPL4Bb(3,18)

T1_L1TXDA____ETHRXD_SW3 (5,6,18)

PC14(5,14,18)

USBRXN(5,6,18)

GPL5Ab(3,18)

GPL2b(2,3,4) R/MIIRXDV-1 (5,18,21)

PC8(5,14,18) T1_L1RXDA____ETHTXD_SW3 (5,6,18)

OE~(2,3,4,11)

R/MIIRXD0-1 (5,18,21)

ATM_RXCLAV(5,6,10,18)nUSBOE (5,18,23)

R/MIIRXD1-1 (5,18,21)

T1_L1RSYNCA____ETHCRS_SW3(5,6,18)T1_L1TCLKA (5,16,18)

USBTXP(5,18,23)

DRMWb(2,3,4)

CLK2 (5,18,23)

BCE2Ab (3,4,18,24)

USBTXN(5,18,23)

GPL3b(2,3,4)


R/MIITXD3-1(5,18,21)

R/MIITXD0-1 (5,18,21)

R/MIIRXERR-1 (5,18,21)

PC9(5,14,18)

IRDTXD (5,18,19)

R/MIITXERR-1 (5,18,21)

T1_L1RCLKA____ETHTXCK_SW3 (5,16,18)

IRDRXD (5,6,18)

USBRXD (5,6,18)

R/MIITXD2-1(5,18,21)USBRXP(5,6,18)

BSYSCLK4(19)

BRDY____ATM_RXD7_SW4 (3,6,18)BBVD2____ATM_RXD6_SW4 (3,6,18)

BCD1b____ATM_RXD4_SW4 (3,6,18)BBVD1____ATM_RXD5_SW4 (3,6,18)

BWP____ATM_RXD2_SW 4 (3,6,18)BCD2b____ATM_RXD3_SW4 (3,6,18)

BVS2____ATM_RXD1_SW4 (3,6,18)BVS1____ATM_RXD0_SW4 (3,6,18)

R/MIITXD1-1 (5,18,21)

SDRMCSb (2,3)DRMCS2b (3,24)

ATM_RXADDR0 (5,7,8,9,18)IRQ1b(3,18)

ATM_TXSOC(5,7,8,9,18)

ATM_TXADDR1 (5,7,8,9,18)

PB27 (5,18)

ATM_TXD5(5,7,8,9,18)

PB29 (5,14,18)

ATM_TXCLK(5,9,18)

ATM_TXD2(5,7,8,9,18)

R/MIIRXD3-1 (5,18,21)

IRQ7b (3,18)

ATM_TXADDR0 (5,7,8,9,18)

PB28 (5,14,18)

MPCMDC(5,18,20,21,22) ATM_TXADDR4 (5,7,8,9,18)

ATM_RXEN(5,7,8,9,18)

ATM_TXD7(5,7,8,9,18)

ATM_TXD3(5,7,8,9,18)

RSRXD1____ATM_TXADDR3_SW1 (5,6,18)

ATM_TXD6(5,7,8,9,18)

PB30 (5,18)

NMIb(3,18,24)

PB26 (5,18)

RSDTR1b____ATM_TXADDR2_SW1 (5,6,18)

R/MIITXCLK-1 (5,18,21)

ATM_TXD4(5,7,8,9,18)

RSTXD1____ATM_RXADDR3_SW1 (5,6,18)ATM_TXEN(5,7,8,9,18)

ATM_TXCLAV(5,6,18)

ATM_RXADDR1 (5,7,8,9,18)

ATM_TXD0(5,7,8,9,18)ATM_RXADDR2(5,7,8,9,18)

ATM_RXADDR4 (5,7,8,9,18)

ATM_TXD1(5,7,8,9,18)

BDM_DSCK(15)BDM_DSDI(15)

EPP_CLK(15)

BDM_DSDO (15)PP_DSTRb (15)

PP_WEb(15)

PP_RSTb (15)

PP_VFLSP0(15)

PP_ASTRb (15)

R/MIIRXCLK-1 (5,18,21)R/MIICRS-1 (3,21)MPCMDIO (3,18,20,21,22)R/MIITXEN-1 (3,21)R/MIICOL-1 (3,21)

CLK6(5,6,18)

R/MIITXD3-2(5,18,22)

R/MIIRXD0-2____RSRXD2_SW2(5,6,18)

R/MIITXEN-2(5,18,22)

CLK5(5,6,18)

R/MIITXD0-2(5,18,22)R/MIITXD1-2(5,18,22)

R/MIITXERR-2____RSTXD2_SW2(5,6,18)

R/MIIRXDV-2(5,18,22)R/MIIRXD3-2(5,18,22)

R/MIICOL-2(5,18,22)

R/MIIRXCLK-2____RSDTR2b_SW2(5,6,18)

R/MIICRS-2(5,18,22)

R/MIIRXERR-2____ETHTXEN_SW3(5,6,18)

R/MIIRXD2-1(5,18,21)

R/MIIRXD2-2(5,18,22)

R/MIIRXD1-2(5,18,22)

RPORIb(3,11,14,15,18)SRESETb(3,15,18,24)

VFLS1(3,15)VFLS0(3,15)

PP_VFLSP1(15)

PP_INTb(15)

FRZ(3,18)

PP_BUSY_OUT (15)

PP_AD[7:0](15)

HRESETb (3,11,15,18,24)

TP69TP72

TP55

TP71

TP56

TP64

TP73

TP57

TP68TP70

TP58

J30

2 x 19 Receptacle

MICTOR VERT

383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

J28

2 x 19 ReceptacleMICTOR VERT

383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

J26


383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

TP59

J25


383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

TP61

TP65TP67

TP63

TP60

TP66TP62

J23


383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

J27


383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

J24


383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

J29


383634

3735333129272523211917151311

9753

32302826

2220181614

1086421

24

3940414243

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FROM BCSR

CPMsignals

CPUsignals

CenterBottom Top

CenterBottom Top

DUET ADSA

Expansion Connectors


C




Title

Size DOCNumber:

Rev


PB27

PC11PC12

EXP_BD[0:7]

PC6

PB29

BA30

PB18

PC13

PB21

PC15

PB14

BA19

PB24

PC4

EXP_A[16:31]

PC7

PB20

PB26

PC9

PB15

PB30PB31

BA25

BA28

BA26

PB19

PB16

PC8

PC10

PB28

BA24

BA[16..31]

PB17

PB25

PB23

BA29

PC14

PC5

BA31

BA18

PB22

EXP_A25

EXP_A18

EXP_A16

EXP_A26

EXP_A19

EXP_A17

EXP_A27

EXP_A24

IPA5IPA6

IPA2IPA3

IPA0BWAITA

IPA1

IPA7

EXP_A24

EXP_A16

EXP_A18EXP_A17

EXP_A30

EXP_A27

EXP_A31

EXP_A21

EXP_A19

EXP_A22

EXP_A25

EXP_A23

EXP_A29EXP_A28

EXP_A20

EXP_A26

PA6

PD15

PA7

PD14

PD4

PA13

PA1

PD6

PA0

PD13

PA5

PA10

PA12

PD12

PA15

PA3

PD3

PA14

PA4

PD8

PA2

PD5

PA8PA9

PA11

PD7

PD9PD10PD11

PE14PE15PE16

PE18PE17

PE19

PE21PE20

PE22

PE24PE23

PE25

PE27PE26

PE28

PE30PE29

PE31

IPA4

EXP_A21EXP_A20

EXP_A22EXP_A23

EXP_A29EXP_A30

EXP_A28

EXP_A31

BA23

BA21BA22

BA16BA17

BA20

BA27

BD0

EXP_BD7EXP_BD6

BD2

EXP_BD3

BD[0..7]

EXP_BD3

EXP_BD0

EXP_BD2

EXP_BD5EXP_BD4

BD7

EXP_BD5

EXP_BD2EXP_BD1

BD6

BD4

EXP_BD0

BD5

BD1

EXP_BD1

EXP_BD7

EXP_BD4

EXP_BD6

BD3

EXP_DIR

EXP_OEb

ATM_TXCLAV(5,6,17)

PB27(5,17)

PC8(5,14,17)

RSRXD1____ATM_TXADDR3_SW1(5,6,17)

ATM_RXADDR0(5,7,8,9,17)

PC9(5,14,17)

RSTXD1____ATM_RXADDR3_SW1(5,6,17)

ATM_RXADDR1(5,7,8,9,17)

USBRXP(5,6,17)

PB26(5,17)

ATM_RXADDR4(5,7,8,9,17)

R/MIITXD2-1(5,17,21)

USBRXN(5,6,17)

BA[16..31](2,4,10,11,24)

PB28(5,14,17)

T1_L1RSYNCA____ETHCRS_SW3(5,6,17)

R/MIIRXD3-1(5,17,21)

R/MIITXD3-1(5,17,21)

BD[0..7](2,4,10,11,24)

PB29(5,14,17)


ATM_TXADDR0(5,7,8,9,17)

PC14(5,14,17)ATM_RXCLAV(5,6,10,17)

PB30(5,17)

USBTXN(5,17,23)

ATM_TXADDR1(5,7,8,9,17)

ATM_RXADDR2(5,7,8,9,17)


USBTXP(5,17,23)

ATM_TXADDR4(5,7,8,9,17)RSDTR1b____ATM_TXADDR2_SW1(5,6,17)

EXP_OEb(24)

GPL5Ab(3,17)

BDRMWb(4)

BS0Ab(3,17)


GPL4Bb(3,17)


BVS1____ATM_RXD0_SW4(3,6,17)

GPL4Ab(3,17)

TAb(3,11,17,24)

CS6b(3,17,24)


BEDOOEb(4)

BVS2____ATM_RXD1_SW4(3,6,17)

CS7b(3,17,24)

BRW2b(4,24)

BRDY____ATM_RXD7_SW4(3,6,17)

BTSb(4)

BWP____ATM_RXD2_SW 4(3,6,17)

BGPL2b(4)

GPL5Bb(3,17)



BWE0b(2,4,10)

BSYSCLK3(19)

BGPL3b(4)

USBRXD(5,6,17)

CLK2(5,17,23)

IRDTXD(5,17,19)

R/MIIRXERR-1(5,17,21)

T1_L1TCLKA(5,16,17)

R/MIIRXD0-1(5,17,21)

ATM_TXD0(5,7,8,9,17)ATM_TXD1(5,7,8,9,17)

R/MIIRXDV-1(5,17,21)

R/MIIRXD1-1(5,17,21)

IRDRXD(5,6,17)

R/MIITXD1-1(5,17,21)

ATM_TXD2(5,7,8,9,17)


nUSBOE(5,17,23)

ATM_TXSOC(5,7,8,9,17)ATM_TXD7(5,7,8,9,17)ATM_TXD6(5,7,8,9,17)ATM_TXD5(5,7,8,9,17)

R/MIITXERR-1(5,17,21)T1_L1TXDA____ETHRXD_SW3(5,6,17)

T1_L1RXDA____ETHTXD_SW3(5,6,17)

R/MIITXD0-1(5,17,21)

ATM_TXD4(5,7,8,9,17)

ATM_TXCLK(5,9,17)ATM_TXEN(5,7,8,9,17)ATM_RXEN(5,7,8,9,17)ATM_TXD3(5,7,8,9,17)

R/MIITXD0-2(5,17,22)R/MIITXD1-2(5,17,22)

CLK6(5,6,17)CLK5(5,6,17)

R/MIITXD3-2(5,17,22)R/MIITXEN-2(5,17,22)

R/MIITXERR-2____RSTXD2_SW2(5,6,17)R/MIIRXD0-2____RSRXD2_SW2(5,6,17)

R/MIIRXD1-2(5,17,22)R/MIIRXCLK-2____RSDTR2b_SW2(5,6,17)

R/MIIRXD2-2(5,17,22)R/MIIRXD3-2(5,17,22)R/MIIRXDV-2(5,17,22)

R/MIIRXERR-2____ETHTXEN_SW3(5,6,17)R/MIICOL-2(5,17,22)R/MIICRS-2(5,17,22)

R/MIIRXD2-1(5,17,21)R/MIIRXCLK-1(5,17,21)


IRQ7b(3,17)

IRQ2b(3,17)IRQ3b(3,7,8,16,17)

NMIb(3,17,24)

FRZ(3,17)

IRQ1b(3,17)

MPCMDIO(3,17,20,21,22)MPCMDC(5,17,20,21,22)

SRESETb(3,15,17,24)HRESETb(3,11,15,17,24)

BCE2Ab(3,4,17,24)BALEA(4,10)

BCE1Ab(3,4,17,24)

RPORIb(3,11,14,15,17)

SW_MODCK1(3,24)SW_MODCK2(24)

RWb(3,4,11,17)

MPCMDC(5,17,20,21,22)

V3U3

V3U3

V3U3

VCCVCC

VPPIN

V3U3

V3U3

J32B

3x32 Female Euro0.1 CTR

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32

C2600.1uF

U38B74LVCHR162245A

410152128343945

7183142


VCCVCCVCCVCC

C2530.1uF

U39A74LVCH162244

47464443

1

4140383748

36353332

25

3029272624

2356891112

1314161719202223

1A01A11A21A3

OE1

2A02A12A22A3OE2

3A03A13A23A3

OE3

4A04A14A24A3OE4

1Y01Y11Y21Y32Y02Y12Y22Y3

3Y03Y13Y23Y34Y04Y14Y24Y3

C2540.1uF

C2550.1uF

J31B


B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32

C2560.1uF

J32A


A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

J32C


C1C2C3C4C5C6C7C8C9

C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

D1D2

J31C


C1C2C3C4C5C6C7C8C9

C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

D1D2

R1161.00K

C2570.1uF

C2580.1uF

J31A


A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

U38A74LVCHR162245A

235689

1112

1314161719202223

4746444341403837

3635333230292726

1

24

48

25

1B11B21B31B41B51B61B71B8

2B12B22B32B42B52B62B72B8

1A11A21A31A41A51A61A71A8

2A12A22A32A42A52A62A72A8

DIR1

DIR2

OE1

OE2

U39B74LVCH162244

410152128343945

7183142


VCCVCCVCCVCC

C2590.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Clock Generator is the source

Capacitor-Resistor located in the end of the trace

162738495

NO LOAD

NO LOAD

NO LOAD

NO LOAD

NO LOAD

NO LOAD

IRDTXD

INFRA-RED PORT

IRDENb

NO LOAD

IRDRXD

NO LOAD

Place C284,C285 near U43

DUET ADSA

RS232, InfraRed, Sys CLK


C




Title

Size DOCNumber:

Rev


SYSCLK_CHIP_PWR

RSEN1b(14,24)

RSEN2b(14,24)

SW1_RSRXD1(6)SW1_RSDTR1b(6)

SW2_RSRXD2(6)SW2_RSDTR2b(6)

SYSCLK(3)

BSYSCLK2 (2)BSYSCLK3 (18)

CLK1 (24)

BSYSCLK4 (17)

BSYSCLK1 (11)

SW1_RSTXD1(6)

SW2_RSTXD2(6)

IRDENb(14,24)SW5_IRDRXD(6)

IRDTXD(5,17,18)

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

R128100

C2681nF1.5KV

12

L40 FB1 2

L47 3 pin FB1 3

2

C2761nF1.5KV

12

C287120pFC0G

RP18

4x22

1234 5

678

C2620.1uF

R1312.00K

RS-232 PHY

RS-

232

Lev

els

TT

LL

evel

s

U41MAX3241ECAI

28

25

24

1

2

27

3

26

141312

91011

2120

1918171615

23

45678

22

C1+

DGND

C1-

C2+

C2-

V+

V-

VCC

T1INT2INT3IN

T1OUTT2OUTT3OUT

R1OUTBR2OUTB

R1OUTR2OUTR3OUTR4OUTR5OUT

EN

R1INR2INR3INR4INR5IN

SHDN

R12347

C2691nF1.5KV

12

L41 FB1 2

+ C28110uF16V

U43

GP2W0004YP

234

5 1

6

TxDRxDSD/MODE V

CC

IN A

GND

C2750.1uF

C288120pFC0G

C2640.1uF

C2701nF1.5KV

12

C2820.1uF

RP19

4x22

1234 5

678

J33A

RS232 DB9

A5A9A4A8A3A7A2A6A1

A10

A11

R1242.00K

C2630.1uF

L43 FB1 2

C2710.1uF

C289120pFC0G

C2661nF1.5KV

12

C283.01uF

L44 FB1 2

U42ACY2309

231415

671011

16

9

1

8



CLKOUT

S1

REF

S2

R130

33.2

R12110.0K

L46 FB1 2

RS-232 PHY

RS-

232

Lev

els

TT

LL

evel

s

U40MAX3241ECAI

28

25

24

1

2

27

3

26

141312

91011

2120

1918171615

23

45678

22

C1+

DGND

C1-

C2+

C2-

V+

V-

VCC

T1INT2INT3IN

T1OUTT2OUTT3OUT

R1OUTBR2OUTB

R1OUTR2OUTR3OUTR4OUTR5OUT

EN

R1INR2INR3INR4INR5IN

SHDN

C2801nF1.5KV

12

C290120pFC0G

C286120pFC0G

C2671nF1.5KV

12

C2840.1uF

L42 FB1 2C2720.1uF

J33B

RS232 DB9

B5B9B4B8B3B7B2B6B1

B10

B11

R27610.0K

C2771nF1.5KV

12

L45 FB1 2

R125100

L37 FB1 2

R27510.0K

U42B

CY2309

4125

13 VDDGNDGND

VDD

C2740.1uF

C2650.1uF

C2781nF1.5KV

12

R126100

R11910.0K

C291120pFC0G

R12010.0K

L38 FB1 2

C2730.1uF

R127100

C2610.1uF

C2791nF1.5KV

12

R12210.0K

L39 FB1 2

R129100+ C285

4.7uF10V

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MPCMDC

Tx / Rx

ETHCOL

FDX

ETHRXCK

LINK

IRQ3b_IRQ7b

MIRRXD0

ETHTXEN

nETHRST

ETHTXD

MPCMDIO

ETHTXCK

ETHCRS

PHY ADDRESS TABLE

ARJ1

FAST ETHERNET1 - PHY ADDRESS 00010

RJ2RJ3RJ4RJ5BBBB

DUET ADSA

10BaseT ETHERNET GPSI


C




Title

Size DOCNumber:

Rev


ETHRXENNORMAL

ETHRXER

COL

PHY3AD2PHY3AD3

SCRM3

ISOLATE_TE3

PHY3AD1

PHY3AD4

PHY3AD0

MPCMDIO(3,17,18,21,22)

SW3_ETHTXEN(6)

MPCMDC(5,17,18,21,22)

GPSICLK(21)

nETHRST(24)

SW3_ETHTXD(6)

SW3_ETHRXD0(6)

IRQ3b_IRQ7b(3,21,22)

SW3_ETHTXCK(6)

SW3_ETHRXCK(6)

SW3_ETHCOL(6)SW3_ETHCRS(6)

ETHENb(14,24)

AVDTT1

A

A

A

V3U3

V3U3

A

AVDTT1 AVDTT1

A

A

V3U3

V3U3

V3U3

C3050.1uF

R154330

R14675

R13710.0K

R15710.0K

BA

RJ110K 1

2

3

+ C29810uF16V

C2950.1uF

R138 22

R153150

R15210K

D38

HSMY-C650Yellow

C3010.1uF

R150150

R139 22

L48

NFM60R1 3

2

R15110K

R14810K

C2920.1uF

R14375

J34

RJ45Shielded

87654321

9

10

P8P7P6P5P4P3P2P1

GNDA

GNDB

R1406.81K

C3000.1uF

R14475

** * * *

***

****

NC1NC2

T3TG22-3506

1

23 5

6

7

10

111214

15

16

89

R13349.9

+ C29710uF16V

BA

RJ510K 1

2

3

R14178.7

C3020.1uF

C3040.1uF

R1470

D37

HSMH-C650Red

C2940.1uF

R13249.9

R14910K

U44ADM9161

1617181920

2122

3826272829

373134

242532

143635

4010

45

4

3

8

7

48

47

111213

4243

TXER/TXD4TXD3TXD2TXD1TXD0

TXENTXCLK/ISOLATE

RXER/RXD4/RPTRRXD3/PHYAD3RXD2/PHYAD2RXD1/PHYAD1RXD0/PHYAD0

RXDV/TESTMODERXENRXCLK/SCRAMEN/10BTSER

MDCMDIOMDINTR

CABSTS/LINKSTSCOL/RMIICRS/PHYAD4

RESETPWRDWN

SD

RX-/FXRD-

RX+/FXRD+

TX-/FXTD-

TX+/FXTD+

BGRES

BGRESG

FDX/COL/OP0SPEED/OP1

LINK/ACT/OP2

XT2XT1

BA

RJ410K 1

2

3

R13410.0K

R15510.0K

R14575

C3030.1uF

R13510.0K

BA

RJ310K 1

2

3

C2930.1uF

R15610.0K

C2961000pF2KV20%

C2990.1uF

R14278.7

D39

HSMG-C650Green

R13610.0K

RP20 4x22

1234 5

678

U44BDM9161

153344

23303941

56

46

129

DGND1DGND2DGND3


AGNDRAGNDTAGNDS

AVDDR1AVDDR2

AVDDT

BA

RJ210K 1

2

3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MPCMDC

Tx / Rx

LINK

*

25MHz


** Only used during power up in RMII mode** No data transfer in RMII mode

*

100Mbps

R/MIICRS-1R/MIICOL-1

*R/MIITXD3-1

25MHz

**

R/MIITXEN-1

RSTR/MIIb-1

FDX

50MHz

**

*

*

R/MIIRXD2-1**

R/MIIRXERR-1

*

R/MIIRXD1-1


*

R/MIITXD0-1

R/MIITXD2-1R/MIITXD1-1

25MHz

R/MIIRXCLK-1

IRQ3

R/MIIRXD3-1

R/MIIRXENC-1

R/MIIRXDV-1

R/MIITXERR-1

R/MIIRXD0-1

MPCMDIO

50MHz

B

PHY ADDRESS TABLERJ10 RJ8 RJ7RJ9

BB BRJ6

B

RJ12

PHY CLOCK TABLE

B*

RJ11

B*

A A

CLK25MHZMII50MHZRMII

* = default

R/MIITXCLK-1

MII

RMII

DUET ADSA

FAST ETHERNET R/MII #1


C




Title

Size DOCNumber:

Rev


PHY1AD0-1

nMDINTR1 SCRM1

PHY1AD3-1RPTR1

PHY1AD2-1

MIICLK1

TESTMOD1

RMIICLK1

50MHZ_CLK_VDD

25MHZ_CLK_VDD

ISOLATE1

PHY1AD4-1

PHY1AD1-1

RMII1

RMIICLK2 (22)

MIICLK2 (22)

GPSICLK (20)

R/MIITXD3-1(5,17,18)

R/MIITXD0-1(5,17,18)R/MIITXD1-1(5,17,18)

R/MIITXERR-1(5,17,18)

R/MIICOL-1(3,17)

R/MIIRXD0-1(5,17,18)R/MIIRXDV-1(5,17,18)

R/MIICRS-1(3,17)

R/MIIRXD3-1(5,17,18)R/MIIRXERR-1(5,17,18)

R/MIIRXD2-1(5,17,18)R/MIIRXD1-1(5,17,18)

R/MIITXEN-1(3,17)

R/MIIRXCLK-1(5,17,18)

R/MIIRXENC-1(11,14)

MPCMDIO(3,17,18,20,22)

MPCMDC(5,17,18,20,22)


RSTR/MIIb-1(11)

R/MIITXD2-1(5,17,18)


R/MII-2(22)V3U3

A

V3U3

AVDTT2

V3U3

V3U3

A

V3U3

V3U3

V3U3

V3U3

A

AVDTT2

A

A

V3U3

A

AVDTT2

A

A

V3U3

V3U3

V3U3

V3U3

C3130.1uF

J35

RJ45Shielded

87654321

9

10

P8P7P6P5P4P3P2P1

GNDA

GNDB

C3200.1uF

R179330

B

ARJ12

Zero Ohm

13

2

U46E74LCX125

714 GNDVCC

BA

RJ610K 1

2

3

R17075

L51Ferrite Bead

640mA

1 2

R185

0

C3190.1uF

U46A

74LCX125

2 3

1

C3250.1uF

R1676.81K

C3170.1uF

U48

50.0MHz50PPM

123

4NC/EDGNDOUT

VDD

RP21 4x221234 5

678

R187

0

C3260.1uF

RP22 4x22

1234 5

678

C3231000pF2KV20%

U47A

74LCX125

2 3

1

C3160.1uF

R186

0

R15810K

BA

RJ710K 1

2

3

U46B

74LCX125

5 6

4

C3070.1uF

R18010K

C3150.1uF

R17510K

U49

25.0MHz50PPM

123

4NC/EDGNDOUT

VDD

R18110.0K

R16975

C3060.1uF

C3221000pF2KV20%

BA

RJ2410K 1

2

3

R188

0

C3140.1uF

R189 1.00K

C3080.1uF

R174150

U47B

74LCX125

56

4 R18210.0K

R190 1.00K

** * * *

***

****

NC1NC2

T4TG22-3506

1

23 5

6

7

10

111214

15

16

89R165

78.7

C3210.1uF

D43

HSMG-C650Green

R17175

U45ADM9161

1617181920

2122

3826272829

373134

242532

143635

4010

45

4

3

8

7

48

47

111213

4243


TXENTXCLK/ISOLATE



MDCMDIOMDINTR


RESETPWRDWN

SD

RX-/FXRD-

RX+/FXRD+

TX-/FXTD-

TX+/FXTD+

BGRES

BGRESG


LINK/ACT/OP2

XT2XT1

U46C

74LCX125

12 11

13

BA

RJ810K 1

2

3

R16149.9

L49

NFM60R1 3

2

JP10

Jumper .2TH1 2

R163

22

R18310.0K

R17710K

D41

HSMY-C650Yellow

R178150

R16010K

U27A

74AC14

1 2

+ C31110uF16V

C3270.1uF

C3180.1uF

C3101000pF2KV20%

R176150

R16249.9

R164

22 D42

HSMG-C650Green

+ C31210uF16V

U47D

74LCX125

9 810

D40

HSMH-C650Red

R1720

C3290.1uF

BA

RJ910K 1

2

3

R16678.7

U46D

74LCX125

9 8

10

L50Ferrite Bead

640mA

1 2

R17310K

U27F

74AC14

13 12

U47E74LCX125

714 GNDVCC

R15910K

R16875

B

ARJ11

Zero Ohm

13

2

R184

0

U45BDM9161

153344

23303941

56

46

129

DGND1DGND2DGND3


AGNDRAGNDTAGNDS

AVDDR1AVDDR2

AVDDT

C3240.1uF

C3090.1uF

C3280.1uF

BA

RJ1010K 1

2

3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

R/MIITXD3-2

R/MIICRS-2*

MPCMDIO

R/MIITXERR-2


*

IRQ3


** Only used during power up in RMII mode** No data transfer in RMII mode

R/MIICOL-2

Tx / Rx

RSTR/MIIb-2

R/MIIRXD0-2

100Mbps

*

*

R/MIIRXDV-2

R/MIIRXERR-2

R/MIITXD0-2

R/MIITXCLK-2R/MIITXEN-2

50MHz

**R/MIIRXD3-2

**

**

*

MPCMDC

R/MIIRXENC-2

FDX

R/MIIRXD1-2

*

25MHz

R/MIIRXD2-2

LINK

R/MIITXD1-2

*R/MIITXD2-2

R/MIIRXCLK-2

B

PHY ADDRESS TABLERJ19 RJ17 RJ16RJ18

BBB ARJ15

DUET ADSA

FAST ETHERNET R/MII #2


C




Title

Size DOCNumber:

Rev


LINK2

RMIICLK2

TESTMOD2

MIICLK2

nMDINTR2

RPTR2

ISOLATE2

PHY2AD3

SCRM2

PHY2AD2

PHY2AD0PHY2AD1

PHY1AD4-2RMII2

MPCMDIO(3,17,18,20,21)

SW3_R/MIITXD2-2(6)R/MIITXD1-2(5,17,18)

RMIICLK2(21)

SW2_R/MIITXERR-2(6)

MIICLK2(21)

R/MIITXD0-2(5,17,18)

R/MIITXD3-2(5,17,18)

MPCMDC(5,17,18,20,21)

R/MIITXEN-2(5,17,18)

R/MIIRXD2-2(5,17,18)

SW2_R/MIIRXCLK-2(6)

R/MIICRS-2(5,17,18)

SW3_R/MIIRXERR-2(6)

R/MIIRXD1-2(5,17,18)

R/MIICOL-2(5,17,18)

R/MIIRXD3-2(5,17,18)

SW3_R/MIITXCLK-2(6)

SW2_R/MIIRXD0-2(6)R/MIIRXDV-2(5,17,18)


R/MIIRXENC-2(11,14)

RSTR/MIIb-2(11)

R/MII-2(21)

RMIICLK2(21)

AVDTT3

V3U3 V3U3

V3U3

AVDTT3

A

AVDTT3

A

A

A

V3U3 A

V3U3

A

V3U3

V3U3

C3330.1uF

C3341000pF2KV20%

C3320.1uF

R20610K

BA

RJ1610K 1

2

3

D44

HSMH-C650Red

RP23 4x221234 5

678

BA

RJ1910K 1

2

3

R19878.7

R20175

R21210K

D45

HSMY-C650Yellow

R19210K

D47

HSMG-C650Green

R19549.9

BA

RJ1710K 1

2

3

C3370.1uF

R21010K

** * * *

***

****

NC1NC2

T5TG22-3506

1

23 5

6

7

10

111214

15

16

89

R21410.0K

+ C33510uF16V

R194

22

C3300.1uF

R20810K

BA

RJ1810K 1

2

3

R19978.7

RP24 4x22

1234 5

678

C3380.1uF

R197

22

R211150

R19649.9

BA

RJ1510K 1

2

3

U50ADM9161

1617181920

2122

3826272829

373134

242532

143635

4010

45

4

3

8

7

48

47

111213

4243


TXENTXCLK/ISOLATE



MDCMDIOMDINTR


RESETPWRDWN

SD

RX-/FXRD-

RX+/FXRD+

TX-/FXTD-

TX+/FXTD+

BGRES

BGRESG


LINK/ACT/OP2

XT2XT1

R2006.81K

R207150

D46

HSMG-C650Green

U50BDM9161

153344

23303941

56

46

129

DGND1DGND2DGND3


AGNDRAGNDTAGNDS

AVDDR1AVDDR2

AVDDT

BA

RJ2510K 1

2

3

U47C

74LCX125

1211

13

C3400.1uF

R216330

C3430.1uF

C3390.1uF

R20375

R21310.0K

J36

RJ45Shielded

87654321

9

10

P8P7P6P5P4P3P2P1

GNDA

GNDB

L52

NFM60R1 3

2

R209150

R20275

R19310K

C3410.1uF

R20475

R21510.0K

C3310.1uF

R2050

C3420.1uF

R19110K

+ C33610uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USBRXN

1.5A

USBRXP

USBRXD

nUSBLOWSPD

USBVCC

nUSBOE

USBTXNUSBTXP

nUSBHISPD

SPARES

USBCLK

Place C346near U52

nUSBLOWSPD

Place C345 near U51

nUSBEN

USBPOWER

GNDCHASSIS

GNDCHASSIS

GNDCHASSIS

DUET ADSA

USB


C




Title

Size DOCNumber:

Rev


D-D+nUSBOE(5,17,18)

nUSBLOWSPD(24)

USBTXN(5,17,18)

SW5_USBRXD(6)

nUSBEN(14,24)

SW5_USBRXP(6)

SW5_USBRXN(6)

nUSBFULLSPD(24)

CLK2(5,17,18)

USBVCC(24)

USBTXP(5,17,18)

VCC

V3U3

V3U3

V3U3

V3U3

V3U3

VCC

S2

D2

D2

G2

Q5-2

MMDF4N01HD

4

3 5

6

12

3 4

J38USB Series-B R/A

12 3 4

5 6

R224

24.3

S

D

G

Q6A

MMDF2P02HD2

71

8

R228

1.00K

S

D

G

Q4A

MMDF2P02HD2

71

8

C3450.1uF

R227

0

R226

10.0K

R2231.5K

R21710.0K

C3460.1uF

F3

SMD150/33

R26815K

3 421

J37

USB Series-A R/A

1 2 3 4

5 6

R26915K

+ C3444.7uF10V

12

G1

S1

D1

D1

Q5-1

MMDF4N01HD

2

1

8

7

R22010.0K

D48

HSMG-C650Green

U51

PDIUSBP11ADSO14

1

2

3

4

5

6

7

8

910

111213

14

MODE

OE

RCV

VP

VM

SUSPND

GND

NC

SPEEDD-

D+VPOVMO

VCC

R21910.0K

U52

25 ppm48 MHz

1 2

34

OE GND

OUTVcc

S

D

GQ6BMMDF2P02HD4

53

6

R2221.5K

R21810.0K

R225

24.3

R221332

S

D

G

Q4BMMDF2P02HD

4

53

6

Helen Converse

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TMSTCK

TDITDO

TRST

GNDNC

NCENABLE

VCC

S-RESET

ABORT

BOTH = HARD-RESET

MOD CK1

MOD CK2

DUET ADSA

BCSR


C




Title

Size DOCNumber:

Rev


FPD5

FPD2

BCSR3R0

BRW2b

A19

PCEENbBCSR3R0

BREV3

BCSR3R1 DRMPD1

PCCVCC1

DBREV0

DBID3

ISPTDO

A20

DBREV2

ETHENb

DBID3

SGLAMPb

SRESETb

LBUFENb

BCSR3R13

RSEN1b

DBID1

FCS2b

ISPINTDI

BCSRCSb

DRMPD1

A30

PCOENb

PCRWb

DBREV0

PCCENb

FPD7

NMIb

BA9

EXTOLI1

ISPTCK

BREV2

DRAMENb

BA28

BREV2

FPD6

FCS3b

ISPTMS

EXTOLI0

BREV0

RSTCNFb

BCSR3CSb

FCS1b

DBID0

BREV1

BREV1

RSEN2b

EXTOLI2

DRMPD2

BA29

DBID1

DRMPD3

DBID5

RPORI

BCE2Ab

DBID2

HRESETb

DBID2

PCCVPP0

BCE1Ab

BCSR3R1

FPD4

BCSR3R1

DBID4

IRDENb

BREV3

DBID5

DBREV1

DBID4

DBID3

PCVCC0

DRMCS2b

DRMPD4

MODCK1

DRVCNFb

FPD1

PCCVPP1

FCS4b

BCSR2R4

DBREV2

BTEAb

BREV0

DBID0

DBID4FPD3

FOEb

BCSR3R13

CLK1

DRMPD2

BREV2

DBREV1

UBUFENb

BCSR3R0

BA27

DBID2

BREV1

DBID0

FENb

FCSb

DBID5

BREV0

SDRAMEN

BCSR3R13

BCSR2R4

TAbDRMCS1b

EXTOLI3

FPD6

BA10

FPD7

DBID1

ISPINTDIISPTDO

ISPTCKISPTMS

MODCK2

BD9

BD8BD7BD6

BD0

BD14

BD2 FPD2

BD11

BD7

BD13

BD4

BD11

BD13

BD5BD4

FPD4

BD15

FPD1

BD13

BD9

BD2

BD12

FPD3

BD15

BD5

BD8

BD1

BD12

BD2

BD7

DRMPD1

FPD4

FPD3

BD3

BD11

BD1

FPD2

BD9

FPD1

BD0

BD15

BD6

BD1

BD3

BD12

BD4

BD14

BD8

BD10

BD3

BD0

BD6

BD5

BD10

BD10

BD14

EXTOLI0

EXTOLI3

EXTOLI0

EXTOLI1EXTOLI2

EXTOLI2EXTOLI1

DBREV1DBREV2

DBREV0EXTOLI3

BCSR2R4

DRMPD2

DRMPD4DRMPD3

FPD5

BREV3

HRESETb(3,11,15,17,18)

IRDENb (14,19)

A19(3,4,17)

nUSBFULLSPD (23)

USBVCC (23)

BA10(2,4,10)

A20(2,3,4,17)

CLK1(19)

nUSBEN (14,23)

BCSRCSb(3,17)

CS5b(3,11,17)

SGLAMPb (14)

RESERVED (14)

BA27(2,4,10,11,18)BA28(2,4,10,11,18)

LBUFENb (4)

NMIb(3,17,18)

TAb(3,11,17,18)

BTEAb(4)

BA29(2,4,10,11,18)

RSTCNFb (3,17)

RSEN1b (14,19)

SRESETb(3,15,17,18)

BCE2Ab(3,4,17,18)

PCVCC0 (13)

BRW2b(4,18)

FENb (14)

PCCVCC1 (13)

CS6b(3,17,18)

MODCK2 (3,17)

BA9(2,4,10)

RSEN2b (14,19)

RPORI(14)

PCOENb (10)

PCRWb (10)

PCCENb (10,11,14)

FCS1b (2)

PCCVPP1 (13)

FPD[1:4] (2)

FCS2b (2)

SDRAMEN (2,14)

PCCVPP0 (13)

nUSBLOWSPD (23)

ETHENb (14,20)

UBUFENb (4)

FCS3b (2)

DRMCS1b(3,17)

A30(3,4,17)

BD[0:31](2,4,10,11,18)

DRMCS2b(3,17)

PCEENb (10)

FCS4b (2)

CS7b(3,17,18)

MODCK1 (3,17)

FOEb (2)

FCSb(3,17)

BCE1Ab(3,4,17,18)

EXP_OEb (18)

nETHRST (20)

SW_MODCK1(3,18)SW_MODCK2(18)

FPD[1:7] (2)

V3U3 V3U3 V3U3 V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

V3U3

RN68x10K

12346789

105

C3650.1uF

U53AM4A3-192/96-6VC

26110

30100116112

3216

5104

189828

10222

46

7

89

1011

12

15

17

19

20

21

23

27

29

56

57

58

60

61

62

65

66

68

70

71

72

757677

78

31

3338

39

40

41

42

43

44

45

46

47

48

53

54

55

7980818285868789

91

92

93

9497

99105

118

119120

124

125126

127

128

129

130

132133

134

137

138140142

143

144

111

23435

107

4952

5967698890101

103113114115

117131

139141

121

74106

3

BD0BD1BD2BD3BD4BD5BD6BD7BD8BD9BD10BD11BD12BD13BD14

Rst1Rst0

DRMPD2

A30A20A19BA29

R_PORI

DRMPD1

NMI~

BA10

PCR_W

BA9

SReset~

Modck2

F_PD4

Ras2DD~

F_PD1

Ras2~

LBUFEn~

Ras1DD~

DRVCNF~

DRMA10

PccVcc1

RS_En2~

DramEn~

DRMA9

HReset~

ModemEn~USBSPD

DRMH_W~

PccVpp1

F_OE~

RSTCNF~UUFEN~

F_Cs2~

F_EN~

F_PD3

F_Cs1~

F_Cs3~

IRD_En~

F_Cs4~

F_Cs~

CE1A~

BCSRCs~

TA~

BR_W2

F_PD2

VDOEN~TPFLDL~

VDORST~SGLAMP~

PccEn~EthEn~

BCSREn~TPSQEL~

UsbVcc1

Ras1~

ModIn

DRMCs2~DRMCs1~

Bcsr3Cs~Bcsr2Cs~

CE2A~

Abr1Abr0

CLK1

BA27BA28

PCEEn~

nETHRST

UBUFEn~

PccVpp0

FCfgEn~PCOEn~

MDM_AUD~

Modck1

SdramEn~PcVcc0

VDOEXTCK

RS_En1~

UsbVcc0

BTEA~

TDITMSTCKTDO

SPARE_CLK0SPARE_CLK1

SPARE_0SPARE_1SPARE_2SPARE_3SPARE_4EXP_OEb

SPARE_6SPARE_7SPARE_8SPARE_9

SPARE_12SPARE_13

SPARE_10SPARE_11

SPARE_CLK2

NCNC0

BD15

TP29

S4

4 Position switch

5321

678

4

R23810.0K

C3630.1uF

C3490.1uF

TP28

TP44

TP48

R242 0

C3500.1uF

TP20

TP27

R23910.0K

TP43

TP46

C3480.1uF

C3590.1uF

R27210K

TP26

R253 0

C3560.1uF

TP42

RN78x10K

12346789

105

C3610.1uF

TP41

R24010.0K

U54B74LVCH162244

410152128343945

7183142


VCCVCCVCCVCC

RN48x10K

1234678910 5

TP40

R252 0

R241 0

TP39

TP54

R27310K

TP45

R256 0

R254 0

TP33

TP38

R294 0

R255 0

TP47

S7

2 Position switch

21

34

R244 0

R245 0

C3620.1uF

TP37

C3600.1uF

R249 0

TP36

TP52

U54A74LVCH162244

47464443

1

4140383748

36353332

25

3029272624

235689

1112

1314161719202223

1A01A11A21A3

OE1

2A02A12A22A3OE2

3A03A13A23A3

OE3

4A04A14A24A3OE4

1Y01Y11Y21Y32Y02Y12Y22Y3

3Y03Y13Y23Y34Y04Y14Y24Y3

TP35

TP50

U55B74LVCH162244

410152128343945

7183142


VCCVCCVCCVCC

TP51

C3640.1uF

C3510.1uF

C3670.1uF

TP34

TP49

R243 0

TP32

R250 0

C3550.1uF

S6PUSH SW BLACK

1

3

4

TP53

TP31

RN88x10K

12346789

105R251 0

C3580.1uF

R246 0

C3660.1uF

TP30

U53BM4A3-192/96-6VC

132551638396

1141082436375064738495136109123

122135

VCC_0VCC_1VCC_2VCC_3VCC_4VCC_5

GND_0GND_1GND_2GND_3GND_4GND_5GND_6GND_7GND_8GND_9

GND_10GND_11GND_12GND_13

VCC_6VCC_7

RN58x10K

12346789

105

S5PUSH SW RED

1

3

4

R247 0

C3470.1uF

R248 0

C3570.1uF

J39

2x5 Header0.1 CTR

1 23 45 67 89 10

R23710.0K

U55A74LVCH162244

47464443

1

4140383748

36353332

25

3029272624

235689

1112

1314161719202223

1A01A11A21A3

OE1

2A02A12A22A3OE2

3A03A13A23A3

OE3

4A04A14A24A3OE4

1Y01Y11Y21Y32Y02Y12Y22Y3

3Y03Y13Y23Y34Y04Y14Y24Y3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DUET ADSA

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C




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