mpc555pb, mpc555 - product brief - nxp semiconductors · mpc555 product brief 7 key features 3...

Product Brief

MPC555PB/DRev. 3, 2/2003

MPC555 Product Brief

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This document provides an overview of the MPC555 microcontroller, including a blockdiagram showing the major modular components and sections that list the major features. TheMPC555 member of the Freescale MPC500 RISC Microcontroller family.

1 IntroductionThe MPC555 device offers the following features:

• PowerPC™ core with floating-point unit

• 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM

• 448 Kbytes Flash EEPROM with 5-V programming

• 5-V I/O system

• Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B controller modules (TouCANTM)

• 50-channel timer system: dual time processor units (TPU3), modular I/O system (MIOS1)

• 32 analog inputs: dual queued analog-to-digital converters (QADC64)

• Submicron HCMOS (CDR1) technology

• 272-pin plastic ball grid array (PBGA) packaging

• 40-MHz operation, -40 °C to 125 °C with dual supply (3.3 V, 5 V) (-55 °C to 125 °C for the suffix A device)

• 32-bit architecture (PowerPC ISA architecture compliant)

• Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz

• Fully static, low power operation

• Integrated double-precision floating-point unit

• Precise exception model

Table 1. MPC555 Features

Device Flash Code Compression

MPC555 448 Kbytes Code compression not supported

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Block Diagram

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• Extensive system development support

— On-chip watchpoints and breakpoints

— Program flow tracking

— BDM on-chip emulation development interface

1.1 Block DiagramFigure 1 is a block diagram of the MPC555.

Figure 1. MPC555 Block Diagram

1.2 Key FeaturesThe MPC555 key features are explained in the following sections.

1.2.1 Four-Bank Memory Controller• Works with SRAM, EPROM, Flash EEPROM, and other peripherals

• Byte write enables

• 32-bit address decodes with bit masks

USIURCPU

BurstInterface

256 KbytesFlash

192 KbytesFlash

16 KbytesSRAM

10 KbytesSRAM

L2U

E-bus

UIMBQADC QADC QSMCM TouCAN

TPU3 DPTRAM TPU3 TouCAN MIOS1

L-bus

IMB3

U-bus

2 MPC555 Product Brief

For More Information On This Product, Go to: www.freescale.com

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1.2.2 U-Bus System Interface Unit (USIU)• Clock synthesizer

• Power management

• Reset controller

• MPC555 decrementer and time base

• Real-time clock register

• Periodic interrupt timer

• Hardware bus monitor and software watchdog timer

• Interrupt controller that supports up to eight external and eight internal interrupts

• IEEE 1149.1 JTAG test access port

• External bus interface

— 24 address pins, 32 data pins

— Supports multiple master designs

— Four-beat transfer bursts, two-clock minimum bus transactions

— Supports 5V inputs, provides 3.3-V outputs

1.2.3 Flexible Memory Protection Unit• Four instruction regions and four data regions

• 4-Kbyte to 16-Mbyte region size support

• Default attributes available in one global entry

• Attribute support for speculative accesses

1.2.4 448-Kbyte Flash EEPROM Memory• One 256-Kbyte and one 192-Kbyte module

• Page read mode

• Block (32-Kbyte) erasable

• External 4.75-V to 5.25-V program and erase power supply

1.2.5 26-Kbytes of Static RAM• One 16-Kbyte and one 10-Kbyte module

• Fast (one-clock) access

• Keep-alive power

• Soft defect detection (SDD)

1.2.6 General-Purpose I/O Support• Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode

• Nine general-purpose I/O pins in MIOS1 unit

• Many peripheral pins can be used for general-purpose I/O when not used for primary function

• 5-V tolerant inputs/outputs

MPC555 Product Brief 3


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1.2.7 Two Time Processor Units (TPU3)• Each TPU3 module provides these features:

— A dedicated micro-engine operates independently of the RCPU

— 16 independent programmable channels and pins

— Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare register and a 16-bit comparator

— Nine pre-programmed timer functions are available

— Any channel can perform any time function

— Each timer function can be assigned to more than one channel

— Two timer count registers with programmable prescalers

— Each channel can be synchronized to one or both counters

— Selectable channel priority levels

— 5-V tolerant inputs/outputs

• 6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for TPU microcode

1.2.8 18-Channel Modular I/O System (MIOS1)• Ten double action submodules (DASM)

• Eight dedicated PWM sub-modules (PWMSM)

• Two 16-bit modulus counter submodules (MCSM)

• Two parallel port I/O submodules (PIOSM)

• 5-V tolerant inputs/outputs

1.2.9 Two Queued Analog-to-Digital Converter Modules (QADC64)

Each QADC provides:

• Up to 16 analog input channels, using internal multiplexing

• Up to 41 total input channels, using internal and external multiplexing

• 10-bit A/D converter with internal sample/hold

• Typical conversion time of 10 µs (100,000 samples per second)

• Two conversion command queues of variable length

• Automated queue modes initiated by:

— External edge trigger/level gate

— Software command

• 64 result registers

• Output data that is right- or left-justified, signed or unsigned

• 5-V reference and range



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1.2.10 Two CAN 2.0B Controller Modules (TouCAN)Each TouCAN provides these features:

• Full implementation of CAN protocol specification, version 2.0A and 2.0B

• Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length

• Global mask register for message buffers 0 to 13

• Independent mask registers for message buffers 14 and 15

• Programmable transmit-first scheme: lowest ID or lowest buffer number

• 16-bit free-running timer for message time-stamping

• Low power sleep mode with programmable wake-up on bus activity

• Programmable I/O modes

• Maskable interrupts

• Independent of the transmission medium (external transceiver is assumed)

• Open network architecture

• Multimaster concept

• High immunity to EMI

• Short latency time for high-priority messages

• Low power sleep mode with programmable wakeup on bus activity

1.2.11 Queued Serial Multi-Channel Module (QSMCM)• Queued serial peripheral interface (QSPI)

— Provides full-duplex communication port for peripheral expansion or interprocessor communication

— Up to 32 preprogrammed transfers, reducing overhead

— 160-byte queue buffer

— Programmable transfer length: from 8 to 16 bits, inclusive

— Synchronous interface with baud rate of up to system clock divided by 4

— Four programmable peripheral-select pins support up to 16 devices

— Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals (e.g., – serial A/D converters, I/O latches, etc.)

• Two serial communications interfaces (SCI). Each SCI offers these features:

— UART mode provides NRZ format and half-or full-duplex interface

— 16 register receive buffer and 16 register transmit buffer (SCI1 only)

— Advanced error detection and optional parity generation and detection

— Word length programmable as 8 or 9 bits

— Separate transmitter and receiver enable bits and double buffering of data

— Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or a new address byte is received

— External source clock for baud generation

— Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs, allowing realization of a low-speed serial protocol



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2 MPC555 Address MapThe internal memory map is shown in Figure 2.

Figure 2. MPC555 Internal Memory Map

0x 30 7

0x 2F 0x 30 0000

U SI U & F l ash16 Kbytes

0x 38 0000

(10 Kbytes)

0x 3F

USIU Control Registers

FLASH Module A (64 b ytes)

FLASH Module B (64 b ytes)

Kbytes

0x 2F C0000x 2F

0x 30 8000

0x 37 FFFF

(480 Kbytes)

SR A M C on t r o l A( 8 bytes)

0x 3F 9800

(485.98 Kbytes)

0x 38 0010

Res erved for USIU

2F C880

1

BFFF

FFFF

FFF

FFFF

0x

0x2F C000

0x30 0000

0x30 7F80

0x30 7FFF

0x30 7080

0x30 7480

0x30 7884

DPTRAM (6 Kbytes)

QSMCM (4 Kbytes)

MIOS1 (4 Kbytes)

TouCAN_A (1 Kbyte)

TouCAN_B (1 Kbyte)

UIMB Registers(128 bytes)

TPU3_A (1 Kbyte)

TPU3_B (1 Kbyte)QADC_A (1 Kbyte)

QADC_B (1 Kbyte)

DPTRAM Control

Reserved (8180 bytes)

Reserved (2 Kbytes)

0x30 2000

0x30 4000

0x30 5000

0x30 6000

Reserved (1920 bytes)

(12 bytes)

IMB3 Address Space

0x2F C800

0x2F C840

UIMB Interface &

(32 Kbytes)IMB3 Modules

CMF Flash A

Reserved for Flash

Control

Reserved for IMB3

Reserved

SRAM A

256

0x07 0000

0x00 0000

0x06 FFFF

0x30 4400

0x30 4800

0x30 4C00

Kbyte

KbytesCMF Flash B192

SR A M C on t r o l B0x 38 0008

( 8 b ytes)

(16 Kbytes)SRAM B

0x04 0000

0x 3F C000

(2.6 Mbytes - 16 Kbytes)



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3 MPC555 Pinout DiagramFigure 3 shows the pinout for the MPC555.

Figure 3. MPC555 Pinout Diagram

MPC555 Ball Map

12

34

56

78

910

1112

1314

1516

1718

1920

AVD

DHA_

TPUC

H1A_

TPU

CH4

A_TP

UCH8

A_TP

UCH

12A_

TPUC

H15

VRL

AAN

0_PQ

B0AA

N48_

PQB4

AAN5

2_PQ

A0AA

N54_

PQA2

BAN0

_PQ

B0BA

N2_

PQB2

BAN3

_PQ

B3BA

N51_

PQB7

VDD

HM

DA11

MDA

12M

DA13

VDDH

BB_

T2CL

KVD

DH

A_TP

UCH

6A_

TPUC

H10

A_TP

UCH

11A_

TPUC

H14

VRH

AAN

3_PQ

B3AA

N49_

PQB5

AAN5

3_PQ

A1AA

N57_

PQA5

BAN1

_PQ

B1BA

N48_

PQB4

BAN5

2_PQ

A0BA

N54_

PQA2

ETRI

G2

MDA

14M

DA15

VDDH

MDA

28

CB_

TPUC

H15

A_T2

CLK

A_TP

UCH

3A_

TPUC

H7A_

TPUC

H9A_

TPUC

H13

VDDA

AAN

2_PQ

B2AA

N51_

PQB7

AAN5

6_PQ

A4AA

N59_

PQA7

BAN4

9_PQ

B5BA

N53_

PQA1

BAN5

6_PQ

A4BA

N57_

PQA5

ETRI

G1

MDA

27M

DA29

MDA

30M

DA31

DB_

TPUC

H11

B_TP

UCH

13A_

TPUC

H0A_

TPUC

H2A_

TPUC

H5VD

DI

VSSA

AAN

1_PQ

B1AA

N50_

PQB6

AAN5

5_PQ

A3AA

N58_

PQA6

BAN5

0_PQ

B6BA

N55_

PQA3

BAN5

8_PQ

A6BA

N59_

PQA7

VDDI

VDDL

MPW

M1

MPW

M2

MPW

M3

EB_

TPU

CH7

B_TP

UCH

10B_

TPUC

H14

VDDL

MPW

M0

MPW

M17

MPW

M19

MPI

O6

FB_

TPU

CH5

B_TP

UCH6

B_TP

UCH8

B_TP

UCH1

2M

PWM

16M

PWM

18M

PIO

7M

PIO

9

GB_

TPU

CH2

B_TP

UCH3

B_TP

UCH4

B_TP

UCH9

MPI

O5

MPI

O8

MPI

O11

MPI

O12

HB_

TPU

CH1

B_TP

UCH0

B_CN

RX0

B_CN

TX0

MPI

O10

MPI

O15

MPI

O14

MPI

O13

JTC

K_ D

SCK

TDO

_D S

DO

TRST

_BVD

D S

RAM

VSS

VSS

VSS

VSS

VF2

_MPI

O2

VFLS

0_M

PIO

3VF

0 _M

PIO

0VF

1 _M

PIO

1

KTM

STD

I_DS

DI

SGP_

FRZ

VDDL

VSS

VSS

VSS

VSS

VDDL

VFLS

1_M

PIO

4A_

CNTX

0A_

CNR

X0

LIW

P1 _

VFLS

IWP0

_VF

LSIR

Q3B

_SG

PIR

Q4B

_SG

PVS

SVS

SVS

SVS

SPC

S1_Q

GP

PCS0

_QG

PM

ISO

_Q

GP4

MO

SI _

QG

P5

MIR

Q0B

_SG

PIR

Q1B

_SG

PIR

Q2B

_ SG

PSG

P_

IRQ

OUT

BVS

SVS

SVS

SVS

SPC

S3_Q

GP

PCS2

_QG

PEC

KSC

K_ Q

GP6

NW

EB_

AT[0

]BR

B_IW

P2BG

B_LW

P1BB

B _I

WP3

Note

: The

pin

out i

s a

top

dow

n vi

ew o

f the

pac

kage

.RX

D1_

QG

PITX

D1_

QG

PORX

D2_

QG

PITX

D2_

QG

PO

PW

EB_

AT[1

]W

EB_

AT[2

]W

EB_

AT[3

]C

S0B

VPP

EPEE

VSSF

VDDH

RRD

_WRB

CS3

BCS

2BC

S 1B

VDDL

VDDF

XFC

VDDS

YN

TO

EBTE

ABTS

IZ1

VDDL

VDDI

KAPW

RVS

SSYN

EXTA

L

UTS

IZ0

TAB

TSB

BDIP

BV D

DIAd

dr_

SGP3

1Ad

dr_

SGP3

0Ad

dr_

SGP2

8Ad

dr_

SGP2

9VD

DLDa

ta_

SGP2

9Da

ta_

SGP2

7Da

ta_

SGP2

5Da

ta_

SGP2

3VD

DLDa

ta_

SGP2

0RC

FB_T

XPEX

TCLK

ECK_

BUC

KXT

AL

VBU

RSTB

BIB_

STSB

Addr

_ SG

P11

Addr

_ SG

P10

Addr

_ SG

P9Ad

dr_

SGP8

Addr

_ SG

P22

Addr

_ SG

P27

Data

_ SG

P31

Data

_ SG

P30

Data

_ SG

P28

D ata

_ SG

P26

Data

_ SG

P24

Data

_ SG

P22

Data

_ SG

P21

Data

_ SG

P19

Data

_ SG

P18

CLKO

UTPO

RESE

TBSR

ESET

B

WAd

dr_

SGP1

2VD

DH

A ddr

_ SG

P14

Addr

_ SG

P16

Addr

_ SG

P18

Addr

_ SG

P20

Addr

_ SG

P23

Addr

_ SG

P26

Data

_ SG

P1Da

ta_

SGP3

Data

_ SG

P5Da

ta_

SGP7

Data

_ SG

P9Da

ta_

SGP1

1Da

ta_

SGP1

3Da

ta_

SGP1

5Da

ta_

SGP1

7IR

Q5B

_SG

PVD

DHHR

ESET

B

YVD

DHAd

dr_

SGP1

3Ad

dr_

SGP1

5Ad

dr_

SGP1

7Ad

dr_

SGP1

9Ad

dr_

SGP2

1Ad

dr_

SGP 2

4Ad

dr_

SGP2

5Da

ta_

SGP0

Data

_ SG

P2Da

ta_

SGP4

Data

_ SG

P6Da

ta_

SGP8

Data

_ SG

P10

Data

_ SG

P12

Data

_ SG

P14

Data

_ SG

P16

IRQ

6B _

mck

2IR

Q7B

_m

ck3

VDDH

VDDH

=3 volt power (I/O)

VDDi

=3 volt power (internal)

VSS

=ground

VDDH

=5 volt power

=Misc power

y Dees Substrate 9/30/97a

21 November 1997

Version 10.2



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4 Supporting Documentation ListThis list contains references to currently available and planned documentation.

• MPC555 User’s Manual (MPC555UM/AD)

• RCPU Reference Manual (RCPURM/AD)

• Board Strategies for Ensuring Optimum Frequency Synthesizer Performance (AN1282/D)

• Using the MIOS on the MPC555 Evaluation Board (AN1778/D)

• Exception Table Relocation and Multi-Processor Address Mapping in the Embedded MPC5XX Family (AN1821/D)

• Non-Volatile Memory Technology Overview (AN1837/D)

• Designing Expansion Boards for the Freescale EVB555/ETAS ES200 (AN2001/D)

• MPC555 Interrupts (AN2109/D)

• EMC Guidelines for MPC500-Based Automotive Powertrain Systems (AN2127/D)

• Nexus Standard Specification (non-Freescale document)

• Nexus Web Site: http://www.nexus5001.org/

• IEEE 1149.1 Specification (non-Freescale document)

5 Revision History

Table 2. Revision History

Revision Number Substantive Changes Date of Release

2 Existing Document. September 2001

2.1 Added temperature range for suffix A device. 11 December 2002

3 Updated template and formats. 11 February 2003



http://www.nexus5001.org/

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MPC555PB/D

For More Information On This Product,

Go to: www.freescale.com

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