mmcm vivado example verilog - worcester polytechnic …users.wpi.edu/~rjduck/mmcm vivado example...

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ECE3829/574 Using MMCMs Jim Duckworth, September 2015 1 This tutorial shows how to create a simple project with a MMCM (Mixed-Mode Clock Manager) using Xilinx Vivado Design Suite. (Verilog Example) In this example we instantiate an MMCM to generate a 10MHz clock from the 100MHz oscillator connected to the FPGA. Create a new project and verify the Tools => Project Settings => General => Target Language is set to Verilog. Create a simple module with the following ports and counter logic: Select the IP Catalog in the Project Manager and select the clocking wizard:

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Page 1: MMCM Vivado example Verilog - Worcester Polytechnic …users.wpi.edu/~rjduck/MMCM Vivado example Verilog.pdf · · 2015-09-05Microsoft Word - MMCM Vivado example Verilog.docx Author:

ECE3829/574 Using MMCMs

Jim Duckworth, September 2015 1

This tutorial shows how to create a simple project with a MMCM (Mixed-Mode Clock Manager) using

Xilinx Vivado Design Suite. (Verilog Example)

In this example we instantiate an MMCM to generate a 10MHz clock from the 100MHz oscillator

connected to the FPGA.

Create a new project and verify the Tools => Project Settings => General => Target Language is set to

Verilog.

Create a simple module with the following ports and counter logic:

Select the IP Catalog in the Project Manager and select the clocking wizard:

Page 2: MMCM Vivado example Verilog - Worcester Polytechnic …users.wpi.edu/~rjduck/MMCM Vivado example Verilog.pdf · · 2015-09-05Microsoft Word - MMCM Vivado example Verilog.docx Author:

ECE3829/574 Using MMCMs

Jim Duckworth, September 2015 2

The Clocking Wizard - Customize IP window opens:

Page 3: MMCM Vivado example Verilog - Worcester Polytechnic …users.wpi.edu/~rjduck/MMCM Vivado example Verilog.pdf · · 2015-09-05Microsoft Word - MMCM Vivado example Verilog.docx Author:

ECE3829/574 Using MMCMs

Jim Duckworth, September 2015 3

In the Output Clocks tab select 10MHz for the clk_out1 frequency:

In the Port Renaming tab, change the port name to clk_10M:

Page 4: MMCM Vivado example Verilog - Worcester Polytechnic …users.wpi.edu/~rjduck/MMCM Vivado example Verilog.pdf · · 2015-09-05Microsoft Word - MMCM Vivado example Verilog.docx Author:

ECE3829/574 Using MMCMs

Jim Duckworth, September 2015 4

Click OK

Click on Generate.

The MMCM is now added to the available design sources:

Page 5: MMCM Vivado example Verilog - Worcester Polytechnic …users.wpi.edu/~rjduck/MMCM Vivado example Verilog.pdf · · 2015-09-05Microsoft Word - MMCM Vivado example Verilog.docx Author:

ECE3829/574 Using MMCMs

Jim Duckworth, September 2015 5

We now need to add the MMCM to our top level design.

In the Sources window, Select IP Sources and then expand the Instantiation Template to see the

clk_wix_veo file:

Page 6: MMCM Vivado example Verilog - Worcester Polytechnic …users.wpi.edu/~rjduck/MMCM Vivado example Verilog.pdf · · 2015-09-05Microsoft Word - MMCM Vivado example Verilog.docx Author:

ECE3829/574 Using MMCMs

Jim Duckworth, September 2015 6

Select the lines at the bottom of the file for the instantiation template (select the lines and use ctrl C to

copy):

Back in your top level file, paste the instantiation template and modify the signal names to match your

connections:

You can now synthesize and implement this design.

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