a generation ahead · vivado –mode tcl; launches vivado in command line mode. vivado –mode...

© Copyright 2012 Xilinx

TCL, the Tool Control Language, and Vivado

A GENERATION AHEADSEMINAR SERIES

© Copyright 2012 XilinxPage 2

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Expectations

Controlling Vivado with TCL

Vivado Physical Constraints

Vivado Timing Constraints

More Information

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Agenda


I. Expectations

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There is NO WAY I can teach you the entire TCL language and how to use it with Vivado in 43 minutes

It is absolutely possible to expose you to enough TCL in 42 minutes such that you’ll get it– And this will be done in the context of using Vivado

For now don’t think of TCL as a language. Think of it as a bunch of similarly structured commands.– As you write more powerful scripts, and you find that you need more

power and flexibility in your scripts, TCL enables that

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Expectations for the Next 44 Minutes

Homework: Get a TCL book, explore TCL on the WEB, play in Vivado


II. Controlling Vivado with TCL

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SDC - Synopsys Design Constraints– Timing Constraints

XDC - Xilinx Design Constraints– Physical Constraints

Vivado Tcl– SDC + XDC– Xilinx commands

• Project management, synthesize, place and route, compilation, report,…

– Xilinx objects• Netlist, device, timing, project,…

– General Tcl (8.5)• List-related commands are overloaded to support primary

objects• Primary objects can directly be used with general

commands

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Vivado Tcl

Vivado Tcl“Executables” / Commands

XDCPhysical

SDCTiming

Things that used to go in a UCF are now TCL commands and

are now included in a .xdcconstraints file

Things that used to be separate executables in ISE are now TCL commands and can be included in a .tcl batch file

Include in .xdc file


• -- mode tcl:– Vivado is running, no GUI– start_GUI TCL

command will launch the GUI without forgetting what you’ve done

• -- mode batch– Same as –mode tcl, but

executes a tcl script on start-up

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Launching Vivado From the ISE Command Prompt

Launches Xilinx Command Prompt

Vivado Launches GUI

vivado –mode tcl Launches Vivado in command line mode

vivado –mode batch –source

Launches Vivado in command line, executes filename.tcl

Then type


A Vivado “Batch Mode” TCL Script Might Look Something Like this

read_verilog

read_vhdl

read_edif

synth_design

report_timing_summary

write_checkpoint

opt_design

place_design


write_checkpoint

route_design


write_checkpoint

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You can still load the design into PlanAhead GUI for Design Analysis

Commands Used to Synthesize / Implement Design

start_gui

read_checkpoint


ISE Command Line Equivalence in Vivado

ISE Command Line Tool Vivado Equivalent TCL Commandsxst synth_designNgdbuild (Translate) link_design

(Not required if running synth_design)map opt_design

power_opt_design (optional)phys_opt_design (optional)

par place_designroute_design

trce report_timingbitgen write_bitstream

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Design runs use specific source sets– Design Sources– Constraints Sets– Simulation Sets

Uses the concept of design runs– launch_run

(synthesis / implementation)

– wait_on_run

– open_run (synthesis / implementation)

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A Separate “Project Flow” Uses DIFFERENT TCL Commands

Vivado IDE for Project Management

Commands Used to Accomplish Same Thing

create_project …

add_files …

import_files …

…

launch_run synth_1

wait_on_run …

open_run …


launch_runs impl_1

wait_on_run …

open_run …

Confused?


EXAMPLEget_ports returns all top level IO ports of the design

get_pins returns all pins in design

Pins and Ports May Not Be What you Expect

Ports are the pads or balls of the FPGA. Literally. – You apply things like LOC and IOSTANDARD to ports

There’s also CELLs and PINS– The I/O of an instantiated module or primitive is the PIN of a CELL

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top

module

PinsPins

Ports Ports

primitive

Cells


III Vivado Physical Constraints

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Finding Netlist Objects in the Design

Command Descriptionget_cells Cell objects based on name/hierarchy or connectivityget_pins Pin objects based name/hierarchy or connectivityget_nets Net objects by name/hierarchy or connectivityget_ports Top-level netlist ports by name or connectivityget_iobanks IO Bank objects, needed for constraining

all_inputs Get a list of all input ports in the current designall_outputs Get a list of all output ports in the current designall_ffs Get a list of all flip flops in current designall_latches Get a list of all latches in current designall_dsps Get a list of dsp cells in the current designall_rams Get a list of ram cells in the current design

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To create constraints or analyze designs, you need to access netlist objects


Utilization– get_cells :returns list of all cells in the design on one line– join [get_cells] "\n“ : return list of all cells in the design, but on separate lines– llength [get_cells [all_dsps]] : How many are DSPs are in the desgin

OR

report_utilization– Just a bunch of stuff scrolling by

report_utilization –file my_util.txt– Creates a file, sticks it . . . somewhere

Click the GUI button that says Report Utilization.– Gives you a great table– But you didn’t learn as much TCL

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Simple Example 1: Utilization


Simple Example #2: Find Netlist Objects

Use the Find (Ctrl-F) function in the Vivado GUI to find objects in the netlist:– Choose Instances to search for Cells

Use the Search Results with “get_cells”. You can then apply a “property”

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place_cell [get_cells Inst_mac_logic/Inst_mac_25x18/p_accum_reg] DSP48_X0Y24

Search Results


set_property PACKAGE_PIN A25 [get_ports COUNT_OUT_OSERDES_N]

set_property IOSTANDARD LVDS_25 [get_ports COUNT_OUT_OSERDES_N]

set_property IOSTANDARD LVCMOS18 [get_ports MAC_OUT[*]]

set_property DRIVE 12 [get_ports MAC_OUT[*]]

set_property SLEW SLOW [get_ports MAC_OUT[*]]

get_property PACKAGE_PIN [get_port MAC_OUT[47]]

get_property SLEW [get_port MAC_OUT[47]]

get_property DRIVE [get_port MAC_OUT[47]]

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Simple Example #3: Checking Your Work

Check your work!


You’ve set Location Constraints on all of your I/O– llength [get_ports]: Returns number of I/O in your design– llength [get_property PACKAGE_PIN [get_ports]]

– Should return the same number

Of course the tools will tell you this too after you place_design

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Simple Example #4: More Sanity Checking


In ISE, PROBEs allows you to tap off of a net, connecting it to an unused I/O. How would you do the same thing in Vivado TCL?

1. Create a port2. Select an I/O Standard3. Select an unused pin location4. Connect the net from the design to the port created in 1.

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Master Class: PROBES (1)


Master Class: PROBES (2)

proc addProbe {signal pin IOStandard name} {create_port -direction OUT $nameset_property IOSTANDARD $IOStandard [get_port $name]set_property LOC $pin [get_port $name]connect_net -net $signal -objects [get_port $name]}

Save this file as probes.tclAfter design is loaded, type “source probes.tcl” at the TCL promptType “addProbe mem_en V25 LVCMOS18 Fred” at the TCL prompt

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“FIND” the net Pick a pin

FredPick whatever

works


IV. Vivado Timing Constraints

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Create clocks and define clock interactions

– Four-step guideline

Set input and output delays

– Beware of not creating wrong HOLD violations

Set timing exceptions

– Less is more!

– Beware of not creating wrong HOLD violations

Use report commands to validate each step

Vivado Timing Constraints Best Practices

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For SDC-based timers, clocks only exist if you create them– Use create_clock for primary clocks

“Generated” Clocks are created automatically through clocking modules– MMCM and PLL output clocks are automatically generated– Gigabit transceivers are not supported. Create them manually.

Use create_generated_clock for internal clocks (if needed)All inter-clock paths are evaluated by default

Clock Ground Rules

don’t create_clock here

create_clockhere

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Step 1– Use create_clock for all primary clocks on top level ports– Run the design (synthesis) or open netlist design

Step 2– Run report_clocks– Study the report to verify period, phase and propagation– Apply corrections to your constraints (if needed)

Four Steps for Creating Clocks

AttributesP: PropagatedG: Generated

Clock Period Waveform Attributes Sourcessys_clk 10.000 {0.000 5.000} P {sys_clk}pll0/clkfbout 10.000 {0.000 5.000} P,G {pll0/plle2_adv_inst/CLKFBOUT}pll0/clkout0 2.500 {0.000 1.250} P,G {pll0/plle2_adv_inst/CLKOUT0}pll0/clkout1 10.000 {0.000 5.000} P,G {pll0/plle2_adv_inst/CLKOUT1}

Output of report_clocks (excerpt)

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Step 3– Evaluate the clock interaction using report_clock_interaction

– Unconstrain inter-clock paths (Clock Domain Crossing) as needed• Make sure you designed proper CDC synchronizers

• Use set_clock_groups (preferred method to set_false_path)

– Do you have unconstrained objects? • Find out with check_timing

Step 4– Run report_clock_networks– You want the design to have clean clock lines without logic

• Tip: Use clock gating option in synthesis to remove LUTs on the clock line

Four Steps for Creating Clocks (continued)

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Clock Creation Example

# SDC create_clock for the two primary clockscreate_clock ‐name clk_oxo ‐period 10 [get_ports clk_oxo]create_clock ‐name clk_core ‐period 10 [get_ports clk_core]

# Set Asynchronous Clock Groups set_clock_groups ‐asynchronous ‐group [get_clocks –include_generated_clocks clk_oxo] \‐group [get_clocks –include_generated_clocks clk_core} ]

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Order Doesn’t Matter


Start with no IO constraints

– Focus on finding and fixing core timing issues

Specify realistic IO delays

– Use set_input_delay and set_output_delay

– Wrong delay value (e.g. 0 ns) can cause wrong HOLD violations

Setting Input / Output Delays

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set_input_delay: Used to specify a min setup Requirement at the FPGA Inputs.

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Reference point is launch clock of external data source to FPGA (opposite of Offset In)

Input delay value typically includes the clock to out of the external source plus the trace delay

UCF: OFFSET = IN 6ns BEFORE ClkIn;

XDC: create_clock –name clk_in –period 10 [get_ports ClkIn]set_input_delay 4 –clock clk_in [get_ports DataIn]


set_Output_Delay: Used to specify a clock to output requirement at the FPGA outputs.

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UCF: OFFSET = OUT 4ns AFTER Clk;

XDC: create_clock –name clk –period 10 [get_ports Clk]set_output_delay 6 –clock clk [get_ports Dout]

Reference point is clock of edge at external target (opposite of Offset In)

Output delay value typically includes the setup requirement of the external target plus the trace delay


set_multicycle_path N implies a HOLD check at N-1– E.g.: a multicycle_path of 10 implies a HOLD requirement of 9 cycles!

Guidelines to avoid hurting runtime and SETUP– Add proper circuitry (e.g. clock enable logic)– Reduce the HOLD requirement by N-1 (back to 0) to avoid wrong HOLD violations

Multicycle Paths—Understand the Tools

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holdsetup

Launch

set_multicycle_path –from [get_cells regB] –to [get_cells regC] 2 setup:2, hold:1set_multicycle_path –from [get_cells regB] –to [get_cells regC] 1 –hold setup:2, hold:0

P&R fixes HOLD violations as #1 priority, becauseDesigns with HOLD violations simply won’t work on HWDesigns with SETUP violations will work, but only if you slow your clock down


TCL Timing Command Summary

Create and validate clocks– check_timing: for missing clocks and IO constraints– report_clocks: check frequency and phase– report_clock_networks: possible clock root

Validate clock groups– report_clock_interaction

Validate I/O delays– report_timing –from [input_port] –setup/-hold– report_timing –to [output_port] –setup/-hold

Add exceptions if necessary– Validate using report_timing

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Output of report_timing_summary

– Intra-clock report– Inter-clock report

No RED is same thing as Timing Score = 0

RED? That’s where the fun starts!

Timing Closure?

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report_timing_summary -delay_type min_max -path_type full_clock_expanded -report_unconstrained -check_timing_verbose -max_paths 10 -nworst 1 -significant_digits 3 -input_pins -name timing_1


V. For More Information

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There is No Shortage of Information on TCL

Vivado Design Suite Tcl Command Reference Guide (Xilinx.com)

Vivado Design Suite Properties Reference Guide (Xilinx.com)

The GUI – help returns a number of categories, help –[category] returns additional detail– [command] –help returns detail on the command

Xilinx Tcl Cheat Sheet

Tcl and the TK Toolkit (John K. Ousterhout, Amazon.com)

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Slide Number 1Slide Number 2AgendaI. ExpectationsExpectations for the Next 44 MinutesII. Controlling Vivado with TCLVivado TclLaunching Vivado From the ISE Command PromptA Vivado “Batch Mode” TCL Script Might Look Something Like thisISE Command Line Equivalence in Vivado A Separate “Project Flow” Uses DIFFERENT TCL CommandsPins and Ports May Not Be What you ExpectIII Vivado Physical ConstraintsFinding Netlist Objects in the Design Simple Example 1: UtilizationSimple Example #2: Find Netlist ObjectsSimple Example #3: Checking Your WorkSimple Example #4: More Sanity CheckingMaster Class: PROBES (1)Master Class: PROBES (2)IV. Vivado Timing ConstraintsVivado Timing Constraints Best PracticesClock Ground RulesFour Steps for Creating ClocksFour Steps for Creating Clocks (continued)Clock Creation ExampleSetting Input / Output Delaysset_input_delay: Used to specify a min setup �Requirement at the FPGA Inputs.�set_Output_Delay: Used to specify a clock to output requirement at the FPGA outputs. Multicycle Paths—Understand the ToolsTCL Timing Command Summary�Timing Closure?�V. For More InformationThere is No Shortage of Information on TCL

a generation ahead · vivado –mode tcl; launches vivado in command line mode. vivado –mode...

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