MIXED-SIGNAL LAYOUT GENERATION CONCEPTS

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING ANDCOMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSINGConsulting Editor: Mohammed Ismail. Ohio State University

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MIXED-SIGNAL LAYOUTGENERATION CONCEPTS

by

Chieh LinPhilips Research Laboratories

Arthur H.M. van RoermundEindhoven University of Technology

and

Domine M.W. LeenaertsPhilips Research Laboratories

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

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Preface

Layout generation is an important topic in IC design. For digital circuits a lot of researchhas been conducted in this area, resulting in a large variety of books and layout generationtools. However, with the ever increasing frequencies, we are facing now significant analogtypes of artifacts in the IC, introduced during the physical design phase, when schematics aretranslated to physical ICs via a layout. Moreover, with the trend to systems on chip, analogcircuitry and massive amounts of digital circuitry are going to be integrated on the same chip,now called a mixed-signal chip. Compatibility between the high-resolution but low-levelanalog signals and the relatively large-swing digital signals with their fast transition edges isbecoming a severe problem, which makes layout generation a tedious and complex job.

In this book we focus on two strongly coupled aspects of automatic layout generation,placement and routing. We will discuss the problem in detail in the context of mixed-signaldesigns. Apart from the physical artifacts and their parasitic influence on the electrical be-haviour of the circuit, we will address aspects related to the optimization problem associatedwith automatic layout generation. These are the optimization methods, with special empha-sis on simulated annealing; adequate data structures; appropriate models and representations;and efficient algorithms. As optimization is an iterative process, incremental algorithms thatonly generate strictly necessary new information are especially interesting to speed up theprocess. These algorithms get special attention.

The book can be seen as a combination of introductory texts and results of new research.Therefore it will be interesting for designers that like to get an overall picture, and for expertsin the field who like to see the state of the art, and who will be interested in the new topicsdiscussed in this book. Moreover, it is interesting both for designers and specialists in the areaof circuit design and for those working in the area of electronic design automation (EDA).

From the new contributions we will mention only a few selected issues here. A novel in-cremental approach to placement optimization is presented, featuring significantly improvedasymptotic computational complexity results for a single placement computation within asimulated-annealing environment. A new consistent linear-time algorithm is described thatmaps a given placement of modules in a user-specified region to an efficient formal represen-tation, such that the information can be further processed by means of efficient algorithms.Efficiency is an important issue for CAD tools. An improved robust placement algorithm isaddressed. The algorithm can incorporate range and boundary constraints that are imposedon specific modules in a very efficient manner. Further, a framework is given that incorpo-rates placement and routing, making it easy to take into account physical problems that arerelated to the spatial distribution of objects in a plane, which in this case is the plane of the IC.New results are shown on very fast Steiner-minimal-tree approximation algorithms in com-bination with efficient dynamic routing graph models. Extensive experimental evaluations ofthe proposed algorithms show that our algoritms compare favorably with the state of the art.Moreover, discrepancies are exposed in current packing-centric works that use inadequate

routing schemes.This book is the result of research conducted in the Mixed-signal Microelectronics Group

at Eindhoven University. At the time of conducting this research, all authors were membersof this group. Chieh Lin was a Ph.D. student of mine, Domine Leenaerts staff member andcoach. Both of them are now with Philips Research Laboratories in Eindhoven. It really is apleasure for me to write the preface of this book, and I hope many designers wi l l benefit fromit.

Prof.dr.ir. A.H.M. van RoermundChairman Mixed-signal Microelectronics GroupEindhoven University of Technology

vi Preface

Contents

Preface

List of Abbreviations

IntroductionOutline of the Book

Mapping Problems in the Design FlowTop-Down Flow and Bottom-Up Approach

A VLSI Design CyclePhysical DesignMixed-Signal Layout StylesFrom Circuit to LayoutLayout System Requirements

The Mapping ProblemHigh-Level SpecificationsLayout System SpecificationsConstraint Mapping ProblemHigh-Level SensitivitiesLower Level SensitivitiesSensitivity Computation Problem

Placement and Routing Constraints

11.1

22.1

2.1.12.1.22.1.32.1.42.1.5

2.22.2.12.2.22.2.32.2.42.2.52.2.6

2.3

Optimization Methods3VLSI Optimization Methods

Deterministic AlgorithmsStochastic AlgorithmsHeuristic Algorithms

3.13.1.13.1.23.1.3

3.2 Simulated AnnealingBasic SA AlgorithmProblem RepresentationPerturbation OperatorsAcceptance and Generation FunctionsTemperature ScheduleStop CriterionCost Function

Concluding Remarks

3.2.13.2.23.2.33.2.43.2.53.2.63.2.7

3.3

v

xi

14

7789

1112131414141515161617

1919202122232325262727282829

4 Optimization Approach Based on Simulated AnnealingOptimization FlowProblem Representation

PlacementRoutingSubstrate Coupling

Perturbation OperatorsAcceptance and Generation FunctionsTemperature ScheduleStop CriterionCost Function

Implicit Cost EvaluationConcluding Remarks

Efficient Algorithms and Data StructuresComputational ModelAsymptotic AnalysisComputational ComplexityData Structures for CAD

Corner StitchingLinked ListSplay TreeHash TablePriority QueueOther Advanced Data Structures

Concluding Remarks

PlacementPrevious WorkEffective and Efficient PlacementRepresentation Generality, Flexibility and SensitivitySequence Pair RepresentationGraph-Based Packing Computation

Relative Placement ComputationAn Efficient Relative Placement AlgorithmAbsolute Placement Computation

Non-Graph-Based Packing ComputationMaximum-Weight Common Subsequence (MWCS) ProblemMaximum-Weight Monotone Subsequence (MWMS) Problem

Graph-based Incremental Placement ComputationIncremental Relative Placement ComputationIncremental Relative Placement Computational ComplexityIncremental Absolute Placement ComputationIncremental Absolute Placement Computational ComplexityAverage Incremental Computational Complexity

Implementation Considerations

4.14.2

4.2.14.2.24.2.3

4.34.44.54.64.7

4.7.14.8

55.15.25.35.4

5.4.15.4.25.4.35.4.45.4.55.4.6

5.5

66.16.26.36.46.5

6.5.16.5.26.5.3

6.66.6.16.6.2

6.76.7.16.7.26.7.36.7.46.7.5

6.8

31323434343636383839394040

414242434444474850525353

5558596164686974767979818587949698

104104

viii Contents

Experimental ResultsA Single IterationPacking OptimizationConclusions

Placement-to-Sequence-Pair MappingConstrained Block Placement

Non-Graph-Based Constrained PlacementImplementation ConsiderationsExperimental Results on Non-Graph-Bascd Constrained Block Place-mentIncremental Graph-Based Constrained Placement

Concluding Remarks

RoutingThe Routing ProblemClassification of Routing Approaches

Routing HierarchyRouting Model

Previous WorkComputational ComplexityGlobal Routing Model

Model EfficiencyGlobal Routing Graph ComputationSupporting Dynamic Changes

Global Routing AlgorithmsTwo-pin Routing AlgorithmsMinimal Bounding Box (MBB) RoutingMinimum Spanning Tree (MST) RoutingPath-Based RoutingNode-Based Routing

Benchmarking of Heuristics in Our Routing ModelBenchmark Problem InstancesExperimental ResultsConcluding Remarks

Incremental RoutingRe-routing Nets Connected to Moved ModulesRe-routine Affected Nets Not Connected to Moved Modules

Impact of Routing on Placement QualityIntegrated Placement and RoutingExperimental ResultsConclusions

Concluding Remarks

6.96.9.16.9.26.9.3

6.106.11

6.11.16.11.26.11.3

6.11.46.12

77.17.2

7.2.17.2.2

7.37.47.5

7.5.17.5.27.5.3

7.67.6.17.6.27.6.37.6.47.6.5

7.77.7.17.7.27.7.3

7.87.8.17.8.2

7.97.9.17.9.27.9.3

7.10

105105106110111114115118

118121123

125126127128130131132133133134135137138142143144149151151152158158158162164164165167167

Contents ix

Dealing with Physical Phenomena: Parasitics, Crosstalk and Process VariationsPrevious WorkEfficiency and Accuracy RequirementsSelf-Parasitics

Wire Resistance, Capacitance and InductanceVia Resistance and Area

CrosstalkSubstrate CouplingParasitic Coupling Capacitance

Process VariationsIncorporating Crosstalk and Parasitics into RoutingIncorporating Substrate Coupling into Placement

A Basic ModuleGeneralized 2-Dimensional Substrate Coupling ModelSubstrate Coupling Impact MinimizationAn Efficient Substrate Coupling Impact Minimization AlgorithmImplementation ConsiderationsExperimental ResultsConclusions

Incremental Substrate Coupling Impact MinimizationConcluding Remarks

Conclusions

Bibliography

About the Authors

Index

88.18.28.3

8.3.18.3.2

8.48.4.18.4.2

8.58.68.7

8.7.18.7.28.7.38.7.48.7.58.7.68.7.7

8.88.9

9

169170170171171171172172174175175176176177179180181181182183183

185

189

199

201

x Contents

List of Abbreviations

ADBH Average-Distance-Based HeuristicADH Average-Distance HeuristicBSG Bounded Sliceline GridCA Chip AreaCAD Computer-Aided DesignCI Coupling ImpactCMWCS Constrained Maximum-Weight Common SubsequenceDAG Directed Acyclic GraphDV Direct ViewEDA Electronic Design AutomationESMT Euclidian Steiner Minimal TreeFPGA Field-Programmable Gate ArrayGSMT Graph Steiner Minimal TreeIC Integrated CircuitILP Incremental Longest PathsIP Intellectual PropertyISPBH Iterated Shortest-Paths-Based HeuristicLCS Longest Common SubsequenceLD Left-DownLOT Labeled Ordered TreeMBB Minimal Bounding BoxMST Minimum Spanning TreeMWCS Maximum-Weight Common SubsequenceMWMS Maximum-Weight Monotone SubsequenceNS Non-SlicingPE Placement EvaluationRAM Random-Access MachineRSMT Rectilinear Steiner Minimal TreeSA Simulated AnnealingSCIM Substrate Coupling Impact MinimizationSMT Steiner Minimal TreeSP Sequence PairSPBH Shortest-Paths-Based HeuristicSPH Shortest-Paths HeuristicSSSP Single-Source Shortest PathsVLSI Very Large Scale IntegrationWL Wire Length

Chapter 1

Introduction

The design of integrated circuits has been an actively exploited area for almost half a cen-tury already. The possibility to integrate a plethora of functions onto a small piece of semi-conductor material has enabled the development of many high-tech systems, e.g. the modernpersonal computer. Without exaggeration, one can state that without the invention of inte-grated circuits, the world would not be as it is today. With improvements in manufacturingtechnologies, also the integration density of components within a single integrated circuit(IC) has increased dramatically. The exponentially growing trend with the number of com-ponents in an IC as a function of time, still seems to hold and is expected to hold for at leastanother decade [Semiconductor Industry Association, 1998]. Figure 1.1 depicts this trendgraphically. This trend is better known as Moore’s Law. Within this figure, a few keywordsclarify some important trends. A very noticeable effect is that with increasingly smaller fea-ture sizes and larger designs, the intrinsic speed of transistors increases, but the (global) wiredelays also increase. With this trend, a vast area arose dedicated to the integration of circuits

which is called the field of Very Large Scale Integration (VLSI).

Increasing the number of components in a given area has an obvious cost benefit, becausethe number of produced ICs per t ime u n i t increases when other factors are kept constant.However, as always there is also a problematic dark side that comes wi th higher integration.The problems are even more pronounced due to higher operating frequencies of current sys-tems. Roughly speaking, one part of the problems is related to the percentage of working ICs,which is called yield. Yield is a complicated factor that has l inks with many aspects of VLSItechnology; from system design to circuit design, to layout design, to technology. More-over, due to smaller sizes, accuracy and power dissipation problems emerge. Typically, mostof these performance factors can be traded off against each other. The other part consistsof the increasing influence of unavoidable parasitic elements such as parasitic resistances,capacitances, and inductances. But also parasitic substrate coupling and, to a lesser extent,electromagnetic coupling cannot be neglected anymore. Simply stated, the non-ideal behav-ior of semi-conductor material starts affecting the funct ional i ty of the IC in such a way, thatmeasures have to be taken to ensure good funct ioning . The correct func t ion ing of a systemis especially susceptible to these parasitic phenomena in the case of mixed-signal designs,where both (insensitive and noisy) digital and (sensit ive) analog bui ld ing blocks are presenton the same chip.

Practical experience has been used and is s t i l l used to l imi t the adverse effects of non-idealities. However, due to the high complexity of VLSI systems it is an immensely d i f f icu l ttask to handle all problems adequately, even for an expert designer. This is where the com-puter comes into play. When a computer is used properly, it is able to handle large amountsof data and process it in such a way that the generated output satisfies certain given specifi-cations. The use of computers in a design task is called Computer Aided Design (CAD). Amore appropriate term in connection with computer-aided design of ICs is Electronic DesignAutomation (EDA) which includes electronic CAD tools, but is more general. The purposeof a CAD tool is to support the designer during the process of realizing an IC.

The final physical outcome of the design process is a disc of si l icon, called a wafer, whichconsists of a number of more or less identical copies of the same integrated circuit . Thiswafer is then cut, resulting in a set of dies, each one of them containing the same integratedcircuit. The creation of such a wafer is accomplished using a set of masks which are used todeposit several layers of different materials onto the wafer. The task of organizing geometricinformation in this context, resulting in an answer to the question which materials have to beput where on the wafer, is called physical design. The end result of a physical design stepis a called a layout, which is essentially a set of masks that comply with given design rules.Also layout synthesis or layout generation are used frequently in the same context. Althoughlayout generation is a very important step in the VLSI process, it is only one of many steps.Some other important steps are circuit design, simulation and verification.

Our primary concern in this work is the layout generation step of VLSI design. Morespecifically, we deal with a remarkably interesting and challenging subclass consisting ofboth analog and digital ingredients. In essence, layout generation is accomplished by solvingtwo strongly coupled problems under a set of constraints. These two problems are known asthe placement and the routing problem.

The design of integrated circuits is not new. Therefore, most problems associated with layoutgeneration are not new. However, most problems became real problems when feature sizesapproached submicron and deep-submicron dimensions and operating frequencies made a

2 Introduction

leap forward.Historically, the roots of algorithmic approaches to designing layouts lie in the digital

area. It is there where the circuits grew extraordinary fast to incredibly large sizes. There-fore, layout design automation was first investigated and employed in that area. However,contemporary mixed-signal designs also require the use of computers due to the large numberof phenomena that have to be taken into account in order to comply with the specifications.Larger designs, tighter specifications and more interdependencies have led to increased com-plexity. The layout problem was boosted again recently by the observation that the layoutproblem for digital designs should be looked at through analog glasses. For, essentially, thephenomena that form bottlenecks in digital layout design, are analog in nature.

An illustrative overview is given here which should give a good impression of the workthat has been and is carried out in the VLSI layout generation domain, especially in the mixed-signal and analog fields. By no means does this overview intend to be complete. It onlyprovides a representative sampling of existing mixed-signal and analog layout generationsystems, in order to give an impression of the state-of-the-art in this field, and to illustrate thevariety of ways in which typical constraints are handled and problems are approached.

In the works [Malavasi, 1993, Charbon, 1995], all conducted at the University of Califor-nia at Berkeley, several techniques are introduced for performance-driven layout of analogintegrated circuits. The basic concepts are sensitivity computation, modeling of performanceconstraints and performance-driven placement, routing and compaction. The approach is onlysuitable for small analog integrated circuits, because the system behavior scales very badlywith increasing problem size. Furthermore, the circuits that can be handled are assumed tobe linear. Examples of such circuits are operational amplifiers and filters. In [Chang, 1994]the above approach is extended and incorporated into a top-down constraint-driven designmethodology for analog integrated circuits.

Researchers from Carnegie Mellon University have been quite successful with their toolsASTRX/OBLX [Ochotta et al., 1996] and KOAN/ANAGRAM [Cohn et al., 1991,Cohn et al.,1994]. The tools are known to be successful when applied to linear analog circuits such asfilters and operational amplifiers.

Also, the Catholic University of Leuven has contributed significantly to the developmentof analog CAD tools. In [Lampaert, 1998] analog layout generation for performance andmanufacturability is described in detail. The system employs a top-down hierarchical designmethodology in which the explicit generation of a specific set of low-level constraints isavoided. Instead, the layout tools are driven more or less directly by higher-level performanceconstraints via pre-determined performance sensitivity values. An implicit assumption of thisapproach is that the circuit is sufficiently linear in the region in which the layout parametersunder consideration have influence. The ultimate goal is a layout that satisfies all performanceconstraints by construction.

Several other groups and researchers have attempted to transfer the methodologies whichare used in the digital VLSI domain to the analog and mixed-signal VLSI domain, but mostof these approaches have not been very successful as yet. The main reason being the factthat digital approaches rely on certain assumptions (to reduce complexity) that are simplyunacceptable in the analog domain. A good example of this is the consideration of only acritical path to determine the quality of wiring.

From the previous discussion it should be clear that VLSI design consists of several tasks

3

which are very hard to solve in a proper way. Also the design step that considers layoutgeneration is extremely difficult. It should be clear that the qual i ty of a layout is of utmostimportance in any IC design. Thus far, only few researchers have concentrated on layout gen-eration for mixed-signal designs. Although layout generators are known for analog designs,those systems are usually not suitable for general application to mixed-signal designs wherethe layout problems are worst.

There is not a single layout generator which is best compared to others. All existingapproaches and systems have fundamental limitations and weaknesses. The current layoutgeneration problems suffer somehow from at least one of the following problems.

Properly placing objects – sub-circuit modules – in a two-dimensional plane is per-formed poorly with respect to wiring quality.

Only a subset of mixed-signal design constraints is (or can be) taken into account dur-ing placement and routing.

Ad hoc solutions are used which are not very robust and require a significant amountof (problem dependent) tuning effort.

Scalability properties are poor due to inefficient modeling and/or implementation.

Thus, the necessity of improved layout generation concepts and systems is clear.

The goal of this book is to establish methodologies and concepts to automate the layoutgeneration step within the framework of mixed-signal VLSI design.

In principle there are two ways to approach the problem of generating high-quality mixed-signal layouts. One approach is to keep refining well-known techniques from the digitaldesign field, taking into account increasingly important second-order effects, so as to satisfymixed-signal and analog requirements. The other approach is to review the physical designproblem anew in order to find fundamentally more efficient means to tackle it. For instance,a more efficient formal representation could contribute to this, eventually leading to bettersolutions in less time, combined with better scalability performance. The term scalabilityis used here to denote the behavior of a computing system when the problem instance sizeunder consideration increases. Scalability and generality of the approach is regarded as amajor concern.

1.1 Outline of the Book

Hereafter, the main topics which are covered in this book are described briefly. First theproblem we want to solve is described in detail in Chapter 2, from a system view to assessablesubproblems. Also the inputs and outputs of the layout system are defined explicitly. Itis made clear that various mapping problems need to be solved to establish a transparentinterface between real-world specifications and desired specifications.

Then, in Chapter 3 an overview of existing optimization methods is given which arepossible candidates for VLSI-related problems. Based on our requirements and previousresults on similar problems, we indicate which optimization method has preference.

4 Introduction

Consequently, in Chapter 4 we focus on the chosen optimization method and explore it inmore detail, describing its properties and its application to our problem representation. Thus,the most important aspects of our optimization approach are discussed.

We then clarify the impact of efficient algorithms and data structures on the performanceof the overall system in Chapter 5. Moreover, scalability issues in connection with the effi-ciency of algorithms and their data structures are discussed.

One of the main topics in this book work is on the problem of optimally placing a set ofobjects in a two-dimensional plane under certain constraints. Chapter 6 discusses this prob-lem in depth and an efficient solution is proposed. Theoretical analyses are carried out andcompared with existing results. The chapter also gives an overview of all currently knownapproaches in the proposed placement context, linking several related but strictly mathemati-cally oriented fields of research to the placement problem. Experimental results are obtained,which confirm the theory.

As will be made clear at a later stage, placement of objects does not have any practicaluse if routing is ignored. Therefore, in Chapter 7 we explore routing issues within the sameoptimization framework, and put a significant amount of effort into establishing a routingmethodology. Apart from this, existing results are compared with new experimental resultsand discrepancies in previous approaches are exposed.

Chapter 8 covers the problems of non-ideal effects in a layout. Both crosstalk and par-asitics are well-known culprits of performance degradation in high-frequency designs. Inmixed-signal circuits these phenomena manifest themselves quite rapidly, as compared tofully digital designs with large noise margins or fully analog designs with less “noisy” com-ponents. An overview is given of existing methods to tackle problems due to crosstalk andparasitics. Furthermore, a method is proposed to incorporate substrate coupling into the op-timization framework in a most efficient manner.

Since algorithmic and representation efficiency are serious concerns throughout this re-search work, a major part of this book discusses fundamental concepts to improve efficiency.As these concepts are tightly coupled with a certain problem, it is more convenient to intro-duce and elaborate on them while discussing the underlying problem. A fundamental conceptto improve efficiency is incremental computation. In essence, the idea is to compute only newinformation when it is strictly necessary. We show that this approach leads to fundamentalimprovements in placement and global routing efficiency in the adopted stochastic (simulatedannealing) optimization framework. Note that higher computational efficiency automaticallyimplies better scalability properties. In each chapter, where appropriate, experimental resultsare given after the discussion of the respective algorithms. Furthermore, we have attemptedto describe and present the experiments (and their results) in such a way that comparison withexisting works is not hampered.

We end this book with main conclusions in Chapter 9.

1.1 Outline of the Book 5

Chapter 2

Mapping Problems in the Design Flow

This chapter describes the problem which is attacked in this book in more detail. We showexplicitly where the problem of layout generation is located within the overall VLSI designcycle. Then we zoom in on the layout problem and show that it is a non-trivial problem tosolve. In order to solve the problem adequately, first it has to be defined in an accurate way.One part of problem definition entails proper modeling of physical entities. The other part isformulation of given “real-life” specifications into simpler specifications that can be handledproperly at an algorithmic level.

In principle, the layout problem can be split in two, strongly coupled, parts. One partis the placement or floorplanning problem, the other part is the routing problem. A typicallayout problem could be stated as follows. Given a set of geometric objects to be placedin a two-dimensional plane, place these objects in such a way that a certain cost function isminimal. A standard textbook on physical design automation will take for the cost functionthe total length of all interconnecting wires. The catch is that in order to compute or estimatethe length of a wire, placement information is needed. But, routing information is needed tocompute a placement! This loop can, for instance, be broken by computing a placement basedon the amount of interconnections between the blocks; blocks with many interconnectionsshould be placed closer together than blocks with less interconnections. In textbooks, theapproach is called the min-cut problem. It is an approximation to the layout problem, in thatit does not cope with wire length but with number of interconnections.

For more information on the layout problem the reader is referred to, e.g., [Lengauer,1990, Sherwani, 1993].

2.1 Top-Down Flow and Bottom-Up Approach

In order to adequately solve the layout problem, it is necessary to divide this complex prob-lem into less complex and conceptually easier to handle subproblems such as the placementproblem and the routing problem. Moreover, we have to define the required information tosolve the layout problem more precisely. Hence, the path from electrical circuit description,process technology data, and system specifications, to the layout system is made explicit.Generally, we denote the flow of operations, from a high level to lower levels, leading torefinements at each step, a top-down flow. The information is essentially pushed into onedirection, with or without some feedback path, to arrive at a desired target. The need for thisessentially hierarchical approach is obvious when the initial problem is too difficult to assessat once.

In cases where we precisely know the impact of a certain higher-level decision on a lowerlevel, a top-down approach is very convenient. However, when problems become more com-plicated and interdependencies start playing an important role, it is almost impossible toaccomplish the task in an adequate way with solely top-down information. As the amount ofinformation from a lower level starts getting increasingly more important on a higher level,we speak of a bottom-up flow. We make plausible that, indeed, a bottom-up approach natu-rally applies to layout generation.

During the top-down flow of the design cycle, we arrive at the point where informationneeds to be supplied to the layout generation system. Hence, the interface of the layoutsystem must be defined explicitly, facilitating communication of relevant information to thelayout system. As a consequence, the layout system itself can operate more efficiently andconsistently generate predictable results as a function of several inpu t parameters which wil lbe described shortly.

2.1.1 A VLSI Design Cycle

The fundamental process steps in a VLSI design cycle are shown in Figure 2.1. The fourblocks on the left-hand side represent processes that start from a very high level of an idea.Then specifications are defined in the next block. The architectural design process dealswith functional blocks at a high level for which (conceptual) realizations exist, and theirintercommunication. Finally at the lowest conceptual level, the functional blocks must betransformed to building blocks which are used in circui t design. This is the top-down partof the cycle. The result of the top-down flow is an electrical circui t . This is the basis ofthe bottom-up flow. The last four blocks of the cycle consist of the generation of buildingblock layout modules at the lowest level, going up to placement and routing of these layout

8 Mapping Problems in the Design Flow

modules. After placement and routing, the layout can be manufactured and finally tested tosee if its functionality and performance complies with the original idea and its specifications.Although the overall flow of information is top-down, the last four blocks in the diagram aredrawn “bottom-up”. The intention is to make clear that the physical design part requires anessentially bottom-up approach. The reason for this is that a mixed-signal design has bothdigital and analog components and typically these components are highly interconnected. Itis this class of designs that is impacted most severely by parasitic effects such as substratecoupling, delay, mismatch, etc. As such, it is sheer impossible to decouple placement androuting while targeting high quality. Thus, predicting the result of placement and routing isat least as difficult.

The outer flow in the figure states what type of information is exhibited at a certain stagein the design cycle. At the highest level the behavioral representation is eminent. Afterthat, the structural representation becomes important, in which more precise information isgiven on what functions are performed where. At the technological representation level, theimplementation aspects come into play. It specifies what type of circuit elements are used,their properties, and so on. The physical representation level comprises of everything that isdirectly related to the layout of the circuit on the wafer. Finally, a prototype IC is available.

Note that the direction of the arrows only indicates the flow of the processes in time foreach part of the overall design, not the interdependency of the processes. For example, inorder to perform adequate placement and routing, information is needed on certain specifica-tions. Furthermore, in the architectural design, testing facilities should be taken into account.In short, strong interrelationships exist between almost all of the VLSI process steps. Hence,it is impossible to regard a specific process step without taking notice of the other steps. Onthe other hand, including many process steps in an attempt to find a universal layout method-ology will be too idealistic because of the intrinsic problem complexities involved. A way tosolve this dilemma, is to define an interface from each block to the other blocks and specifyexactly what is input and what is output, and find a methodology that will provide high-qualitylayouts within the confined framework. This is the well-known top-down approach.

2.1.2 Physical Design

The focus of this book is on several aspects of the physical design step; more specificallythe placement and routing phases. Physical design is the last step in the design cycle wherea designer can exercise his or her influence on the final performance of an integrated circuitbefore it is fixed onto silicon. In Figure 2.1 the part of the VLSI design cycle that will befocused on in this work, is shown in the shaded area: the circuit, module generation, andplacement/routing.

The physical design step in itself can also be seen as an iteration loop. In order to l imitthe complexity due to interdependencies, we presume that the given circuit, which is one ofthe inputs of the physical design step, is our nominal reference. As a consequence, we donot attempt to improve or to alter the behavior of our reference circuit; our goal is to preventdeterioration of system performance as much as possible due to undesired but unavoidableimplementation phenomena such as crosstalk, wire delays, surface gradients, etc.

Figure 2.2 gives a classical flow diagram which represents the physical design. As can beseen from the diagram, the input of the physical design phase consists of the circuit netlist,circuit specifications, and technology data. By means of module generation, the basic objects

2.1 Top-Down Flow and Bottom-Up Approach 9

are conceived for the placement and routing phase, which are the core problems of physicaldesign. The initial layout needs to be checked for design rules compliance. After that, anextraction of the layout needs to be performed. The extracted information is an annotatednetlist including all parasitic elements which are not or only partially accounted for in thecircuit netlist (schematic). This annotated netlist is compared with the original netlist to seeif any discrepancies have been introduced, apart from the parasitics. Using the annotatednetlist, circuit simulations are performed, typically with a Spice-like simulation tool. If all iswell, and the specifications are complied with, the final layout is ready to be fabricated. Ifsomething is wrong, a change in the placement/routing is required and the loop is repeateduntil the layout is acceptable. However, it may turn out that the layout system cannot find

a satisfactory solution (even if the system would be ideal). In such cases there is an escaperoute via the dotted arrows to adjust, for example, the specifications, or transistor modelswhich are used by the simulator.

10 Mapping Problems in the Design Flow

2.1.3 Mixed-Signal Layout Styles

Several layout styles are available for implementing mixed-signal and analog integrated cir-cuits. The differences in these styles are typically density, performance, flexibility, and time-to-market, where one characteristic is usually traded off against another. There is a broadvariety of different layout styles. It is difficult to classify them from the point of layout flexi-bility, i.e. the degrees of freedom a designer has to make layout decisions. Hereafter followsa brief overview of a few common layout styles. For more information, the interested readeris referred to [Baker et al., 1998].

Full Custom

In a full-custom layout every component in the design is hand-crafted with the ultimate trade-off between performance, area, and power, which often results in highly irregular placementand routing. Typically, no restrictions are imposed on the width, height, aspect ratio, or ter-minal positions of the layout blocks. Furthermore, each block is allowed to be placed at anylocation on the chip surface without restrictions. Of course, design rules have to be takeninto account at all times. Obviously, this technique has the largest flexibility, the best per-formance, and a very high integration density, since the layout can be optimized and tunedfor each specific application. A major drawback of the full-custom layout technique is thatit is immensely labor-intensive, resulting in large turnaround times and thus a large time-to-market. In addition, the tools that (partially) support the designer in creating a high-qualitylayout are very complex (although their main task is to limit design complexity) and can onlylead to a good layout with the aid of an expert.

Standard Cell

In order to overcome the drawbacks of the full-custom layout style, mainly due to complex-ity, several methods have been proposed to mitigate the overwhelming effect of complexitycombined with full design freedom. This is essentially accomplished by putting restrictionsand constraints on the physical design of the circuits. Standard cell layout is a common lay-out technique which was first introduced in the digital VLSI domain. It is featured by the useof a standard library of prefabricated cells with different functionalities. The standard cell(a layout block) is restricted to a fixed height and has variable width. All cells are placed ina number of rows. A certain amount of space between two rows, also called a channel, isreserved for routing. Thus, placement and routing have become (conceptually) simpler.

Field-Programmable Gate Array (FPGA)

The essence of an FPGA consists of a fixed number of functional (but primitive) buildingblocks distributed on a chip, where the actual interconnections are defined via electricallyprogrammable switches. FPGAs cannot be used for higher frequencies because of inferiorrouting and additional parasitics.

Sea of Gates

The sea-of-gates design style is comparable with FPGA; all layout blocks are predefined onchip and the designer only has to define the interconnect. Unlike FPGA, no switches are

2.1 Top-Down Flow and Bottom-Up Approach 11