microcontrollers - meam.design
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Microcontrollers
Integrated Circuits in 1958
The first single-chip microprocessor, circa 1971
(Intel 4004: 740kHz, 4-bit, 4KB cache, 2,300 transistors)
(Intel Gulftown 6-core processor - 1.17B transistors)
microprocessors, circa 2011
The microcontroller
The microcontroller
28-pin DIP8-bit Atmel ATmega32U4 processor16 MHz clock25 I/O pins12 channel 10-bit ADC32k Flash, 1k EEPROM, 2.5k SRAM4 independent timers with PWMUSART, I2C, SPI, JTAG, USB
47766D–AVR–01/09
ATmega16U4/ATmega32U4
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.
The ATmega16U4/ATmega32U4 provides the following features: 16/32K bytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 512Bytes/1K bytes EEPROM,1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32general purpose working registers, four flexible Timer/Counters with compare modes and PWM,one more high-speed Timer/Counter with compare modes and PLL adjustable source, oneUSART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-
PROGRAMCOUNTER
STACKPOINTER
PROGRAMFLASH
MCU CONTROLREGISTER
GENERALPURPOSE
REGISTERS
INSTRUCTIONREGISTER
TIMERS/COUNTERS
INSTRUCTIONDECODER
DATA DIR.REG. PORTB
DATA DIR.REG. PORTE
DATA DIR.REG. PORTD
DATA REGISTERPORTB
DATA REGISTERPORTE
DATA REGISTERPORTD
INTERRUPTUNIT
EEPROM
SPI
STATUSREGISTER
SRAM
USART1
Z
Y
X
ALU
PORTB DRIVERSPORTE DRIVERS
PORTF DRIVERS
PORTD DRIVERS
PORTC DRIVERS
PB7 - PB0PE6
PF7 - PF4
RES
ET
VCC
GND
XTAL
1
XTAL
2
CONTROLLINES
PC7
INTERNALOSCILLATOR
WATCHDOGTIMER
8-BIT DA TA BUS
USB 2.0
TIMING ANDCONTROL
OSCILLATOR
CALIB. OSC
DATA DIR.REG. PORTC
DATA REGISTERPORTC
ON-CHIP DEBUG
JTAG TAP
PROGRAMMINGLOGIC
BOUNDARY- SCAN
DATA DIR.REG. PORTF
DATA REGISTERPORTF
POR - BODRESET
PD7 - PD0
TWO-WIRE SERIALINTERFACE
PLLHIGH SPEED
TIMER/PWM
PE2
PC6PF1 PF0
ON-CHIPUSB PAD 3VREGULATOR
UVcc
UCap
1uF
ANALOGCOMPARATOR
VBUS
DP
DM
ADCAGND
AREF
AVCC
TEMPERATURESENSOR
take a break and go learn
binary
Microcontroller Architectures
A Harvard architecture computer uses separate pathways for instructions and data
CPU datainstructions
A Von Neumann architecture computer uses a shared pathway for instructions and data to/from the CPU
CPUdata&instructions
Memory Map
data(8 bit)
address(16 bit)
instruction(16 or 32 bit)
address(16 bit)
0x7FFF
0x0000
32k Flash“Program Memory”
2.5k SRAM“Data Memory”
0x0000
0x0AFF
CPU
2.5k SRAM“Data Memory”
0x0000
0x0AFF
0x00200x0060
0x0100
working regI/O
ext. I/O
SRAM
MSB LSB
address: 0x02A5
value: 0x2F
0 0 1 0 1 1 1 1
Memory Map
2.5k SRAM“Data Memory”
0x0000
0x0AFF
0x00200x0060
0x0100
working regI/O
ext. I/O
SRAM
Memory Map
GPIO
Clock
SerialComm
Timer
A2D