-1-UC San Diego / VLSI CAD Laboratory

Methodology for Electromigration Signoff in the

Presence ofAdaptive Voltage Scaling

Methodology for Electromigration Signoff in the

Presence ofAdaptive Voltage Scaling

Wei-Ting Jonas Chan, Andrew B. Kahng and Siddhartha Nath

VLSI CAD LABORATORY, UC San Diego

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OutlineOutline Motivation Previous Work Analysis Models Experimental Setup and Results Conclusions

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Bias Temperature Instability (BTI)Bias Temperature Instability (BTI)

|ΔVth| increases when device is on (stressed)|ΔVth| is partially recovered when device is off (relaxed)

Device aging (|ΔVth|) accumulates over timeNBTI: PMOS PBTI: NMOS

|Vgs| timeON OFF

ON OFF

[VattikondaWC06]

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Electromigration in InterconnectsElectromigration in Interconnects

Electromigration (EM) is the gradual displacement of metal atoms in an interconnect

Iavg causes DC EM and affects power delivery networks

Irms causes AC EM and affects clock and logic signals

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Adaptive Voltage Scaling (AVS)Adaptive Voltage Scaling (AVS) Accumulated BTI higher |ΔVth| slower circuit AVS can compensate for performance degradation

Circuit

Closed-loop AVS

On-chip aging monitor

Circuit performanceVoltage

regulator

Circuit performance

Vdd

time

time

Without AVSWith AVS

target

-6-

BTI + AVS SignoffBTI + AVS Signoff

Vlib

VBTIDerated library

|Vt| Circuit implementation

and signoff

netlistBTI degradation

and AVSVfinal

?

Step 1 Step 2 Step 3

Signoff loop of BTI

Ensure circuit meets timing requirements under BTI aging Use AVS to offset BTI degradation

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EM + BTI + AVS Signoff?EM + BTI + AVS Signoff?

Stress on Wires

VfinalDesign

Implementation

Vlib , VBTIDerated Libraries

Signoff loop of BTI + EM

Aggressive AVS scheduling results in more severe degradation Guardband during implementation increases due to degradation

How to signoff for EM with AVS? What are area, power costs? What is the impact to EM lifetime?

BTI loop

EM loop

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OutlineOutline Motivation Previous Work Analysis Models Experimental Setup and Results Conclusions

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Previous WorksPrevious Works EM lifetime and wire degradation models

– Closed-form lifetime models (Black, Arnaud et al., Federspiel et al.)

– Statistical model for wire degradation (Mishra et al.) Claim their model reduces pessimism in Black’s Equation

EM-durable circuits– Wire-sizing algorithms (Adler et al., Jiang et al.)– Wire segmentation and via insertion algorithms (Li et al.)– Current-aware routers (Lienig et al., Yan et al.)

BTI Signoff– Interactions between AVS and BTI (Chan et al., Chen et al.,

Basoglu et al.)

No studies on three-way interactions between BTI, EM and AVS!!!

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OutlineOutline Motivation Previous Work Analysis Models Experimental Setup and Results Conclusions

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𝑡50=𝐴∗

𝐽𝑛∙𝑒

𝐸𝑎

𝑘𝑇

EM Model: Black’s EquationEM Model: Black’s Equation

t50 – median time to failure (= loge 2 x MTTF) A* – geometry-dependent constant J – current density in interconnect segment n – constant ( = 2) Ea – activation energy of metal atoms k – Boltzmann’s constant T – temperature of the interconnect

EM degrades interconnect lifetime Black’s Equation calculates lifetime of interconnect

segment due to EM degradation

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New EM Model: Mishra-SapatnekarNew EM Model: Mishra-Sapatnekar Models resistance increase due to voids in wires instead of MTTF Derived from statistical model of nucleation and growth time

∆𝑅𝑅𝑜

=( 𝜌𝑇𝑎

𝜌𝐶𝑢

𝐴𝐶𝑢

𝐴𝑇𝑎

−1) 𝐿𝑣𝑜𝑖𝑑

𝐿𝑤𝑖𝑟𝑒

– Resistance increase due to voids in wires – Resistivity of copper Tantalum liner , – Cross section area of of copper and Tantalum liners , – Length of void and wire – Diffusivity during void growth period – Effective charge number – observation time and length of nucleation

𝐿𝑣𝑜𝑖𝑑=(𝐷𝑒𝑓𝑓 .𝑔

𝑘𝐵𝑇 )𝑒𝑍∗𝑒𝑓𝑓❑ 𝜌𝑐𝑢 𝑗 (𝑡𝑜−𝑡𝑛)

Log-normal distribution

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New EM Model: Impact on Signal WiresNew EM Model: Impact on Signal Wires

0.0E+00

5.0E-10

1.0E-09

1.5E-09

2.0E-09

2.5E-091X2X3X4X6X

(∆R+R0)/R0

Dela

y (

sec)

Sweep different gate sizes up to 8× Larger gates do not necessarily help to reduce EM impact ∼8% delay degradation for buffers smaller than 4× when

resistance increases to high values ( 146%) ∼

Statistical model is optimistic in predicting delay penalties

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New EM Model: Impact on Signal WiresNew EM Model: Impact on Signal Wires

100%

121%

146%

177%

214%

259%

314%

380%

459%

556%

0.0E+00

1.0E-09

2.0E-09

3.0E-09

4.0E-09

(∆R+R0)/R0

Dela

y (

sec)

Multiple of FO4

Gate = 8X

Sweep FO4 capacitive load by factors {1.0×, 1.6×, 2.1×} EM slows down circuit performance due to

increased stage delay increased output transition times

Delay increases by ~35% with large resistance increase ~200%

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OutlineOutline Motivation Previous Work Analysis Models Experimental Setup and Results Conclusions

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Experimental SetupExperimental Setup Multiple implementations based on different signoff

corners AES and DMA designs from Opencores 28nm foundry FDSOI technology Commercial tool-based SP&R flows Synopsys PrimeTime for timing analysis Matlab for AVS simlulation with BTI and EM

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AVS Signoff Corner SelectionAVS Signoff Corner Selection

Impl# 1 2 3 4 5 6 7 8

Vlib(V) Vmin Vmin Vmax Vmin 0.98V 0.97V 0.96V 0.95V

VBTI (V) Vmin Vmax Vmax N/A 0.98V 0.97V 0.96V 0.95V

• Characterize different derated libraries against BTI• Evaluate impact of library characterization• Vfinal is predicted by cell chains ahead of implementation

• Eight implementations1 : VBTI = Vlib = Vmin Ignore AVS2 : Most pessimistic derated library3 : VBTI = Vlib = Vmax Extreme corner for AVS4 : No derated library (reference)5 : Sweep around Vfinal

6 : Vfinal by cell chain prediction [ChanCK13]7 : Sweep around Vfinal

8 : Sweep around Vfinal

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AVS Signoff Corner SelectionAVS Signoff Corner Selection

10000 12000 14000 16000 18000 20000 2200020222426283032

44

4

888

7776

66

555

3

33

2

22

11

1

Non-EM Aware After Fixing (Mishra)After Fixing (Black's)

Area (μm2)

Pow

er

(mW

)

AES

Optimistic about AVS

Pessimistic about AVS

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AVS Impact on EM LifetimeAVS Impact on EM Lifetime

1 2 3 4 5 6 7 8 90

2

4

6

8

10

12

0.8

0.9

1

1.1

1.2

Lifetime (year)

Implementation #

Lif

eti

me (

year)

Vfi

nal (V

)

Vfinal (V)

𝑀𝑇𝑇𝐹 (𝑖 )=𝑀𝑇𝑇𝐹 (𝑖−1)×(𝑉 𝐷𝐷 (𝑖−1 )𝑉 𝐷𝐷 (𝑖 ) )

2

• Assume no EM fix at signoff• BTI degradation is checked at each step and MTTF is updated as

30% MTTF penalty

200mV voltage compensation

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Power Penalty to Fix EM with AVSPower Penalty to Fix EM with AVS

1 2 3 4 5 6 7 8 912.00

13.00

14.00

15.00

16.00

17.00

0.30

0.32

0.34

0.36

Core Power (mW) P/G Power (mW)

Implemetation #

Core

Pow

er

(mW

)

P/G

Pow

er

(mW

)

• Core power increases due to elevated voltage • P/G power increases due to both elevated voltage and mesh

degradation• A tradeoff between invested guardband in signoff

Highest invested guardband

Least invested guardband

14% power penalty

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EM Impact on AVS SchedulingEM Impact on AVS Scheduling AVS behavior is an important role to decide the EM penalty

on lifetime We empirically sweep AVS voltage step size to obtain the

impact– #Implementation 3 is used– AVS starts at 0.9V, and no EM fix for AVS in signoff

5 step sizes – S1 = 8mV– S2 = 10mV– S3 = 15mV– S4 = 18mV– S5 = 20mV

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0 2 4 6 8 10 120.900.920.940.960.981.001.021.04

S1 S2 S3 S4 S5

Year

VD

D

DMA, #3S1 S2 S3 S4 S5

7.8

7.9

8.0

8.1

MTTF (

Year)

EM Impact on AVS SchedulingEM Impact on AVS Scheduling

1.2 years MTTF penalty

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OutlineOutline Motivation Previous Work Analysis Models Experimental Setup and Results Conclusions

-24-

ConclusionsConclusions We study the joint impact of BTI, AVS and EM on signoff We study two EM models and their impact on

implementation (i) Black’s Equation and (ii) Mishra-Sapatnekar

We demonstrate empirical results for lifetime, area and power penalty due to EM when AVS is involved– Up to 30% lifetime penalty

We demonstrate empirical results for power at different signoff corners– Up to 14% power penalty

Ongoing– Improve accuracy of signoff using a temperature gradient– Learning-based modeling to quantify design costs of reliability

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Thank you!

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Backup

-27-

EM Model: Mishra-SapatnekarEM Model: Mishra-Sapatnekar

∆𝑅𝑅𝑜

=( 𝜌𝑇𝑎

𝜌𝐶𝑢

𝐴𝐶𝑢

𝐴𝑇𝑎

−1) 𝐿𝑣𝑜𝑖𝑑

𝐿𝑤𝑖𝑟𝑒

𝐿𝑣𝑜𝑖𝑑=(𝐷𝑒𝑓𝑓 .𝑔

𝑘𝐵𝑇 )𝑒𝑍∗𝑒𝑓𝑓❑ 𝜌𝑐𝑢 𝑗 (𝑡0−𝑡𝑛)

Log-normal distribution

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Study on EM Impact in AVS SystemStudy on EM Impact in AVS System

Vregulator

Core (VDD domain)

Mesh and ring∆RPG (due to EM)

Assume two types of degradation IR drop due to power mesh degradation (∆RPG due to EM) Signal wire degradation due to EM