memory tshooting

8/3/2019 Memory Tshooting

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Memory is a cornerstone of the modern PC. Memory that holds the program code and data that is processed by the CPUand it is this intimate relationship between memoryand the CPU that forms the basis of computer performance. With larger and faster CPUsconstantly being introduced, and more complex software is developed to take advantage of the processing power. In turn, the more complex software demands larger amounts of faster memory. With the explosive growth of Windows (and more recently, Windows 95)the demands made on memory performance are more acute than ever. These demandshave resulted in a proliferation of memory types that go far beyond the simple, traditionalDRAM. Cache (SRAM), fast page-mode (FPM) memory, extended data output (EDO)memory, video memory (VRAM), synchronous DRAM (SDRAM), flash BIOS, and other exotic memory types (such as RAMBUS) now compete for the attention of PC techni-cians. These new forms of memory also present some new problems. This chapter will

provide you an understanding of memory types, configurations, installation concerns, and troubleshooting options.

Essential Memory ConceptsThe first step in any discussion of memory is to understand basically how memory works.If you already have a good grasp of memory basics, feel free to skip this part of the chapter.

MEMORY ORGANIZATION

All memory is basically an array organized as rows and columns (Fig. 23-1). Each row isknown as an address one million or more addresses might be on a single memory IC.The columns represent data bitsa typical high-density memory IC has 1 bit, but might

have 2 or 4 bits, depending on the overall amount of memory required.

ESSENTIAL MEMORY CONCEPTS 745

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Rows

Cell matrixarray

D0

M data bits(8-bit data word)

Address 0

Address 1

D7

Address N

FIGURE 23-1 Simplified diagram of a memory array.


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As you probably see in Fig. 23-1, the intersection of each column and row is an individ-

ual memory bit (known as a cell ). This is important because the number of components ina celland the way those components are fabricated onto the memory ICwill have a profound impact on memory performance. For example, a classic DRAM cell is a singleMOS transistor, and static RAM (or SRAM) cells often pack several transistors and other components onto the IC die. Although you do not have to be an expert on IC design, youshould realize that the internal fabrication of a memory IC has more to do with its perfor-mance than just the way it is soldered into your computer.

MEMORY SIGNALS

A memory IC communicates with the outside world through three sets of signals: ad-dress lines, data lines, and control lines. Figure 23-2 illustrates these signal types. Addresslines define which row of the memory array will be active. In actuality, the address is

specified as a binary number, and conversion circuitry inside the memory IC translates the binary number into a specific row signal. Data lines pass binary values back and forth tothe defined address. Control lines are used to operate the memory IC. A Read/Write(R/W) line defines whether data is being read from the specified address or written toit. A Chip Select (CS) signal makes a memory IC active or inactive (this ability to dis-connect from a circuit is what allows a myriad of memory ICs to all share common ad-dress and data signals in the computer). Some memory types require additional signals,such as Row Address-Select (RAS) and Column Address-Select (CAS), for refresh oper-ations. More exotic memory types might require additional control signals.

746 MEMORY TROUBLESHOOTING

Controlcircuit

CS

Address

R/W

Bi-directionaldata buffer

Cell I/Ocircuitry

Addressrow

select

Addressbuffer

Addresscolumnselect

Storagecell

array

Data

Vcc Gnd

FIGURE 23-2 Diagram of a typical memory IC.


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Memory Package Styles and StructuresUltimately, the memory die is mounted in a package just like any other IC. The completed memory packages can then be soldered to your motherboard or attached to plug-in struc-tures, such as SIMMs, DIMMs, and memory cards. Only four package styles are normallyused for memory devices:

s DIP (Dual In-line Package) This classic IC package is used for through-hole mounting(prior to surface-mount technology). The advantage of DIP ICs is their compatibilitywith IC sockets, which allows ICs to be inserted or removed as required. Unfortu-nately, the long metal pins can bend and break if the IC is inserted or removed incor-rectly. Also, the overall size of the package demands extra space. DIP ICs were used in older PCs (286 and earlier systems) and older VGA/SVGA video boards. DIPs arestill sometimes used on motherboards to provide cache RAM.

s SIP (Single In-line Package) This type of IC package is rarely used todaythere aresimply not enough pins. However, they did make a short appearance with memory de-vices in late-model 286 and early 386 systems, which flirted with proprietary memoryexpansions. I remember NEC using such devices in a 2MB add-on for their 386SX/20 and you needed to add that module before you added even more memory in the form of

proprietary SIMMs. SIPs can be troublesome because they are difficult to find re- placements for, so expect replacement memory modules using them to cost a premium.

s SOJ (Small-Outline J Lead) This is the contemporary package style for surface-mount circuits. The leads protrude from the package like a DIP, but are bent around

just under the package in the form of a j. Sockets for SOJ packages are often used for replaceable memory ICs, such as the BIOS ROM, but most RAM devices are soldered directly to the motherboard as system memory (or a video board as video RAM).SIMMs often use SOJ memory components.

s TSOP (Thin, Small-Outline Package) Like the SOJ, a TSOP is also a surface-mount package style. However, its small, thin body makes TSOP memory ideal for narrowspaces. Expect to find such devices serving as memory in notebook/sub-notebook sys-tems or PCMCIA cards (a.k.a., PC Cards).

ADD-ON MEMORY DEVICES

Memory has always pushed the envelope of IC design. This trend has given us tremen-dous amounts of memory in very small packages, but it also has kept memory relativelyexpensive. Manufacturers responded by providing a minimum amount of memory withthe system, then selling more memory as an add-on optionthis keeps the cost of a basicmachine down and increases profit through add-on sales. As a technician, you should un-derstand the three basic types of add-on memory.

Proprietary add-on modules Once the Intel i286 opened the door for more than1MB of memory, PC makers scrambled to fill the void. However, the rush to more mem-ory resulted in a proliferation of non-standard (and incompatible) memory modules. Eachnew motherboard came with a new add-on memory schemethis invariably led to a greatdeal of confusion among PC users and makers alike. You will likely find proprietarymemory modules in 286 and early 386 systems.

MEMORY PACKAGE STYLES AND STRUCTURES 747

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SIMMs and DIMMs By the time 386 systems took hold in the PC industry, proprietary

memory modules had been largely abandoned in favor of the Memory Module (Fig. 23-3).A SIMM (Single In-line Memory Module) is light, small, and contains a relatively large block of memory, but perhaps the greatest advantage of a SIMM is standardization. Using astandard pin layout, a SIMM from one PC can be installed in any other PC. The 30-pinSIMM (Table 23-1) provides 8 data bits, and generally holds up to 4MB of RAM. The 30-


A 72-pin SIMM

A 168-pin DIMM

FIGURE 23-3 Comparison of SIMMs and DIMMs.

TAB LE 2 3- 1 P IN OU T OF ASTANDARD 30-PINSIMM

PIN NAME DESCRIPTION

1 VCC +5 VDC2 CAS Column address strobe3 DQ0 Data 04 A0 Address 05 A1 Address 16 DQ1 Data 17 A2 Address 28 A3 Address 39 GND Ground

10 DQ2 Data 211 A4 Address 412 A5 Address 513 DQ3 Data 314 A6 Address 615 A7 Address 716 DQ4 Data 417 A8 Address 818 A9 Address 919 A10 Address 1020 DQ5 Data 5


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pin SIMM proved its worth in 386 and early 486 systems, but fell short when providingmore memory to later-model PCs. The 72-pin SIMM (Table 23-2) supplanted the 30-pinversion by providing 32 data bits, and it could hold up to 32MB (or more). Table 23-3 out-lines a variation of the standard 72-pin SIMM highlighting the use of Error-CorrectionCode (ECC) instead of parity.

You might also find such structures referred to as DIMMs (Dual In-Line Memory Mod-ules) . DIMMs appear virtually identical to SIMMs, but they are larger. And where eachelectrical contact on the SIMM is tied together between the front and back, the DIMM keepsfront and back contacts separateeffectively doubling the number of contacts available onthe device. For example, if you look at a 72-pin SIMM, you will see 72 electrical contactson both sides of the device (144 contacts total)but these are tied together, so there are only72 signals (even with 144 contacts). On the other hand, a DIMM keeps the front and back contacts electrically separate (and usually adds some additional pins to keep SIMMs and DIMMs from accidentally being mixed). Table 23-4 outlines a 144-pin DIMM. Today, vir-tually all DIMM versions provide 168 pins (84 pins on each side). DIMMs are appearingin high-end 64-bit data-bus PCs (such as Pentiums and PowerPC RISC workstations). AsPCs move from 64 to 128 bits over the next few years, DIMMs will likely replace SIMMsas the preferred memory-expansion device. Table 23-5 lists the pinout for an unbuffered DRAM DIMM and Table 23-6 presents the pinout for an unbuffered SDRAM DIMM.

Finally, you might see SIMMs and DIMMs referred to as composite or non-compositemodules . These terms are used infrequently to describe the technology level of the memorymodule. For example, a composite module uses older, lower-density memory, so more ICsare required to achieve the required storage capacity. Conversely, a non-composite mod-ule uses newer memory technology, so fewer ICs are needed to reach the same storage ca-

pacity. In other words, if you encounter a high-density SIMM with only a few ICs on it,chances are that the SIMM is non-composite.

MEGABYTES AND MEMORY LAYOUT

Now is a good time to explain the idea of bytes and megabytes. Very simply, a byteis 8 bits (binary 1s and 0s), and a megabyte is one million of those bytes (1,048,576 bytes


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PIN NAME DESCRIPTION

21 WE Write enable22 GND Ground23 DQ6 Data 624 n/c Not connected25 DQ7 Data 726 QP Data parity out27 RAS Row address strobe28 CASP Parity control29 DP Data parity in30 VCC +5 Vdc

TABLE 23-1 PINOUT OF ASTANDARD 30-PINSIMM (CONTINUED)


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TABLE 23-2 PINOUT OF A STANDARD 72-PIN SIMM

PIN NON-PARITY PARITY DESCRIPTION

1 VSS VSS Ground2 DQ0 DQ0 Data 03 DQ18 DQ18 Data 184 DQ1 DQ1 Data 15 DQ19 DQ19 Data 196 DQ2 DQ2 Data 27 DQ20 DQ20 Data 208 DQ3 DQ3 Data 39 DQ21 DQ21 Data 21

10 VCC VCC +5 Vdc11 n/c n/c Not connected12 A0 A0 Address 013 A1 A1 Address 114 A2 A2 Address 215 A3 A3 Address 316 A4 A4 Address 417 A5 A5 Address 518 A6 A6 Address 619 A10 A10 Address 1020 DQ4 DQ4 Data 421 DQ22 DQ22 Data 2222 DQ5 DQ5 Data 523 DQ23 DQ23 Data 2324 DQ6 DQ6 Data 625 DQ24 DQ24 Data 2426 DQ7 DQ7 Data 727 DQ25 DQ25 Data 2528 A7 A7 Address 729 A11 A11 Address 1130 VCC VCC +5 VDC31 A8 A8 Address 832 A9 A9 Address 933 RAS3 RAS3 Row address strobe 334 RAS2 RAS2 Row address strobe 235 n/c PQ26 Parity 26 (3rd)36 n/c PQ8 Parity 8 (1st)

37 n/c PQ17 Parity 26 (3rd)38 n/c PQ35 Parity 35 (4th)39 VSS VSS Ground40 CAS0 CAS0 Column address strobe 041 CAS2 CAS2 Column address strobe 242 CAS3 CAS3 Column address strobe 343 CAS1 CAS1 Column address strobe 1


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PIN NON-PARITY PARITY DESCRIPTION

44 RAS0 RAS0 Row address strobe 045 RAS1 RAS1 Row address strobe 146 n/c n/c Not connected47 WE WE Read/-write48 n/c n/c Not connected49 DQ9 DQ9 Data 950 DQ27 DQ27 Data 2751 DQ10 DQ10 Data 1052 DQ28 DQ28 Data 2853 DQ11 DQ11 Data 1154 DQ29 DQ29 Data 2955 DQ12 DQ12 Data 1256 DQ30 DQ30 Data 3057 DQ13 DQ13 Data 1358 DQ31 DQ31 Data 3159 VCC VCC +5 Vdc60 DQ32 DQ32 Data 3261 DQ14 DQ14 Data 1462 DQ33 DQ33 Data 3363 DQ15 DQ15 Data 1564 DQ34 DQ34 Data 3465 DQ16 DQ16 Data 1666 n/c n/c Not connected67 PD1 PD1 Presence detect 168 PD2 PD2 Presence detect 269 PD3 PD3 Presence detect 370 PD4 PD4 Presence detect 471 n/c n/c Not connected72 VSS VSS Ground

SIZE: (PRESENCE DETECT LINES)

PD2 PD1 SIZE

GND GND 4 or 64MBGND NC 2 or 32MBNC GND 1 or 16MBNC NC 8 MB

ACCESSTIME: (PRESENCE DETECT LINES)

PD4 PD3 ACCESSTIME

GND GND 50, 100 nsGND NC 80 nsNC GND 70 nsNC NC 60 ns

TABLE 23-2 PINOUT OF A STANDARD 72-PIN SIMM(CONTINUED)


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TABLE 23-3 PINOUT OF A 72-PIN ECC SIMM

PIN ECC OPTIMIZED DESCRIPTION

1 VSS VSS Ground2 DQ0 DQ0 Data 03 DQ1 DQ1 Data 14 DQ2 DQ2 Data 25 DQ3 DQ3 Data 36 DQ4 DQ4 Data 47 DQ5 DQ5 Data 58 DQ6 DQ6 Data 69 DQ7 DQ7 Data 7

10 VCC VCC +5 Vdc11 PD5 PD5 Presence detect 512 A0 A0 Address 013 A1 A1 Address 114 A2 A2 Address 215 A3 A3 Address 316 A4 A4 Address 417 A5 A5 Address 518 A6 A6 Address 619 n/c n/c Not connected20 DQ8 DQ8 Data 821 DQ9 DQ9 Data 922 DQ10 DQ10 Data 1023 DQ11 DQ11 Data 1124 DQ12 DQ12 Data 12

25 DQ13 DQ13 Data 1326 DQ14 DQ14 Data 1427 DQ15 DQ15 Data 1528 A7 A7 Address 729 DQ16 DQ16 Data 1630 VCC VCC +5 Vdc31 A8 A8 Address 832 A9 A9 Address 933 n/c n/c Not connected34 RAS1 RAS1 Row address strobe 135 DQ17 DQ17 Data 1736 DQ18 DQ18 Data 1837 DQ19 DQ19 Data 19

38 DQ20 DQ20 Data 2039 VSS VSS Ground40 CAS0 CAS0 Column address strobe 041 A10 A10 Address 1042 A11 A11 Address 1143 CAS1 CAS1 Column address strobe 144 RAS0 RAS0 Row Address Strobe 0


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TABLE 23-4 PINOUT FOR AN OLDER 144-PINSMALL-OUTLINE (SO) DIMM

PIN NORMAL ECC DESCRIPTION

1 VSS VSS Ground2 VSS VSS Ground3 DQ0 DQ0 Data 0

4 DQ32 DQ32 Data 325 DQ1 DQ1 Data 16 DQ33 DQ33 Data 337 DQ2 DQ2 Data 28 DQ34 DQ34 Data 349 DQ3 DQ3 Data 3

10 DQ35 DQ35 Data 35

PIN ECC OPTIMIZED DESCRIPTION

45 RAS1 RAS1 Row address strobe 146 DQ21 DQ21 Data 2147 WE WE Read/-write48 ECC ECC Error-correct ion control49 DQ22 DQ22 Data 2250 DQ23 DQ23 Data 2351 DQ24 DQ24 Data 2452 DQ25 DQ25 Data 2553 DQ26 DQ26 Data 2654 DQ27 DQ27 Data 2755 DQ28 DQ28 Data 2856 DQ29 DQ29 Data 2957 DQ30 DQ30 Data 3058 DQ31 DQ31 Data 3159 VCC VCC +5 Vdc60 DQ32 DQ32 Data 3261 DQ33 DQ33 Data 3362 DQ34 DQ34 Data 3463 DQ35 DQ35 Data 3564 n/c DQ36 Data 3665 n/c DQ37 Data 3766 n/c DQ38 Data 3867 PD1 PD1 Presence detect 168 PD2 PD2 Presence detect 2

69 PD3 PD3 Presence detect 370 PD4 PD4 Presence detect 471 n/c DQ39 Data 3972 VSS VSS Ground

TABLE 23-3 PINOUT OF A 72-PIN ECC SIMM(CONTINUED)


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11 VCC VCC +5 Vdc12 VCC VCC +5 Vdc13 DQ4 DQ4 Data 414 DQ36 DQ36 Data 3615 DQ5 DQ5 Data 516 DQ37 DQ37 Data 3717 DQ6 DQ6 Data 618 DQ38 DQ38 Data 3819 DQ7 DQ7 Data 720 DQ39 DQ39 Data 39

21 VSS VSS Ground22 VSS VSS Ground23 CAS0 CAS0 Column address strobe 024 CAS4 CAS4 Column address strobe 425 CAS1 CAS1 Column address strobe 126 CAS5 CAS5 Column address strobe 527 VCC VCC +5 Vdc28 VCC VCC +5 Vdc29 A0 A0 Address 030 A3 A3 Address 331 A1 A1 Address 132 A4 A4 Address 433 A2 A2 Address 2

34 A5 A5 Address 535 VSS VSS Ground36 VSS VSS Ground37 DQ8 DQ8 Data 838 DQ40 DQ40 Data 4039 DQ9 DQ9 Data 940 DQ41 DQ41 Data 4141 DQ10 DQ10 Data 1042 DQ42 DQ42 Data 4243 DQ11 DQ11 Data 1144 DQ43 DQ43 Data 4345 VCC VCC +5 Vdc46 VCC VCC +5 Vdc47 DQ12 DQ12 Data 1248 DQ44 DQ44 Data 4449 DQ13 DQ13 Data 1350 DQ45 DQ45 Data 4551 DQ14 DQ14 Data 1452 DQ46 DQ46 Data 4653 DQ15 DQ15 Data 1554 DQ47 DQ47 Data 47

TABLE 23-4 PINOUT FOR AN OLDER 144-PINSMALL-OUTLINE (SO) DIMM(CONTINUED)


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55 VSS VSS Ground56 VSS VSS Ground57 n/c CB058 n/c CB459 n/c CB160 n/c CB561 DU DU Dont use62 DU DU Dont use63 VCC VCC +5 Vdc64 VCC VCC +5 Vdc

65 DU DU Dont use66 DU DU Dont use67 WE WE Read/-write68 n/c n/c Not connected69 RAS0 RAS0 Row address strobe 070 n/c n/c Not connected71 RAS1 RAS1 Row address strobe 172 n/c n/c Not connected73 OE OE Output enable74 n/c n/c Not connected75 VSS VSS Ground76 VSS VSS Ground77 n/c CB278 n/c CB679 n/c CB380 n/c CB781 VCC VCC +5 Vdc82 VCC VCC +5 Vdc83 DQ16 DQ16 Data 1684 DQ48 DQ48 Data 4885 DQ17 DQ17 Data 1786 DQ49 DQ49 Data 4987 DQ18 DQ18 Data 1888 DQ50 DQ50 Data 5089 DQ19 DQ19 Data 1990 DQ51 DQ51 Data 5191 VSS VSS Ground

92 VSS VSS Ground93 DQ20 DQ20 Data 2094 DQ52 DQ52 Data 5295 DQ21 DQ21 Data 2196 DQ53 DQ53 Data 5397 DQ22 DQ22 Data 2298 DQ54 DQ54 Data 5499 DQ23 DQ23 Data 23



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100 DQ55 DQ55 Data 55101 VCC VCC +5 Vdc102 VCC VCC +5 Vdc103 A6 A6 Address 6104 A7 A7 Address 7105 A8 A8 Address 8106 A11 A11 Address 11107 VSS VSS Ground108 VSS VSS Ground109 A9 A9 Address 9110 A12 A12 Address 12111 A10 A10 Address 10112 A13 A13 Address 13113 VCC VCC +5 Vdc114 VCC VCC +5 Vdc115 CAS2 CAS2 Column address strobe 2116 CAS6 CAS6 Column address strobe 6117 CAS3 CAS3 Column address strobe 3118 CAS7 CAS7 Column address strobe 7119 VSS VSS Ground120 VSS VSS Ground121 DQ24 DQ24 Data 24122 DQ56 DQ56 Data 56123 DQ25 DQ25 Data 25

124 DQ57 DQ57 Data 57125 DQ26 DQ26 Data 26126 DQ58 DQ58 Data 58127 DQ27 DQ27 Data 27128 DQ59 DQ59 Data 59129 VCC VCC +5 Vdc130 VCC VCC +5 Vdc131 DQ28 DQ28 Data 28132 DQ60 DQ60 Data 60133 DQ29 DQ29 Data 29134 DQ61 DQ61 Data 61135 DQ30 DQ30 Data 30136 DQ62 DQ62 Data 62137 DQ31 DQ31 Data 31138 DQ63 DQ63 Data 63139 VSS VSS Ground140 VSS VSS Ground141 SDA SDA142 SCL SCL143 VCC VCC +5 Vdc144 VCC VCC +5 Vdc



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TABLE 23-5 PINOUT OF A 168-PIN UNBUFFERED DRAM DIMM

PIN NON-PARITY PARITY 72 ECC 80 ECC DESCRIPTION

1 VSS VSS VSS VSS Ground2 DQ0 DQ0 DQ0 DQ0 Data 03 DQ1 DQ1 DQ1 DQ1 Data 14 DQ2 DQ2 DQ2 DQ2 Data 25 DQ3 DQ3 DQ3 DQ3 Data 36 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc7 DQ4 DQ4 DQ4 DQ4 Data 48 DQ5 DQ5 DQ5 DQ5 Data 59 DQ6 DQ6 DQ6 DQ6 Data 6

10 DQ7 DQ7 DQ7 DQ7 Data 711 DQ8 DQ8 DQ8 DQ8 Data 812 VSS VSS VSS VSS Ground13 DQ9 DQ9 DQ9 DQ9 Data 914 DQ10 DQ10 DQ10 DQ10 Data 1015 DQ11 DQ11 DQ11 DQ11 Data 1116 DQ12 DQ12 DQ12 DQ12 Data 1217 DQ13 DQ13 DQ13 DQ13 Data 1318 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc19 DQ14 DQ14 DQ14 DQ14 Data 1420 DQ15 DQ15 DQ15 DQ15 Data 1521 n/c CB0 CB0 CB0 Parity/check-bit input/output 022 n/c CB1 CB1 CB1 Parity/check-bit input/output 123 VSS VSS VSS VSS Ground24 n/c n/c n/c CB8 Parity/check-bit input/output 8

25 n/c n/c n/c CB9 Parity/check-bit input/output 926 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc27 WE0 WE0 WE0 WE0 Read/write input28 CAS0 CAS0 CAS0 CAS0 Column address strobe 029 CAS1 CAS1 CAS1 CAS1 Column address strobe 130 RAS0 RAS0 RAS0 RAS0 Row address strobe 031 OE0 OE0 OE0 OE0 Output enable32 VSS VSS VSS VSS Ground33 A0 A0 A0 A0 Address 034 A2 A2 A2 A2 Address 235 A4 A4 A4 A4 Address 436 A6 A6 A6 A6 Address 637 A8 A8 A8 A8 Address 8

38 A10 A10 A10 A10 Address 1039 A12 A12 A12 A12 Address 1240 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc41 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc42 DU DU DU DU Dont use43 VSS VSS VSS VSS Ground44 OE2 OE2 OE2 OE2 Output enable 2


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45 RAS2 RAS2 RAS2 RAS2 Row address strobe 246 CAS2 CAS2 CAS2 CAS2 Column address strobe 247 CAS3 CAS3 CAS3 CAS3 Column address strobe 348 WE2 WE2 WE2 WE2 Read/write Input 249 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc50 n/c n/c n/c CB10 Parity/check bit input/output 1051 n/c n/c n/c CB11 Parity/check bit input/output 1152 n/c CB2 CB2 CB2 Parity/check bit input/output 253 n/c CB3 CB3 CB3 Parity/check bit input/output 354 VSS VSS VSS VSS Ground55 DQ16 DQ16 DQ16 DQ16 Data 1656 DQ17 DQ17 DQ17 DQ17 Data 1757 DQ18 DQ18 DQ18 DQ18 Data 1858 DQ19 DQ19 DQ19 DQ19 Data 1959 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc60 DQ20 DQ20 DQ20 DQ20 Data 2061 n/c n/c n/c n/c Not connected62 DU DU DU DU Dont use63 n/c n/c n/c n/c Not connected64 VSS VSS VSS VSS Ground65 DQ21 DQ21 DQ21 DQ21 Data 2166 DQ22 DQ22 DQ22 DQ22 Data 2267 DQ23 DQ23 DQ23 DQ23 Data 2368 VSS VSS VSS VSS Ground

69 DQ24 DQ24 DQ24 DQ24 Data 2470 DQ25 DQ25 DQ25 DQ25 Data 2571 DQ26 DQ26 DQ26 DQ26 Data 2672 DQ27 DQ27 DQ27 DQ27 Data 2773 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc74 DQ28 DQ28 DQ28 DQ28 Data 2875 DQ29 DQ29 DQ29 DQ29 Data 2976 DQ30 DQ30 DQ30 DQ30 Data 3077 DQ31 DQ31 DQ31 DQ31 Data 3178 VSS VSS VSS VSS Ground79 n/c n/c n/c n/c Not connected80 n/c n/c n/c n/c Not connected81 n/c n/c n/c n/c Not connected

82 SDA SDA SDA SDA Serial data83 SCL SCL SCL SCL Serial clock84 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc85 VSS VSS VSS VSS Ground86 DQ32 DQ32 DQ32 DQ32 Data 3287 DQ33 DQ33 DQ33 DQ33 Data 3388 DQ34 DQ34 DQ34 DQ34 Data 34

TABLE 23-5 PINOUT OF A 168-PIN UNBUFFERED DRAM DIMM(CONTINUED)


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89 DQ35 DQ35 DQ35 DQ35 Data 3590 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc91 DQ36 DQ36 DQ36 DQ36 Data 3692 DQ37 DQ37 DQ37 DQ37 Data 3793 DQ38 DQ38 DQ38 DQ38 Data 3894 DQ39 DQ39 DQ39 DQ39 Data 3995 DQ40 DQ40 DQ40 DQ40 Data 4096 VSS VSS VSS VSS Ground97 DQ41 DQ41 DQ41 DQ41 Data 4198 DQ42 DQ42 DQ42 DQ42 Data 4299 DQ43 DQ43 DQ43 DQ43 Data 43

100 DQ44 DQ44 DQ44 DQ44 Data 44101 DQ45 DQ45 DQ45 DQ45 Data 45102 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc103 DQ46 DQ46 DQ46 DQ46 Data 46104 DQ47 DQ47 DQ47 DQ47 Data 47105 n/c CB4 CB4 CB4 Parity/check bit input/output 4106 n/c CB5 CB5 CB5 Parity/check bit input/output 5107 VSS VSS VSS VSS Ground108 n/c n/c n/c CB12 Parity/check bit input/output 12109 n/c n/c n/c CB13 Parity/check bit input/output 13110 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc111 DU DU DU DU Dont use112 CAS4 CAS4 CAS4 CAS4 Column address strobe 4

113 CAS5 CAS5 CAS5 CAS5 Column address strobe 5114 RAS1 RAS1 RAS1 RAS1 Row address strobe 1115 DU DU DU DU Dont use116 VSS VSS VSS VSS Ground117 A1 A1 A1 A1 Address 1118 A3 A3 A3 A3 Address 3119 A5 A5 A5 A5 Address 5120 A7 A7 A7 A7 Address 7121 A9 A9 A9 A9 Address 9122 A11 A11 A11 A11 Address 11123 A13 A13 A13 A13 Address 13124 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc125 DU DU DU DU Dont use

126 DU DU DU DU Dont use127 VSS VSS VSS VSS Ground128 DU DU DU DU Dont use129 RAS3 RAS3 RAS3 RAS3 Column address strobe 3130 CAS6 CAS6 CAS6 CAS6 Column address strobe 6131 CAS7 CAS7 CAS7 CAS7 Column address strobe 7132 DU DU DU DU Dont use



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133 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc134 n/c n/c n/c CB14 Parity/check bit input/output 14135 n/c n/c n/c CB15 Parity/check bit input/output 15136 n/c CB6 CB6 CB6 Parity/check bit input/output 6137 n/c CB7 CB7 CB7 Parity/check bit input/output 7138 VSS VSS VSS VSS Ground139 DQ48 DQ48 DQ48 DQ48 Data 48140 DQ49 DQ49 DQ49 DQ49 Data 49141 DQ50 DQ50 DQ50 DQ50 Data 50142 DQ51 DQ51 DQ51 DQ51 Data 51143 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc144 DQ52 DQ52 DQ52 DQ52 Data 52145 n/c n/c n/c n/c Not connected146 DU DU DU DU Dont use147 n/c n/c n/c n/c Not connected148 VSS VSS VSS VSS Ground149 DQ53 DQ53 DQ53 DQ53 Data 53150 DQ54 DQ54 DQ54 DQ54 Data 54151 DQ55 DQ55 DQ55 DQ55 Data 55152 VSS VSS VSS VSS Ground153 DQ56 DQ56 DQ56 DQ56 Data 56154 DQ57 DQ57 DQ57 DQ57 Data 57155 DQ58 DQ58 DQ58 DQ58 Data 58156 DQ59 DQ59 DQ59 DQ59 Data 59

157 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc158 DQ60 DQ60 DQ60 DQ60 Data 60159 DQ61 DQ61 DQ61 DQ61 Data 61160 DQ62 DQ62 DQ62 DQ62 Data 62161 DQ63 DQ63 DQ63 DQ63 Data 63162 VSS VSS VSS VSS Ground163 CK3 CK3 CK3 CK3164 n/c n/c n/c n/c Not connected165 SA0 SA0 SA0 SA0 Serial address 0166 SA1 SA1 SA1 SA1 Serial address 1167 SA2 SA2 SA2 SA2 Serial address 2168 VCC VCC VCC VCC +5 Vdc or +3.3 Vdc


TABLE 23-6 PINOUT OF A 168-PIN UNBUFFERED SDRAM DIMM

PIN NON-PARITY 72 ECC 80 ECC DESCRIPTION

1 VSS VSS VSS Ground2 DQ0 DQ0 DQ0 Data 03 DQ1 DQ1 DQ1 Data 1


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TABLE 23-6 PINOUT OF A 168-PIN UNBUFFERED SDRAM DIMM(CONTINUED)

4 DQ2 DQ2 DQ2 Data 25 DQ3 DQ3 DQ3 Data 36 VDD VDD VDD +5 Vdc or +3.3 Vdc7 DQ4 DQ4 DQ4 Data 48 DQ5 DQ5 DQ5 Data 59 DQ6 DQ6 DQ6 Data 6

10 DQ7 DQ7 DQ7 Data 711 DQ8 DQ8 DQ8 Data 812 VSS VSS VSS Ground13 DQ9 DQ9 DQ9 Data 914 DQ10 DQ10 DQ10 Data 10

15 DQ11 DQ11 DQ11 Data 1116 DQ12 DQ12 DQ12 Data 1217 DQ13 DQ13 DQ13 Data 1318 VDD VDD VDD +5 Vdc or +3.3 Vdc19 DQ14 DQ14 DQ14 Data 1420 DQ15 DQ15 DQ15 Data 1521 n/c CB0 CB0 Parity/check-bit input/output 022 n/c CB1 CB1 Parity/check-bit input/output 123 VSS VSS VSS Ground24 n/c n/c CB8 Parity/check-bit input/output 825 n/c n/c CB9 Parity/check-bit input/output 926 VDD VDD VDD +5 Vdc or +3.3 Vdc27 WE WE WE Read/-write

28 DQMB0 DQMB0 DQMB0 Byte mask signal 029 DQMB1 DQMB1 DQMB1 Byte mask signal 130 S0 S0 S0 Chip select31 DU DU DU Dont use32 VSS VSS VSS Ground33 A0 A0 A0 Address 034 A2 A2 A2 Address 235 A4 A4 A4 Address 436 A6 A6 A6 Address 637 A8 A8 A8 Address 838 A10/AP A10/AP A10/AP Address 1039 BA1 BA1 BA1 Bank address 140 VDD VDD VDD +5 Vdc or +3.3 Vdc41 VDD VDD VDD +5 Vdc or +3.3 Vdc42 CK0 CK0 CK0 Clock signal 043 VSS VSS VSS Ground44 DU DU DU Dont use45 S2 S2 S2 Chip select 246 DQMB2 DQMB2 DQMB2 Byte mask signal 247 DQMB3 DQMB3 DQMB3 Byte mask signal 3


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48 DU DU DU Dont use49 VDD VDD VDD +5 Vdc or +3.3 Vdc50 n/c n/c CB10 Parity/check-bit input/output 1051 n/c n/c CB11 Parity/check-bit input/output 1152 n/c CB2 CB2 Parity/check-bit input/output 253 n/c CB3 CB3 Parity/check-bit input/output 354 VSS VSS VSS Ground55 DQ16 DQ16 DQ16 Data 1656 DQ17 DQ17 DQ17 Data 1757 DQ18 DQ18 DQ18 Data 1858 DQ19 DQ19 DQ19 Data 1959 VDD VDD VDD +5 Vdc or +3.3 Vdc60 DQ20 DQ20 DQ20 Data 2061 n/c n/c n/c Not connected62 Vref,NC Vref,NC Vref,NC63 CKE1 CKE1 CKE1 Clock enable signal 164 VSS VSS VSS Ground65 DQ21 DQ21 DQ21 Data 2166 DQ22 DQ22 DQ22 Data 2267 DQ23 DQ23 DQ23 Data 2368 VSS VSS VSS Ground69 DQ24 DQ24 DQ24 Data 2470 DQ25 DQ25 DQ25 Data 2571 DQ26 DQ26 DQ26 Data 26

72 DQ27 DQ27 DQ27 Data 2773 VDD VDD VDD +5 Vdc or +3.3 Vdc74 DQ28 DQ28 DQ28 Data 2875 DQ29 DQ29 DQ29 Data 2976 DQ30 DQ30 DQ30 Data 3077 DQ31 DQ31 DQ31 Data 3178 VSS VSS VSS Ground79 CK2 CK2 CK2 Clock signal 280 n/c n/c n/c Not connected81 n/c n/c n/c Not connected82S DAS DAS DAS Serial data83S CLS CLS CLS Serial clock84 VDD VDD VDD +5 Vdc or +3.3 Vdc

85 VSS VSS VSS Ground86 DQ32 DQ32 DQ32 Data 3287 DQ33 DQ33 DQ33 Data 3388 DQ34 DQ34 DQ34 Data 3489 DQ35 DQ35 DQ35 Data 3590 VDD VDD VDD +5 Vdc or +3.3 Vdc91 DQ36 DQ36 DQ36 Data 3692 DQ37 DQ37 DQ37 Data 37



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93 DQ38 DQ38 DQ38 Data 3894 DQ39 DQ39 DQ39 Data 3995 DQ40 DQ40 DQ40 Data 4096 VSS VSS VSS Ground97 DQ41 DQ41 DQ41 Data 4198 DQ42 DQ42 DQ42 Data 4299 DQ43 DQ43 DQ43 Data 43

100 DQ44 DQ44 DQ44 Data 44101 DQ45 DQ45 DQ45 Data 45102 VDD VDD VDD +5 Vdc or +3.3 Vdc103 DQ46 DQ46 DQ46 Data 46104 DQ47 DQ47 DQ47 Data 47105 n/c CB4 CB4 Parity/check-bit input/output 4106 n/c CB5 CB5 Parity/check-bit input/output 5107 VSS VSS VSS Ground108 n/c n/c CB12 Parity/check-bit input/output 12109 n/c n/c CB13 Parity/check-bit input/output 13110 VDD VDD VDD +5 Vdc or +3.3 Vdc111 CAS CAS CAS Column address strobe112 DQMB4 DQMB4 DQMB4 Byte mask signal 4113 DQMB5 DQMB5 DQMB5 Byte mask signal 5114 S1 S1 S1 Chip select 1115 RAS RAS RAS Row address strobe116 VSS VSS VSS Ground

117 A1 A1 A1 Address 1118 A3 A3 A3 Address 3119 A5 A5 A5 Address 5120 A7 A7 A7 Address 7121 A9 A9 A9 Address 9122 BA0 BA0 BA0 Bank address 0123 A11 A11 A11 Address 11124 VDD VDD VDD +5 Vdc or +3.3 Vdc125 CK1 CK1 CK1 Clock signal 1126 A12 A12 A12 Address 12127 VSS VSS VSS Ground128 CKE0 CKE0 CKE0 Clock enable signal 0129 S3 S3 S3 Chip Select 3

130 DQMB6 DQMB6 DQMB6 Byte mask signal 6131 DQMB7 DQMB7 DQMB7 Byte mask signal 7132 A13 A13 A13 Address 13133 VDD VDD VDD +5 Vdc or +3.3 Vdc134 n/c n/c CB14 Parity/check-bit input/output 14135 n/c n/c CB15 Parity/check-bit input/output 15136 n/c CB6 CB6 Parity/check-bit input/output 6137 n/c CB7 CB7 Parity/check-bit input/output 7



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to be exactbut manufacturers often round down to the nearest million or so). The ideaof megabytes (MB) is important when measuring memory in your PC. For example, if aSIMM is laid out as 1M by 8 bits, it has 1MB. If the SIMM is laid out as 4M by 8 bits, ithas 4MB. Unfortunately, memory has not been laid out as 8 bits since the IBM XT.

More practical memory layouts involve 32-bit memory (for 486 and OverDrive processors) or 64-bit memory (for Pentium processors). When memory is wider thanone byte, it is still measured in MB. For example, a 1M 32-bit (4 bytes) SIMM would

be 4MB (that is, the capacity of the device is 4MB), and a 4M 32-bit SIMM would be16MB. So when you go shopping for an 8MB 72-pin SIMM, chances are that youregetting a 2M 32-bit memory module. Table 23-7 provides you with an index to helpidentify common 72-pin SIMMs. You can see the relationship between memory layoutand overall capacity.



138 VSS VSS VSS Ground139 DQ48 DQ48 DQ48 Data 48140 DQ49 DQ49 DQ49 Data 49141 DQ50 DQ50 DQ50 Data 50142 DQ51 DQ51 DQ51 Data 51143 VDD VDD VDD +5 Vdc or +3.3 Vdc144 DQ52 DQ52 DQ52 Data 52145 n/c n/c n/c Not connected146 Vref,NC Vref,NC Vref,NC147 n/c n/c n/c Not connected148 VSS VSS VSS Ground149 DQ53 DQ53 DQ53 Data 53150 DQ54 DQ54 DQ54 Data 54151 DQ55 DQ55 DQ55 Data 55152 VSS VSS VSS Ground153 DQ56 DQ56 DQ56 Data 56154 DQ57 DQ57 DQ57 Data 57155 DQ58 DQ58 DQ58 Data 58156 DQ59 DQ59 DQ59 Data 59157 VDD VDD VDD +5 Vdc or +3.3 Vdc158 DQ60 DQ60 DQ60 Data 60159 DQ61 DQ61 DQ61 Data 61160 DQ62 DQ62 DQ62 Data 62161 DQ63 DQ63 DQ63 Data 63

162 VSS VSS VSS Ground163 CK3 CK3 CK3 Clock signal 3164 n/c n/c n/c Not connected165 SA0 SA0 SA0 Serial address 0166 SA1 SA1 SA1 Serial address 1167 SA2 SA2 SA2 Serial address 2168 VDD VDD VDD +5 Vdc or +3.3 Vdc



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Memory OrganizationThe memory in your computer represents the result of evolution over several computer generations. Memory operation and handling is taken care of by your systems micro-

processor. As CPUs improved, memory-handling capabilities have improved as well. To-days microprocessors, such as the Intel Pentium or Pentium Pro, are capable of addressingmore than 4GB of system memorywell beyond the levels of contemporary software ap-

plications. Unfortunately, the early PCs were not nearly so powerful. Older PCs could only address 1MB of memory because of the limitations of the 8088 microprocessor.

Because backward compatibility is so important to computer users, the drawbacks and limitations of older systems had to be carried forward into newer computers, instead of be-ing eliminated. Newer systems overcome their inherent limitations by adding differenttypes of memory, along with the hardware and software to access the memory. This partof the chapter describes the typical classifications of computer memory: conventional, ex-

tended, and expanded memory. This chapter also describes high memory concepts. No-tice that these memory types have nothing to do with the actual ICs in your system, but theway in which software uses the memory.

CONVENTIONAL MEMORY

Conventional memory is the traditional 640KB assigned to the DOS Memory Area(10000h to 9FFFFh, as shown in Fig. 23-4). The original PCs used microprocessors that

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TABLE 23-7 72-PIN SIMM IDENTIFICATION GUIDELINES

CONFIGURATION DESCRIPTION CAPACITY TYPE

36 chips: (36) 16 1 SOJs Parity SIMM, usually double sided 64MB 16 36or 12 chips: (8) 16 4, (4) 16 1 SOJs24 chips: (16) 4 4 SOJs, (8) 4 1 SOJs Parity SIMM, usually double sided 32MB 8 3612 chips: (8) 4 4 SOJs, (4) 4 1 SOJs Parity SIMM, double or single sided 16MB 4 3624 chips: (16) 1 4 SOJs, (8) 1 1 SOJs Parity SIMM, usually double sided 8MB 2 3612 chips: (8) 1 4 SOJs, (4) 1 1 SOJs Parity SIMM, double or single sided 4MB 1 364 chips: (4) 256 18 SOJs Parity SIMM, usually double sided 2MB 512 36or 24 chips: (16) 256 4 SOJs,& (8) 256 1 PLCC12 chips: (8) 256 4 SOJs, Parity SIMM 1MB 256 36& (4) 256 1 PLCC

32 chips: (32) 16

1 SOJs Non-parity SIMM, usually double sided 64MB 16

32or 8 chips: (8) 16 4 SOJs16 chips: (16) 4 4 SOJs Non-parity SIMM, usually double sided 32MB 8 328 chips: (8) 4 4 SOJs Non-parity SIMM, usually single sided 16MB 4 3216 chips: (16) 1 4 SOJs Non-parity SIMM, usually double sided 8MB 2 32or 4 chips: (4) 1 16 SOJs8 chips: (8) 1 4 SOJs Non-parity SIMM, usually single sided 4MB 1 32or 2 chips: (2) 1 16 SOJs16 chips: (16) 256 4 SOJs Non-parity SIMM, usually double sided 2MB 512 328 chips: (8) 256 4 SOJs Non-parity SIMM 1MB 256 32


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could only address 1MB of memory (called real-mode memory or base memory ). Out of that 1MB, portions of the memory must be set aside for basic system functions. BIOScode, video memory, interrupt vectors, and BIOS data are only some of the areas that re-quire reserved memory. The remaining 640KB became available to load and run your ap-

plication, which can be any combination of executable code and data. The original PConly provided 512KB for the DOS program area, but computer designers quickly learned that another 128KB could be added to the DOS area while still retaining enough memoryfor overhead functions, so 512KB became 640KB.

Every IBM-compatible PC still provides a 640KB base memory range, and most DOSapplication programs continue to fit within that limit to ensure backward compatibility toolder systems. However, the drawbacks to the 8088 CPU were soon apparent. Morememory had to added to the computer for its evolution to continue. Yet, memory had to

be added in a way that did not interfere with the conventional memory area. Table 23-8 il-lustrates a comprehensive memory map for a typical PC.

EXTENDED MEMORY

The 80286 introduced in IBMs PC/AT was envisioned to overcome the 640KB barrier byincorporating a protected mode of addressing. The 80286 can address up to 16MB of mem-ory in protected mode, and its successors (the 80386 and later) can handle 4GB of protected-


1024Kb FFFFFh

System ROM

System ROM

Optional/user ROM

Video RAM

User area

System/user area

User area

Optional/user ROM

Video RAM

User area

User area

User area

640Kb

0Kb

F0000h

E0000h

D0000h

C0000h

B0000h

A0000h

90000h

70000h

50000h

30000h

10000h

00000h

FIGURE 23-4 Conventional and upper memory ina typical PC.


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TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC

ADDRESSRANGE (H) DESCRIPTION

00000003FF Interrupt Vector Table (256 double words):00000 INT 00H Divide-by-zero interrupt handler00004 INT 01H Single-step interrupt handler00008 INT 02H Non-maskable interrupt (memory parity or I/O error)0000C INT 03H Breakpoint00010 INT 04H Arithmetic overflow interrupt handler00014 INT 05H Print screen00018 INT 06H Reserved0001C INT 07H Reserved00020 INT 08H Timer-interrupt routine (18.21590 /sec) IRQ000024 INT 09H Keyboard service routine IRQ100028 INT 0AH VGA retrace (and AT slave interrupts) IRQ20002C INT 0BH Serial device 2 service routine IRQ300030 INT 0CH Serial device 1 service routine IRQ400034 INT 0DH Hard-disk interrupt routine IRQ500038 INT 0EH Diskette interrupt routine IRQ60003C INT 0FH Parallel-port service routine IRQ700040 INT 10H Video services00044 INT 11H Equipment check00048 INT 12H Memory-size check0004C INT 13H Diskette and hard disk I/O00050 INT 14H RS-232 service call

00054 INT 15H System services calls00058 INT 16H Keyboard call0005C INT 17H Printer I/O call00060 INT 18H Basic ROM entry (startup)00064 INT 19H Boot loader: implement system (IPL) from disk00068 INT 1AH Time-of-day call0006C INT 1BH Keyboard break address00070 INT 1CH User timer interrupt00074 INT 1DH Monitor ROMfor 6845 video inititialization00078 INT 1EH Disk-control table pointer0007C INT 1FH Alphanumeric character pattern table pointer00080 INT 20H DOS terminate program00084 INT 21H Microsoft DOS function calls

00088 INT 22H DOS terminate address (not a callable function)0008C INT 23H DOS Ctrl-break exit address (not a callable funct ion)00090 INT 24H DOS fatal-error exit address (not a callable function)00094 INT 25H DOS absolute disk read00098 INT 26H DOS absolute disk write0009C INT 27H Terminate and stay resident (control passes to COMMAND.COM)000A0 INT 28H Idle loop, spooler waiting; issued by DOS when waiting


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TABLE 23-8 REAL-MODE MEMORY MAP OF A TYPICAL PC (CONTINUED)


000A4 INT 29H CON device raw output handler000A8 INT 2AH 3.x Network communications000AC INT 2BH-2DH reserved for DOS000B8 INT 2EH Execute DOS command (undocumented)000BC INT 2FH Print spool control (Multiplex Interrupt)000C0 INT 30H-31H Internal use000C8 INT 32H Reserved for DOS000CC INT 33H Microsoft mouse-driver calls000D0 INT 34H-3EH Reserved for DOS000FC INT 3FH U sed by LINK to manage overlay segments00100 INT 40H Fixed-disk/floppy-disk handler00104 INT 41H ROM pointer; fixed-disk parameters00108 INT 42H EGA: video vector screen BIOS entry0010C INT 43H EGA: Initialization parameters00100 INT 44H EGA: Graphics-character patterns00114 INT 45H Reserved00118 INT 46H AT: Pointer to second fixed disk parameters0011C INT 47H Reserved00120 INT 48H P Cjr cordless-keyboard Xlat routine00124 INT 49H PCjr non-keyboard scan-code Xlat table00128 INT 4AH AT, PS/2 user alarm routine0012C INT 4BH-4FH Reserved00140 INT 50H Periodic alarm interrupt from timer00144 INT 51H-59H Reserved00168 INT 5AH Cluster adapter BIOS-entry address0016C INT 5BH Cluster boot00170 INT 5CH NETBIOS entry point00174 INT 5DH-5FH Reserved00180 INT 60H-66H R eserved for user program interrupts0019C INT 67H EMM: Expanded memory manager routines001A0 INT 68H-6BH Unused001B0 INT 6CH System-resume vector001B4 INT 6DH-6FH Unused001C0 INT 70H Real-time clock IRQ8001C4 INT 71H LAN adapter IRQ9001C8 INT 72H Reserved IRQ10001CC INT 73H Reserved IRQ11001D0 INT 74H Mouse interrupt IRQ12001D4 INT 75H 80287 NMI Error IRQ13001D8 INT 76H Fixed disk controller IRQ14001DC INT 77H Reserved IRQ15001E0 INT 78H-7FH Unused


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00200 INT 80H-85H Reserved for BASIC00218 INT 86H AT: NetBIOS relocated INT 18H0021C INT 87H-F0H R eserved for BASIC interpreter003C4 INT F1H-FFH Reserved for user program interrupts003FF Used for power-on and initial boot stack

00400-004FF BIOS Data Area:00400 COM1: to COM4: port addresses00408 LPT1: to LPT3: port addresses0040E LPT4: address except PS/2 reserved00410 Equipment flag

bits: 1514 Number of LPTs attached13 Internal modem (CVT) or reserved12 Joystick119 Number of COMs8 Unused (jr: DMS chip present)76 Number of disk drives5 1 = 80 25 0 = 40 25 screen4 1 = color 0 = monochrome32 00 = 64K chips; 11 = 256K chips (PC,XT,AT)1 Math coprocessor installed0 IPL disk installed

00412 Init. flag; reserved (CVT self-test status)00413 Memory size in K bytes00415 Reserved00416 Reserved00417 Keyboard monitor flag bytes 0 and 1:

bit: 7 ins lock 7 ins pressed6 caps lock 6 caps pressed5 num lock 5 num lock pressed4 scroll lock 4 scroll pressed3 alt pressed 3 pause locked2 crtl pressed 2 sysreq pressed1 alt pressed

00419 Alternate keypad entry0041A Keyboard buffer head pointer0041C Keyboard buffer tail pointer0041E Keyboard buffer0043E Drive recalibration status

bit: 7 Interrupt flag64 Reserved3 Recalibrate drive 32 Recalibrate drive 21 Recalibrate drive 10 Recalibrate drive 0


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0043F Motor statusbit: 7 Currently reading or writing

6 Reserved54 00 Drive 0 Selected

01 Drive 1 Selected10 Drive 2 Selected11 Drive 3 Selected

3-0 Drive 3-0 motor on status00440 Motor-control time-out counter00441 Diskette Status Return Code

00H No error

01H Invalid diskette drive parameter02H Address mark not found03H Write-protect error04H Requested sector not found05H Reserved06H Diskette change line active07H Reserved08H DMA overrun on operation09H Attempt to DMA across a 64K boundary0AH Reserved0BH Reserved0CH Media type not found0DH Reserved0EH Reserved0FH Reserved10H CRC error on diskette read20H General controller failure40H Seek operation failed80H Diskette drive not ready

00442 Diskette drive controller status bytes (NEC)00449 CRT_MODE

bit: 7 Text 80 25 mono on mono card6 Graphics 640 200 mono on color card5 Graphics 320 200 mono on color card4 Graphics 320 200 on color card3 Text 80 25 color2 Text 80 25 mono on color1 Text 40 25 color0 Text 40 25 mono on color card

0044A CRT_COLS Number of columns (80)0044C CRT_LEN Length of regen buffer in bytes

0044E CRT_START Starting address in regen buffer00450 Cursor position on each of eight pages00460 CURSOR_MODE top-bottom line of cursor (cursor type)00462 ACTIVE_PAGE index00463 ADDR_6845 Base address for 6845 display chip

3B4H for monochrome3D4H for color



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00465 CRT_MODE_SETTING for 3 x 8 register3B8H for MDA3D8H for CGA

00466 CRT_PALLETTE setting register (3D9H) on color card00467 Temporary storage for SS:SP during shutdown0046B Flag to indicate interrupt0046C Timer counter (timer low, timer high words)00470 Timer overflow (24-hour roll-over flag byte)00471 Break key state (bit 7 = 1 if break key pressed)00472 Reset flag word:

1234 bypass memory test4321 preserve memory5678 system suspend9ABC manufacturing testABCD system POST loop (CVT)

00474 Hard-disk status or reserved for ESDI Adapter/A00H No error01H Invalid function request02H Address mark not found03H Write protect error04H Requested sector not found05H Reset failed06H Reserved07H Drive parameter activity failed08H DMA overrun on operation09H Data boundary error0AH Bad sector flag detected0BH Bad track detected0CH Reserved0DH Invalid number of sectors on format0EH Control data address mark detected0FH DMA arbitration level out of range10H Uncorrectable ECC or CRC error20H General controller failure40H Seek operation failed80H Time outAAH Drive not readyBBH Undefined error occurredCCH Write fault on selected driveE0H Status error/error register 0FFH Sense operation failed

00475 Number of hard-disk drives00476 Fixed disk-drive control byte (PC XT)00477 Fixed disk-drive controller port (PC XT)00478 LPT1: to LPT4: time-out byte values (PS/2 has no LPT4:)0047C COM1: to COM4: timeout byte values00480 Keyboard buffer start pointer (word)00482 Keyboard buffer end pointer (word)



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00484 ROWS video character Rows - 100485 POINTS Height of character matrix-bytes per character00487 INFO byte:

bit: 7 Video mode number (of INT 10H funct.0)65 Size of video RAM 0064K

10192K01128K11256K

4 reserved3 (1) video subsystem is inactive2 reserved

1 (1) video subsystem on monochrome0 (1) alphanumeric cursor emulation enabled00488 INFO_3 byte:

bit: 7 Input FEAT1 (bit 6 of ISR0 (Input Status Reg. )6 Input FEAT1 (bit 5 of ISR0)5 Input FEAT0 (bit 6 of ISR0)4 Input FEAT0 (bit 5 of ISR0)3 EGA config. switch 4 (1=off)2 EGA config. switch 31 EGA config. switch 20 EGA config. switch 1

00489 Flagsbit: 7 bit 4 Alphanumeric scan lines:

00 350-line mode01 40010 20011 Reserved

6 (1) Display switching enabled5 Reserved3 (1) Default palett loading is disabled2 (1) Using monochrome monitor1 (1) Gray scale is enabled0 (1) VGA is active

0048A DCC Display combination code table index (VGA)0048B Media control

bit: 76 Last diskette drive data rate selected00500Kb per second01300Kb per second10250Kb per second11reserved

54 Last diskette drive step rate selected30 reserved

0048C Hard-disk status register0048D Hard-disk error register0048E Hard-disk interrupt control flag0048F Combination hard disk/floppy card (bit 0=1)00490 Drive-0 media-state byte00491 Drive-1 media-state byte



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00492 Drive 2 media state byte00493 Drive 3 media state byte

bit : 76 Disket te drive date rate00500Kb per second01300Kb per second10250Kb per second11Reserved

5 Double stepping required4 Media established3 Reserved20 Drive/media s tate

000 360Kb diskette/360Kb drive not established001 360Kb diskette/1.2Mb drive not established010 1.2Mb diskette/1.2Mb drive not established011 360Kb diskette/360Kb drive established100 360Kb diskette/1.2Mb drive established101 1.2Mb diskette/1.2Mb drive established110 Reserved111 None of the above

00494 Drive 0 track currently selected00495 Drive 1 track currently selected00496 Keyboard mode state and type flags

bit: 7 Read ID in progress6 Last character was first ID character5 Force NumLock i f read ID and KBX4 101/102 keyboard installed3 Right Alt key pressed2 Right Ctrl key pressed1 Last code was E0 hidden code0 Last code was E1 hidden code

00497 Keyboard LED flagsbit: 7 Keyboard transmit error flag

6 Mode-indicator update5 Cancel receive flag4 Acknowledgment received3 = 0 reserved2-0 Keyboard LED state bits

00498 Offset address to user wait complete flag0049A Segment to user wait complete flag0049C User wait count, microseconds low word0049E User wait count, microseconds high word

004A0 Wait active flagbit: 7 Wait-time elapse and post flag61 Reserved

004A1 LANA DMA channel flags004A2 LANA 0 status004A3 LANA 1 status004A4 Saved hardfile interrupt vector



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004A8 BIOS video save table and overrides004AC Reserved004B4 Keyboard NMI control flags (CVT)004B5 Keyboard break-pending flags (CVT)004B9 Port-60 single-byte queue (CVT)004BA Scan code of last key (CVT)004BB Pointer-to-NMI buffer head (CVT)004BC Pointer-to-NMI buffer tail (CVT)004BD NMI scan-code buffer (CVT)

004CE Day counter (CVT and after)004D0 Reserved004F0 Application program communication area

00500005FF DOS Data Area:00500 Print-screen status flag

1 = printer active0FFH = printer fault

00501 Reserved for BASIC and POST work area00504 Single-drive mode-status byte

0 = drive A1 = drive B

00505 Reserved POST work area00510 Reserved for BASIC

0050F BASIC ShellFlag = 2 if current shell00510 BASIC segment address storage set with DEF SEG00512 BASIC int 1Ch clock-interrupt vector00516 BASIC int 23h ctrl-break interrupt vector0051A BASIC int 24h disk-error interrupt vector0051B BASIC dynamic storage00520 DOS dynamic storage00522 Used by DOS for diskette initialization00530 Used by MODE command00534 Reserved for DOS data00600 Reserved for DOS00700 I/O drivers from xIO.SYS

008470FFFF xIO.SYS IRET for interrupts 1, 3, and 0FH during POSTMS-DOS kernel from xDOS.SYS: Interrupt handlers and routinesMS-DOS disk-buffer cache, FCBs and installable device driversMCB (Memory control block, 16 bytes, paragraph aligned)Start of transient program



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mode memory. Today, virtually all computer systems provide several MB of extended memory. Besides an advanced microprocessor, another key element for extended memoryis software. Memory-management software must be loaded in advance for the computer to access its extended memory. Microsofts DOS 5.0 provides an extended memory man-ager utility (HIMEM.SYS), but other off-the-shelf utilities are available as well.

Unfortunately, DOS itself cannot use extended memory. You might fill the extended memory with data, but the executable code comprising the program remains limited to theoriginal 640KB of base memory. Some programs written with DOS extenders can over-come the 640KB limit, but the additional code needed for the extenders can make such

programs a bit clunky. A DOS extender is basically a software module containing its ownmemory-management code, which is compiled into the final application program.

The DOS extender loads a program in real-mode memory. After the program is loaded,it switches program control to the protected-mode memory. When the program in protected mode needs to execute a DOS (real mode) function, the DOS extender converts protected-mode addresses into real-mode addresses, copies any necessary program data from pro-tected to real-mode locations, switches the CPU to real-mode addressing, and carries out thefunction. The DOS extender then copies any results (if necessary) back to protected-modeaddresses, switches the system to protected-mode once again, and the program continues to


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100009FFFF User Data Area (programs and data)A0000AFFFF Start of EGA and VGA graphics-display RAM modes 0Dh and aboveB0000B3FFF Start of MDPA and Hercules graphics-display RAMB4000B7FFF Reserved for graphics-display RAMB8000BBFFF Start of CGA color graphics-display RAMBC000BFFFF Reserved for graphics-display RAMC0000C3FFF EGA BIOS ROMC4000C5FFF Video-adapter ROM spaceC6000C63FF 256 bytes of PGA communication area

C6400C7FFF Last 7Kb of video adapter ROM spaceC8000CBFFF 16K of hard-disk BIOS adapter ROM spaceCC000CFFFFD0000D7FFF 32K cluster-adapter BIOS ROMD8000DBFFFDC000DFFFF Last 16Kb of adapter ROM spaceE0000EFFFF 64K expansion ROM space (AT, PS/2)F0000F3FFF System-monitor ROMF4000F7FFF System-expansion ROMsF8000FBFFFFC000FEFFF BIOS ROM, BASIC, and simple BIOSFF000FFFEF System ROMFFFF0FFFF3 Hardware boot far jump vector



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run. This back-and-forth conversion overhead results in less-than-optimum performance,

compared to strictly real-mode programs or true protected-mode programs.With multiple megabytes of extended memory typically available, it is possible (but un-likely) that any one program will utilize all of the extended memory. Multiple programsthat use extended memory must not attempt to utilize the same memory locations. If con-flicts occur, a catastrophic system crash is almost inevitable. To prevent conflicts in ex-tended memory, memory-manager software can make use of three major industrystandards: the Extended Memory Specification (XMS) , the Virtual Control Program Inter-

face (VCPI) , or the DOS Protected-Mode Interface (DPMI) . This chapter does not detailthese standards, but you should know where they are used.

EXPANDED MEMORY

Expanded memory is another popular technique used to overcome the traditional 640KB limit

of real-mode addressing. Expanded memory uses the same physical RAM chips, but dif-fers from extended memory in the way that physical memory is used. Instead of trying to ad-dress physical memory locations outside of the conventional memory range, as extended memory does, expanded memory blocks are switched into the base memory range, where theCPU can access it in real mode. The original expanded memory specification (called the Lo-tus-Intel-Microsoft LIM or EMS specification) used 16KB banks of memory which weremapped into a 64KB range of real-mode memory existing just above the video memory range.Thus, four blocks of expanded memory could be dealt with simultaneously in the real mode.

Early implementations of expanded memory utilized special expansion boards thatswitched blocks of memory, but later CPUs that support memory mapping allowed ex-

panded memory managers (EMMs or LIMs) to supply software-only solutions for i386,i486, and Pentium-based machines. EMS/LIM 4.0 is the latest version of the expanded memory standard which handles up to 32MB of memory. An expanded memory manager (such as the DOS utility EMM386.EXE) allows the extended memory sitting in your com-

puter to emulate expanded memory. For most practical purposes, expanded memory ismore useful than extended memory because its ability to map directly to the real mode al-lows support for program multi-tasking. To use expanded memory, programs must bewritten specifically to take advantage of the function calls and subroutines needed toswitch memory blocks. Functions are completely specified in the LIM/EMS 4.0 standard.

UPPER MEMORY AREA (UMA)

The upper 384KB of real-mode memory is not available to DOS because it is dedicated tohandling memory requirements of the physical computer system. This is called the High

DOS Memory Range or Upper Memory Area (UMA) . However, even the most advanced PCs do not use the entire 384KB, so there is often a substantial amount of unused memoryexisting in your systems real-mode range. Late-model CPUs, such as the i386 and i486 canremap extended memory into the range unused by your system. Because this found mem-ory space is not contiguous with your 640KB DOS space, DOS application programs cannotuse the space, but small independent drivers and TSRs can be loaded and run from this UMA.The advantage to using high DOS memory is that more of the 640KB DOS range remainsavailable for your application program. Memory-management programs (such as the utili-ties found with DOS 5.0 and higher) are needed to locate and remap these memory blocks.



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HIGH MEMORY

A peculiar anomaly occurs with CPUs that support extended memorythey can accessone segment (about 64KB) of extended memory beyond the real-mode area. This capa-

bility arises because of the address line layout on late-model CPUs. As a result, the real-mode operation can access roughly 64KB above the 1MB limit. Like high DOS memory,this found 64KB is not contiguous with the normal 640KB DOS memory range, so DOScannot use this high memory to load a DOS application, but device drivers and TSRs can

be placed in high memory. DOS 5.0 is intentionally designed so that its 40 to 50KB of code can be easily moved into this high memory area. With DOS loaded into high mem-ory, an extra 40 to 50KB or so will be available within the 640KB DOS range.

Memory ConsiderationsMemory has become far more important than just a place to store bits for the micro-

processor. It has proliferated and specialized to the point where it is difficult to keep track of all the memory options and architectures that are available. This part of the chapter re-views established memory types, and explains some of the current memory architectures.

MEMORY SPEED AND WAIT STATES

The PC industry is constantly struggling with the balance between price and performance.Higher prices usually bring higher performance, but low cost makes the PC appealing tomore people. In terms of memory, cost-cutting typically involves using cheaper (slower)memory devices. Unfortunately, slow memory cannot deliver data to the CPU quicklyenough, so the CPU must be made to wait until memory can catch up. All memory is rated in terms of speedspecifically, access time . Access time is the delay between the time datain memory is successfully addressed, to the point at which the data has been successfully de-livered to the data bus. For PC memory, access time is measured in nanoseconds (ns), and current memory offers access times of 50 to 60 ns. 70-ns memory is extremely common.

The question often arises: Can I use faster memory than the manufacturer recommends?The answer to this question is almost always Yes, but rarely does performance benefit.As you will see in the following sections, memory and architectures are typically tailored for specific performance. Using memory that is faster should not hurt the memory or im-

pair system performance, but it costs more and will not produce a noticeable performanceimprovement. The only time such a tactic would be advised is when your current systemis almost obsolete, and you would want the new memory to be useable on a new, faster motherboard if you choose to upgrade the motherboard later on.

A wait state orders the CPU to pause for one clock cycle to give memory additional timeto operate. Typical PCs use one wait state, although very old systems might require twoor three. The latest PC designs with high-end memory or aggressive caching might be ableto operate with no (zero) wait states. As you might imagine, a wait state is basically awaste of time, so more wait states result in lower system performance. Zero wait states al-low optimum system performance. Table 23-9 illustrates the general relationship betweenCPUs, wait states, and memory speed. It is interesting to note that some of the fastest sys-tems allow the most wait states. This flexibility lets the system support old, slow memory,

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but the resulting system performance would be so poor that there would be little point inusing the system in the first place.

There are three classic means of selecting wait states. First, the number of wait states

might be fixed (common in old XT systems). Wait states might be selected with one or more jumpers on the motherboard (typical of i286 and early i386 systems). Current sys-tems, such as i486 and Pentium computers, place the wait state control in the CMOS setuproutine. You might have to look in an advanced settings area to find the entry. Whenoptimizing a computer, you should be sure to set the minimum number of wait states.

DETERMINING MEMORY SPEED

It is often necessary to check SIMMs or DIMMs for proper memory speed during troubleshooting, or when selecting replacement parts. Unfortunately, it can be very difficult todetermine memory speed accurately based on part markings. Speeds are normally marked cryptically by adding a number to the end of the part number. For example, a part number ending in -6 often means 60 ns, a 7 is usually 70 ns, and a 8 can be 80 ns. Still, the onlyway to be absolutely certain of the memory speed is to cross reference the memory partnumber with a manufacturers catalog, and read the speed from the catalogs description(i.e., 4M 32 50 ns EDO ).


TABLE 23-9 CPUS, WAIT STATES, ANDMEMORY SPEED

CPU WAIT STATES MEMORY ACCESS

8088 1 200 ns8086 0 150 ns80286 1 150 ns80286 1 120 ns80286 0 85 ns80386SX 02 100 ns80386SX/DX 02 85 ns80386SX 02 80 ns80386DX 05 80 ns80386SX 02 70 ns80486DX 05 80 ns80486DX 05 70 ns80486SLC2 02 70 ns80486SLC3 02 70 ns80486SX 02 70 ns80486DX4 02 70 ns80486DX2 02 70 nsPentium 05 60 nsPentium 02 50 ns

Setting too few wait states can cause the PC to behave erratically.


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PRESENCE DETECT (PD)

Another feature of modern memory devices is a series of signals known as the Presence Detect lines (youll see these as PDx signals in 72-pin pinouts, such as Table 23-2 and 23-3). By setting the appropriate conditions of the PD signals, it is possible for a computer toimmediately recognize the characteristics of the installed memory devices, and configureitself accordingly. Presence detect lines typically specify three operating characteristics of memory: size (device layout) and speed. Table 23-10 highlights many of the most com-monly used signal combinations.

UNDERSTANDING MEMORY REFRESH

The electrical signals placed in each DRAM storage cell must be replenished (or re-freshed) periodically every few milliseconds. Without refresh, DRAM data will be lost.In principle, refresh requires that each storage cell be read and re-written to the memoryarray. This is typically accomplished by reading and re-writing an entire row of the arrayat one time. Each row of bits is sequentially read into a sense/refresh amplifier (part of theDRAM IC), which basically recharges the appropriate storage capacitors, then re-writeseach row bit to the array. In actual operation, a row of bits is automatically refreshed whenever an array row is selected. Thus, the entire memory array can be refreshed byreading each row in the array every few milliseconds.

The key to refresh is in the way DRAM is addressed. Unlike other memory ICs that supply all address signals to the IC simultaneously, a DRAM is addressed in a two-step sequence.The overall address is separated into a row (low) address and a column (high) address. Row


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TABLE 23-10 INDEX OF PRESENCE DETECT (PD) SIGNALS

PIN 67 PIN 68 PIN 69 PIN 70 PIN 7172-PIN SIMM (PD1) (PD2) (PD3) (PD4) (PD5)

Size 256K 32/36 GND N/C (parity pinout) 512K 32/36 N/C GND

1M 32/36 GND GND 2M 32/36 N/C N/C 4M 32/36 GND N/C N/C8M 32/36 N/C GND N/C

Size 256K 32/36 GND N/C N/C(ECC pinout) 512K 32/36 N/C GND N/C

1M 32/36 GND GND N/C2M 32/36 N/C N/C N/C4M 32/36 GND N/C GND8M 32/36 N/C GND GND

Speed 60 ns N/C N/C (parity/ECC pinout) 70 ns GND N/C

80 ns N/C GND 100 ns GND GND 120 ns N/C N/C

GND = Jumper installedN/C = No jumper installed


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address bits are placed on the DRAM address bus first, and the Row Address Select (RAS)

line is pulsed logic 0 to multiplex the bits into the ICs address decoding circuitry. The low portion of the address activates an entire array row and causes each bit in the row to be sensed and refreshed. Logic 0s remain logic 0s and logic 1s are recharged to their full value.

Column address bits are then placed on the DRAM address bus, and the Column Ad-dress Select (CAS) is pulsed to logic 0. The column portion of the address selects the ap-

propriate bits within the chosen row. If a read operation is taking place, the selected bits pass through the data buffer to the data bus. During a Write operation, the Read/Write linemust be logic 0, and valid data must be available to the IC before CAS is strobed. Newdata bits are then placed in their corresponding locations in the memory array.

Even if the IC is not being accessed for reading or writing, the memory must still be re-freshed to ensure data integrity. Fortunately, refresh can be accomplished by interrupting themicroprocessor to run a refresh routine that simply steps through every row address in se-quence (column addresses need not be selected for simple refresh). This row-only (or -RAS

only) refresh technique speeds the refresh process. Although refreshing DRAM every fewmilliseconds might seem like a constant aggravation, the computer can execute quite a fewinstructions before being interrupted for refresh. Refresh operations are generally handled bythe chipset on your motherboard. Often, memory problems (especially parity errors) thatcannot be resolved by replacing a SIMM can be traced to a refresh fault on the motherboard.

MEMORY TYPES

For a computer to work, the CPU must take program instructions and exchange data di-rectly with memory. As a consequence, memory must keep pace with the CPU (or makethe CPU wait for it to catch up). Now that processors are so incredibly fast (and gettingfaster), traditional memory architectures are being replaced by specialized memory devicesthat have been tailored to serve specific functions in the PC. As you upgrade and repair var-ious systems, you will undoubtedly encounter some of the following memory designations:

s DRAM (Dynamic Random-Access Memory) This remains the most recognized and common form of computer memory. DRAM achieves a good mix of speed and density,while being relatively simple and inexpensive to produceonly a single transistor and capacitor is needed to hold a bit. Unfortunately, DRAM contents must be refreshed every few milliseconds or the contents of each bit location will decay. DRAM perfor-mance is also limited because of relatively long access times. Today, many video

boards are using DRAM SIMMs to supply video memory.s SRAM (Static Random-Access Memory) The SRAM is also a classic memory design

it is even older than DRAM. SRAM does not require regular refresh operations, and can be made to operate at access speeds that are much faster than DRAM. However,SRAM uses six transistors (or more) to hold a single bit. This reduces the density of SRAM and increases power demands (which is why SRAM was never adopted for gen-eral PC use in the first place). Still, the high speed of SRAM has earned it a place as thePCs L2 (or external) cache. Youll probably encounter three types of SRAM cacheschemes: asynchronous, synchronous burst, and pipeline burst.

s Asynchronous Static RAM (Async SRAM or ASRAM) This is the traditional form of L2cache, introduced with i386 systems. Theres really nothing too special about AS-RAM, except that its contents can be accessed much faster (20 ns, 15 ns, or 12 ns) than



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DRAM. ASRAM does not have enough performance to be accessed synchronously,

and has long since been replaced by better types of cache.s Synchronous-Burst Static RAM (Sync SRAM or SBSRAM) This is largely regarded asthe best type of L2 cache for intermediate-speed motherboards (~60 to 66MHz). Withaccess times of 8.5 ns and 12 ns, the SBSRAM can provide synchronous bursts of cacheinformation in 2-1-1-1 cycles (i.e., 2 clock cycles for the first access, then 1 cycles per accessin time with the CPU clock). However, as motherboards pass 66MHz (i.e., 75and 83MHz designs), SBSRAM loses its advantage to Pipelined Burst SRAM.

s Pipelined-Burst Static RAM (PB SRAM) At 4.5 to 8 ns, this is the fastest form of high- performance cache now available for 75MHz+ motherboards. PBSRAM requires anextra clock cycle for lead off, but then can sync with the motherboard clock (withtiming such as 3-1-1-1) across a wide range of motherboard frequencies. If youre in-terested in more technical details about PBSRAM, check out the ASUS site at:

http://asustek.asus.com.tw/Products/TB/mem-0001.html.

s VRAM (Video Random-Access Memory) DRAM has been the traditional choice for videomemory, but the ever-increasing demand for fast video information (i.e., high-resolutionSVGA displays) requires a more efficient means of transferring data to and from videomemory. Originally developed by Samsung Electronics, video RAM achieves speed im-

provements by using a dual data bus scheme. Ordinary RAM uses a single data bus data enters or leaves the RAM through a single set of signals. Video RAM provides aninput data bus and an output data bus. This allows data to be read from video RAM atthe same time new information is being written to it. You should realize that the advan-tages of VRAM will only be realized on high-end video systems, such as 1024 768 256(or higher), where you can get up to 40% more performance than a DRAM video adapter.Below that, you will see no perceivable improvement with a VRAM video adapter.

s FPM DRAM (Fast-Page Mode DRAM) This is a popular twist on conventional DRAM.Typical DRAM access is accomplished in a fashion similar to reading from a bookamemory page is accessed first, then the contents of that page can be located. The

problem is that every access requires the DRAM to re-locate the page. Fast-pagemode operation overcomes this delay by allowing the CPU to access multiple pieces of data on the same page without having to re-locate the page every timeas longas the subsequent read or write cycle is on the previously located page, the FPDRAMcan access the specific location on that page directly.

s EDRAM (Enhanced DRAM) This is another, lesser-known variation of the classicDRAM developed by Ramtron International and United Memories. First demonstrated in August 1994, the EDRAM eliminates an external cache by placing a small amount of static RAM (cache) into each EDRAM device itself. In essence, the cache is distributed within the system RAM; as more memory is added to the PC, more cache is effectivelyadded as well. The internal construction of an EDRAM allows it to act like page-modememoryif a subsequent read requests data that is in the EDRAMs cache (known asa hit ), the data is made available in about 15 nsroughly equal to the speed of a fair ex-ternal cache. If the subsequent read requests data that is not in the cache (called a miss ),the data is accessed from the DRAM portion of memory in about 35 ns, which is stillmuch faster than ordinary DRAM.

s EDO RAM (Extended Data Output RAM) EDO RAM is a relatively well-established variation to DRAM, which extends the time that output data is validthus the words


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presence on the data bus is extended. This is accomplished by modifying the

DRAMs output buffer, which prolongs the time where read data is valid. The data willremain valid until a motherboard signal is received to release it. This eases timing con-straints on the memory and allows a 15 to 30% improvement in memory performancewith little real increase in cost. Because a new external signal is needed to operate EDORAM, the motherboard must use a chipset designed to accommodate EDO. Intels Tri-ton chipset was one of the first to support EDO, although now most chipsets (and mostcurrent motherboards) currently support EDO. EDO RAM can be used in non-EDOmotherboards, but there will be no performance improvement.

s BEDO (Burst Extended Data Output RAM) This powerful variation of EDO RAMreads data in a burst, which means that after a valid address has been provided, the nextthree data addresses can be read in only one clock cycle each. The CPU can read BEDO data in a 5-1-1-1 pattern (5 clock cycles for the first address, then one clock cy-cle for the next three addresses. Although BEDO offers an advantage over EDO, it is

only supported currently by the VIA chipsets: 580VP, 590VP, 680VP. Also, BEDOseems to have difficulty supporting motherboards over 66MHz.

s SDRAM (Synchronous or Synchronized DRAM) Typical memory can only transfer dataduring certain portions of a clock cycle. The SDRAM modifies memory operation sothat outputs can be valid at any point in the clock cycle. By itself, this is not really sig-nificant, but SDRAM also provides a pipeline burst mode that allows a second accessto begin before the current access is complete. This continuous memory access offerseffective access speeds as fast as 10 ns, and can transfer data at up to 100MB/s. SDRAMis becoming quite popular on current motherboard designs, and is supported by the IntelVX chipset, and VIA 580VP, 590VP, and 680VP chipsets. Like BEDO, SDRAM cantransfer data in a 5-1-1-1 pattern, but it can support motherboard speeds up to 100MHz,which is ideal for the 75MHz and 82MHz motherboards now becoming so vital for Pen-tium II systems. Check out the following references for more information on SDRAM:~http://www.chips.ibm.com/products/memory/sdramart/sdramart.html~http://www.fujitsu-ede.com/sdram/index.html~http://www.ti.com/sc/docs/memory/brief.htm

s CDRAM (Cached DRAM) Like EDRAM, the CDRAM from Mitsubishi incorporatescache and DRAM on the same IC. This eliminates the need for an external (or L2)cache, and has the extra benefit of adding cache whenever RAM is added to the system.The difference is that CDRAM uses a set-associative cache approach that can be 15to 20% more efficient than the EDRAM cache scheme. On the other hand, EDRAMappears to offer better overall performance.

s RDRAM (Rambus DRAM) Most of the memory alternatives so far have been variationsof the same basic architecture. Rambus, Inc. (joint developers of EDRAM) has created a new memory architecture called the Rambus Channel . A CPU or specialized IC isused as the master device and the RDRAMs are used as slave devices. Data is thensent back and forth across the Rambus channel in 256-byte blocks. With a dual250MHz clock, the Rambus Channel can transfer data based on the timing of bothclocksthis results in data-transfer rates approaching 500MB/s (roughly equivalent to2-ns access time). The problem with RDRAM is that a Rambus Channel would requirean extensive re-design to the current PC memory architecturea move that most PCmakers strenuously resist. As a result, you are most likely to see RDRAM in high-end,



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specialized computing systems. Still, as memory struggles to match the microproces-

sor, PC makers might yet embrace the Rambus approach for commercial systems.s WRAM (Windows RAM) Samsung Electronics has recently introduced WRAM as anew video-specific memory device. WRAM uses multiple-bit arrays connected with anextensive internal bus and high-speed registers that can transfer data almost continu-ously. Other specialized registers support attributes, such as foreground color, background color, write-block control bits, and true-byte masking. Samsung claims data-transfer ratesof up to 640MB/sabout 50% faster than VRAMyet WRAM devices are cheaper than their VRAM counterparts. It is likely that WRAM will receive some serious con-sideration in the next few years.

MEMORY TECHNIQUES

Rather than incur the added expense of specialized memory devices, PC makers often use

inexpensive, well-established memory types in unique architectures designed to make themost of low-end memory. The three most-popular architectures are: paged memory, in-terleaved memory, and memory caching.

Paged memory This approach basically divides system RAM into small groups (or pages) from 512 bytes to several KB long. Memory-management circuitry on the moth-erboard allows subsequent memory accesses on the same page to be accomplished withzero wait states. If the subsequent access occurs outside of the current page, one or morewait states might be added while the new page is found. This is identical in principle tofast-page mode DRAM. You will find page-mode architectures implemented on high-end i286, PS/2 (model 70 and 80), and many i386 systems.

Interleaved memory This technique provides better performance than paged mem-ory. Simply put, interleaved memory combines two banks of memory into one. The first

portion is even, while the second portion is oddso memory contents are alternated between these two areas. This allows a memory access in the second portion to begin be-fore the memory access in the first portion has finished. In effect, interleaving can doublememory performance. The problem with interleaving is that you must provide twice theamount of memory as matched pairs. Most PCs that use interleaving will allow you to add memory one bank at a time, but interleaving will be disabled and system performance willsuffer.

Memory caching This is perhaps the most recognized form of memory-enhancementarchitecture (Fig. 23-5). Cache is a small amount (anywhere from 8KB to 1MB) of veryfast SRAM, which forms an interface between the CPU and ordinary DRAM. The SRAMtypically operates on the order of 5 to 15 ns, which is fast enough to keep pace with a CPUusing zero wait states. A cache-controller IC on the motherboard keeps track of frequentlyaccessed memory locations (as well as predicted memory locations), and copies those con-tents into cache. When a CPU reads from memory, it checks the cache first. If the needed contents are present in cache (called a cache hit), the data is read at zero wait states. If theneeded contents are not present in the cache (known as a cache miss), the data must be read directly from DRAM at a penalty of one or more wait states. A small quantity of very fast


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cache (called Tag RAM) acts as an index, recording the various locations of data stored incache. A well-designed caching system can achieve a hit ratio of 95% or morein other words, memory can run without wait states 95% of the time.

Two levels of cache are in the contemporary PC. CPUs from the i486 onward have asmall internal cache (known as L1 cache ) and external cache (SRAM installed as DIPs or COAST modules on the motherboard) is referred to as L2 cache . The i386 CPUs have nointernal cache (although IBMs 386SLC offered 8KB of L1 cache). Most i486 CPUs pro-vide an 8KB internal cache. Early Pentium processors were fitted with two 8KB internalcachesone for data and one for instructions. Todays Pentium II Slot 1 CPU incorpo-rates 256 to 512KB of L2 cache into the processor cartridge itself.

Shadow memory ROM devices (whether the BIOS ROM on your motherboard or aROM IC on an expansion board) are frustratingly slow with access times often exceedingseveral hundred nanoseconds. ROM access then requires a large number of wait states,which slow down the systems performance. This problem is compounded because theroutines stored in BIOS (especially the video BIOS ROM on the video board) are some of the most frequently accessed memory in your computer.

Beginning with the i386-class computers, some designs used a memory technique called shadowing . ROM contents are loaded into an area of fast RAM during system initializa-tion, then the computer maps the fast RAM into memory locations used by the ROM de-vices. Whenever ROM routines must be accessed during run time, information is takenfrom the shadowed ROM instead of the actual ROM IC. The ROM performance can beimproved by at least 300%.

Shadow memory is also useful for ROM devices that do not use the full available data

bus width. For example, a 16-bit computer system might hold an expansion board thatcontains an 8-bit ROM IC. The system would have to access the ROM not once, but twice,to extract a single 16-bit word. If the computer is a 32-bit machine, that 8-bit ROM would have to be addressed four times to make a complete 32-bit word. You might imagine thehideous system delays that can be encountered. Loading the ROM to shadow memory inadvance virtually eliminates such delays. Shadowing can usually be turned on or off through the systems CMOS Setup routines.


Cachelogic

CPUTag RAM

Cache RAM

Main system RAM

FIGURE 23-5 Major cache system components.


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The Issue of ParityAs you might imagine, it is vital that data and program instructions remain error-free.Even one incorrect bit because of electrical noise or a component failure can crash the PC,corrupt drive information, cause video problems, or result in a myriad of other faults. PCdesigners approached the issue of memory integrity by using a technique known as parity(the same technique used to check serial data integrity).

THE PARITY PRINCIPLE

The basic idea behind parity is simpleeach byte written to memory is checked, and a9th bit is added to the byte as a checking (or parity) bit. When a memory address islater read by the CPU, memory-checking circuitry on the motherboard will calculate

the expected parity bit and compare it to the bit actually read from memory. In thisfashion, the PC can continuously diagnose system memory by checking the integrity of its data. If the read parity bit matches the expected parity bit, the data (and, indirectly,the RAM) is assumed to be valid, and the CPU can go on its way. If the read and ex-

pected parity bits do not match, the system registers an error and halts. Every byte isgiven a parity bit, so for a 32-bit PC, there will be 4 parity bits for every address. A 64-

bit PC, has 8 parity bits, etc.

EVEN VS. ODD

The two types of parity are even and odd. With even parity, the parity bit is set to 0 if aneven number of 1s are already in the corresponding byte (keeping the number of 1s even).If an even number of 1s is not in the byte, the even parity bit will be 1 (making the num-

ber of 1s even).With odd parity, the parity bit is set to 0 if an odd number of 1s is already in the corre-

sponding byte (keeping the number of 1s odd). If an odd number of 1s is not in the byte,the odd parity bit will be 1 (making the number of 1s odd).

Although even and odd parity work opposite of one another, both schemes serve exactlythe same purpose and have the same probability of catching a bad bit. The memory deviceitself does not care at all about what type of parity is being usedit just needs to have the

parity bits available. The use of parity (and the choice of even or odd) is left up to themotherboards memory-control circuit.

THE PROBLEMS WITH PARITY

Although parity has proven to be a simple and cost-effective means of continuously check-ing memory, there are two significant limitations. First, although parity can detect an er-ror, it cannot correct the error because there is no way to tell which bit has gone bad. Thisis why a system simply halts when a parity error is detected. Second, parity is unable todetect multi-bit errors. For example, if a 1 accidentally becomes a 0 and a 0 accidentally

becomes a 1 within the same byte, parity conditions will still be satisfied. Fortunately, the probability of a multi-bit error in the same byte is extremely remote.

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CIRCUMVENTING PARITY

Over the last few years, parity has come under fire from PC makers and memory manu-facturers alike. Opponents claim that the rate of parity errors because of hardware (RAM)faults is very small and that the expense of providing parity bits in a memory-hungry mar-ketplace just isnt justified anymore. There is some truth to this argument, considering thatthe parity technique is more than 15 years old and has serious limitations.

As a consequence, a few motherboard makers have begun removing parity support fromtheir low-end motherboards, and others are providing motherboards that will function withor without parity (usually set in CMOS or with a motherboard jumper). Similarly, somememory makers are now providing non-parity and fake parity memory as cheaper alter-natives to conventional parity memory. Non-parity memory simply foregoes the 9th bit.For example, a non-parity SIMM would be designated 8 or 32 (i.e., 4M 8 or 4M 32). If the SIMM supports parity, it will be designated 9 or 36 (i.e., 4M 9 or 4M 36 ). Fake parity is a bit more deviousthe 9th bit is replaced by a simple (and dirt cheap)

parity-generator chip that looks like a normal DRAM IC. When a read cycle occurs, the parity chip on the SIMM provides the proper parity bit t

memory tshooting

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