meljun cortes--logic design meljun888
TRANSCRIPT
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MELJUN CORTES,BSCS,ACS
Department of ICTFaculty of Information Technology
Digital Logic Design
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About
Author: MELJUN CORTES,BSCS,ACSOffice:
Department of Computer Science
Faculty of Information Technology
HOLY CHILD COLLEGES OF BUTUAN
Mobile: 09295141799
Email:
mailto:[email protected]:[email protected] -
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Content
1. Introduction2. Function Minimization Methods
3. Larger Combinational Systems
4. Sequential Systems
5. Hardware Design Languages
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Acknowledge
The following materials are used as reference for this slide: Logic Circuits slide, Dr. Trinh Van Loan.
Introduction to Logic Design, 2nd Ed, Alan B. Marcovitz, Mc. Graw
Hill,2005
Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott,World Scientific, 1998
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Reference textbooks
Introduction to Logic Design, 2nd
Ed,, Alan B, Marcovitz, Mc.Graw Hill,2005
Foundation of Digital Logic Design, G.Langholz, A. Kandel, J.
Mott, World Scientific, 1998
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Grading policy
Homework: 20%Lab work: 20%
Midterm: 30%
Final Exam (multichoice and writing): 30%
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1. Introduction
1.1. Review of Number Systems1.2. Switching Algebra and Logic Circuits
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Chapter 1. Introduction
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1.1. Review of Number Systems
1.1.1 Number Representation1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
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1.1. Review of Number Systems
1.1.1 Number Representation1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
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1.1.1. Number Representation
Numbers are normally written using a positional number system:
Base/radix: b (the number of digits) Digits: 0..(b-1)
0 ai (b-1)
Binary: b=2, digits:0,1 Decimal: b=10, digits: 0,1,2,3,4,5,6,7,8,9
Octal: b=8, digits: 0,1,2,3,4,5,6,7
Hexadecimal: b=16, digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
mnnnbaaaaaaaaN = ....... 210121)(
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1.1.1. Number Representation
mnnnbaaaaaaaaN = ....... 210121)(
m
m
n
n
n
n babababababaN
+++++++=
............
1
1
0
0
1
1
1
1)10(
==
n
mi
i
i baN .)10(
11101.11(2) = 1x24+1x23+1x22+0x21+1x20+1x2-1+1x2-2=
29.75(10)
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1.1.1. Number Representation
Decimal:
b=10
Digits: 0,1,2,3,4,5,6,7,8,9
Eg:
539.45(10) = 5x102+3x101+9x100+4x10-1+5x10-2
mnnnaaaaaaaaN = ....... 210121)10( ai = 0..9
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1.1.1. Number Representation
Binary: b=2
Digits: 0,1
Eg:
1011.011(2) = 11 + 0*2-1 + 1*2-2+1*2-3=11 + 0 + 0.25 + 0.125
= 11.375(10)
mnnnaaaaaaaaN = ....... 210121)2( ai = 0,1
bit binary digit
==n
mi
i
iaN 2.)10(
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1.1.1. Number Representation
Binary (cnt)
n-bit binary number can represent which range?
an-1 ...a1a0 from 0 to 2n-1
MSB Most Significant Bit
LSB Least Significant Bit
0001 = 1 1001 = 9
0010 = 2 1010 = 10
0011 = 3 1011 = 11
0100 = 4 1100 = 12
0101 = 5 1101 = 13
0110 = 6 1110 = 14
0111 = 7 1111 = 15
1000 = 8
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1.1.1. Number Representation
Octal:
b=8
Digits: 0,1,2,3,4,5,6,7
Eg:
503.071(8)
= 5x82+ 0x81+ 3x80+ 0x8-1+ 7x8-2+ 1x8-3
mnn aaaaaaaN = ....... 21011)8(
ai = 0..7
Hexadecimal:
b=16
Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Eg:
1010 0011(2)= A3(16)
503.071(16) = 5x162 + 0x161 + 3x160 + 0x16-1 + 7x16-2 + 1x16-3
ai = 0..Fmnn
aaaaaaaN
=....... 21011)16(
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Convert from base b to base 10
Base b to base 10 conversion
Eg:0
1010.11(2) = 10.75
1010.11(8) = 0*80+1*81+0*82+1*83 + 1*8-
1+1*8-2 = 0+8+0+512+0.125+0.015625
A12(16) = 10572 = 2*160
+ 1*161
+ 10*162
=
mnnnbaaaaaaaaN = ....... 210121)(
mm
nn
nn babababababaN
+++++++= ............ 11001111)10(
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110.011(2)=?(10) 6.375
110.011(8)=?(10) 72.0175
110.011(16)=?(10) 272.039...
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Convert from base 10 to base b
Base 10 to base b conversionFor integer part:
Divide integer part by b until the result is 0
Write remainders in reverse order to get the converted result.
For the odd part after .
Multiply by b until the result is 0
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Convert from base 10 to base 2
Eg1: 6.625(10) = ?(2)
The integer part
Eg2: 20.75(10) = ?(2)
6 2
0 3 2
1 1 2
1 0
The odd part after .
0.625 x 2 = 1.25
0.25 x 2 = 0.5
0.5 x 2 = 1.0
6.625(10) = 110.101(2)
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20.75(10) = ?(2)10100.11(2)
20 2 0.75 * 2 = 1.5
0 10 2 0.5 * 2 = 1.0 0 5 2
1 2 2
0 1 2
1 0
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20.75(10)=?(8)=10100.11(2) = 24.6(8)
20 8 0.75 * 8 = 6.0
4 2 8 2 0
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Convert from base 2 to base 2n
Group from right to left n-bit groups and replace the equivalent values in
base 2n
Eg:
101011(2) = ?(8) 1010.110(2) =12.6(8)
101011(2) = ?(16) 1010.110(2) =A.C(16)
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Convert from base 2n to base 2
Each digit in base 2n
is replaced by n bit in base 2.
Eg:
37A.B(16)=?(2) = 0011 0111 1010 . 1011(2)
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Convert from base i to base j
If both i and j are powers of 2, use base 2 as an intermediatebase:
Eg: base 8 base 2 base 16
735.37(8)= 000111011101.01111100(2) = 1DD.7C ?(16)
Else, use base 10 as an intermediate base:
Eg: base 5 base 10 base 2
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1.1. Review of Number Systems
1.1.1 Number Representation1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction
1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
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1.1.2 Binary Addition
Binary long addition similar to decimal long addition.
decimalbinary
carry 110 11110
A 2565 10110B 6754 11011
sum 9319 110001
Eg: 10101(2) + 11011(2) = 110000 ? (2)
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1.1.2 Binary Addition
Overflow:
Occur when the result of addition is out of range of representation
(the result can not be stored in the predefined number of bits)
In 8-bit computer, the result of addition of two binary numbers
10101010 and 11010011 is 9-bit binary number which can not be
stored in 8-bit => overflow
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1.1.2 Binary Addition
n-bit adder in computer:A = an-1an-2...a1a0
B = bn-1bn-2...b1b0
1 1 R i f N b S t
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1.1. Review of Number Systems
1.1.1 Number Representation1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction
1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
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1.1.3 Signed Numbers
Represent sign and amplitudeUse the most-left-bit to represent sign:
0: positive, 1: negative
Eg: represent signed numbers using 4 bit:
+5 = 0101, -5 = 1101, -3 = 1011
Using 3 right bits to represent amplitude, we can represent from -7 to
+7.
Drawbacks:
+0 = 0000, -0 = 1000 => complex when calculating
=> need an other representation
2 l t t ti
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2s complement representation
Most left bit is still sign bit
Positive and 0 numbers are expressed in usual binary
format.
The largest number can be represented is 2n-1-1
n=8 => largest signed number: 28-1-1 = 127
Negative numbera is stored as the binary equivalent of 2n-a
in a n-bit system.
-3 is stored as 28-3=11111101 in a 8-bit system
The most negative number can be stored is -2n-1
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2s complement representation
+10 = 0000 1010 - 10 = 28-10 = 1 0000 0000
0000 1010
1111 0110
- 10 = 1111 0110
+10 + (-10) = ? 0000 1010
1111 0110
1 0000 0000
2s complement representation
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2 s complement representation
Procedure to find binary representation of negative numberin 2s complement:
Find the binary equivalent of the magnitude
Complement each bit (0=>1, 1=>0)
Add 1
Eg: find representation of -13 in 8-bit signed numbersystem using 2s complement:
Magnitude: 13 = 0000 1101
Complement: 1111 0010
Add 1: 1
-13 = 1111 0011+
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2s complement representation
Range of representation: Use n bit to represent 2s complement numbers
Range: -2n-1 => 2n-1-1
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4 bit representation of unsigned and signed (2s complement)
Binary format Unsigned Signed
0000 0 0
0001 1 +1
0010 2 +2
0011 3 +3
0100 4 +4
0101 5 +5
0110 6 +60111 7 +7
1000 8 -8
1001 9 -7
1010 10 -6
1011 11 -5
1100 12 -4
1101 13 -3
1110 14 -2
1111 15 -1
2s complement representation
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2s complement representation
To find the magnitude of a negative number: Complement each bit
Add 1
Eg: 1001 0110(2) = -106?
0110 1001
+ 1
01101010 = 106
Additi f i d b
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Addition of signed numbers
The reason that 2s complement is so popular is the simplicityof addition.
To add any two numbers, no matter what the sign of each is,
we just do binary addition on their representation.
-5 1011 -5 1011 -5 1011
+7 0111 +5 0101 +3 0011
+2 0010 0 0000 -2 1110
Additi f i d b
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Addition of signed numbers
Overflow Occur when?
Add two numbers of the opposite sign?
Add two positive numbers?
Add two negative numbers?maybe
Overflow occurs when adding two numbers with the samesign and the result is in different sign
0110 0101 = 101
+ 0101 0010 = 82
1011 0111
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1.1. Review of Number Systems
1.1.1 Number Representation
1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction
1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
1 1 4 Bi S bt ti
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1.1.4 Binary Subtraction
Find the 2s complement of the second operand, then add.
a b = a + (-b)
Eg: 7 5 = ?
5 0101 7 0111
1010 -5 +1011
+ 1 2 0010
-5 1011
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1.1. Review of Number Systems
1.1.1 Number Representation
1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction
1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
Bi C d d D i l BCD
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Binary-Coded Decimal - BCD
BCD:
Use four bits (a nibble) to represent
each of the decimal digits 0 through
9.
Eg:
375 = 0011 0111 0101(BCD)
Decimal Binary BCD0 0000 0000
1 0001 0001
2 0010 0010
3 0011 0011
4 0100 0100
5 0101 0101
6 0110 0110
7 0111 0111
8 1000 1000
9 1001 1001
10 1010 0001 0000
11 1011 0001 0001
12 1100 0001 0010
13 1101 0001 0011
14 1110 0001 0100
15 1111 0001 0101
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1.1. Review of Number Systems
1.1.1 Number Representation
1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction
1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes
ASCII
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ASCII
American Standard Code for Information Interchange - ASCII
Use seven bits to represent various characters on the
standard keyboard as well as a number of control signal
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Problems
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Problems
1. Convert the following unsigned numbers:
a. 98.625(10)=?(2)
b. 11011.011(2)=?(10)
c. 6A1.1E(16)=?(8)
2. Represent the following signed numbers:
a. -74 in 8-bit signed 2s complement.
b. -74 in 16-bit signed 2s complement.
1 Introduction
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1. Introduction
1.1. Review of Number Systems
1.2. Switching Algebra and Logic Circuits
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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.4 Representations of Algebraic Functions
1.2.5 Implementation of Functions with AND, OR, NOT, NAND,
NOR, XOR Gates
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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.3 Representations of Algebraic Functions
1.2.4 Implementation of Functions with AND, OR, NOT, NAND,
NOR, XOR Gates
1 2 1 Definition of Switching Algebra
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1.2.1 Definition of Switching Algebra
Switching algebra is binary:
All variables and constant take on 0 or 1.
Light on/off, switch: up/down, voltage: low/high...
Quantities which are not naturally binary must be coded into binary
format.
Three operators:
OR: a+b
AND: a.b
NOT: a
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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.3 Representations of Algebraic Functions
1.2.4 Implementation of Functions with AND, OR, NOT, NAND,
NOR, XOR Gates
Basic Properties of Switching Algebra
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Basic Properties of Switching Algebra
P1: Commutative: a + b = b + a a.b = b.a
P2: Associative:
a + (b + c) = (a + b) + c a.(b.c) = (a.b).cP3:
a + 0 = a a . 1 = a
P4: a + 1 = 1 a . 0 = 0
Basic Properties of Switching Algebra
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Basic Properties of Switching Algebra
P5: a + a = 1 a . a = 0
P6: no coefficient and no exponent
a + a = a a . a = a
n.a=a (a)n=a
P7: complement
(a) = a
P8: distributive:
a.(b+c) = a.b + a.c a + b.c = (a+b).(a+c)
Basic Properties of Switching Algebra
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P9: adjacency ab + ab = a (a+b)(a+b)=a
P10:
a + ab = a +b a(a+b) = abP11: De Morgan
(a + b) = ab (ab) = a + b
P12: absorption
a + ab = a a(a+b) = a
Basic Properties of Switching Algebra
Basic Properties of Switching Algebra
Basic Properties of Switching Algebra
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P13: redundant ab+bc+ac = ab+bc
A B
C
Basic Properties of Switching Algebra
Problems
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Problems
1. Prove the following equalities:
a. xy+y=x+y
b. xy+xz+yz=xy+xz => prove it incorrect
c. xyz+yz+xz=z
d. (x+y)[x(y+z)]+xy+xz = 1
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1.2. Switching Algebra and Logic Circuits
1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.4 Representations of Algebraic Functions
1.2.5 Implementation of Functions with AND, OR, NOT, NAND,
NOR, XOR Gates
Manipulation of Algebraic Functions
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Manipulation of Algebraic Functions
A literal:
Is the appearance of a variable or its complement
Eg: x and x are two different literals
Expression ab+bcd+ad+e has 8 literals
A product term:
Is one or more literal connected by AND operators
Expression ab+bcd+ad+ehas 4 product terms
Note: A single literal is also a product term
Manipulation of Algebraic Functions
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A standard product term - minterm: Is a product term which includes every variable of the
function, either uncomplemented or complemented.
Eg: for a function of four variables a,b,c,d:
the product term abcd is a standard product term
the product term abd is not
Manipulation of Algebraic Functions
Manipulation of Algebraic Functions
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A sum of product - SOP:
Is one or more product terms connected by OR operators
Eg: abc+abc+ac+a
d
A canonical sum sum of standard product term
Is a sum of products expression where all terms are
standard product terms.
Eg: A function of three variables a,b,c: abc + abc + abc is a canonical sum
abc + abc + a is not
Manipulation of Algebraic Functions
Manipulation of Algebraic Functions
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A minimum sum of products:
Is one of those SOP expression for a function that hasthe fewest number of product terms.
If there is more than one expression with fewest numberof terms, then minimum is defined as one or more ofthose expressions with the fewest number of literals.
Eg:
F1(x,y,z) = xyz+xyz+ xyz+xyz+xyz
F2(x,y,z) = xy+xy+xyz F3(x,y,z) = xy+xy+xz
F4(x,y,z) = xy+xy+yz
Manipulation of Algebraic Functions
F3,F4 are minimum SOP of F1
Manipulation of Algebraic Functions
Manipulation of Algebraic Functions
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A sum term:
Is one or more literals connected by OR operators
Eg:
a + b + c
b
A standard sum term - maxterm:
Is a sum term that includes each variable of the problem,either uncomplemented or complemented
Eg: For a function of four variables x,y,z,t
x+y+z+t is a maxterm
x+y+t is not
Manipulation of Algebraic Functions
Manipulation of Algebraic Functions
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A product of sum POS: Is one or more sum terms connected by AND
Eg:
(w+x+y)(w+y+z)(w+x+z)
w
A canonical product product of standard sum
terms:
Is a product of sum term where all sum terms are standard
Manipulation of Algebraic Functions
a pu at o o geb a c u ct o s
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A minimum POS is defined the same way as SOP: fewest number of terms
the same number of terms => fewest number of literals
Manipulation of Algebraic Functions
p g
Canonical forms
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Three-variable minterm and Maxterm
Decimal x y z minterm Maxterm
0 0 0 0 xyz (m0) x+y+z (M0)
1 0 0 1 xyz (m1) x+y+z (M1)
2 0 1 0 x'yz (m2) x+y+z (M2)
3 0 1 1 x'yz (m3) x+y+z (M3)
4 1 0 0 xyz (m4) x+y+z (M4)
5 1 0 1 xy'z (m5) x'+y+z (M5)
6 1 1 0 xyz' (m6) x'+y+z (M6)
7 1 1 1 xyz (m7) x'+y+z (M7)
Canonical forms
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67
Properties of minterm/Maxterm: mimj=0 if ij
=mi if i=j
Mi+Mj=1 if ij
= Mi if i=j
mi=Mi and Mi=mi for every i
Canonical forms
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68
An algebraic expression of a Boolean function canbe derived from a given truth table in two ways:
By summing (ORing) those minterm for which the function
takes a value 1.
By multiplying (ANDing) those maxterm for which thefunction takes a value 0.
Canonical forms
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69
Decimal x2 x1 x0 f
0 0 0 0 0
1 0 0 1 1
2 0 1 0 03 0 1 1 0
4 1 0 0 1
5 1 0 1 1
6 1 1 0 17 1 1 1 1
f(x2,x1,x0)=m1+m4+m5+m6+m7=(1,4,5,6,7)
f(x2,x1,x0)=M0
M2
M3
= (0,2,3)
Canonical sum-of-products (SOP)
Canonical product-of-sums (POS)
F(a,b,c)= abc+ab
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( , , )
F(a,b,c)=m0+m1+m6 (0,1,6)
Decimal a b c f
0 0 0 0 1
1 0 0 1 1
2 0 1 0 0
3 0 1 1 0
4 1 0 0 0
5 1 0 1 0
6 1 1 0 1
7 1 1 1 0
1.2. Switching Algebra and Logic Circuits
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71
g g g
1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.4 Representations of Algebraic Functions
1.2.5 Implementation of Functions with AND, OR, NOT, NAND,
NOR, XOR Gates
1.2.4 Representations of Algebraic Functions
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72
g
Truth table
Venn diagram
Karnaugh map
Truth table
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List all the possible binary combinations of the independent
variables and display the corresponding binary values of
dependant variables.
Truth table
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n independent variables and m dependant functions:
2n rows
n+m columns 3 independentvariables
2 dependent
functions
23 rows
Venn diagram
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Venn diagram using space to present logic
F(A,B)=A.B
A B
C
F(A,B,C)=C.not(B)
Venn diagram
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A A
A+B A.B
A.BA+B
Karnaugh map
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BC
A00 01 11 10
00 1 3 2
14 5 7 6
C
AB
0 1
000 1
01 2 3
116 7
10
4 5
A Karnaugh map is a graphical method for
representing the true table of a Boolean function.K-map may be used for any variables number, but
often at most six.
Karnaugh map (K-map)
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If variables number is n => 2n cells in K-map.
2n cells are arranged in logical pattern for minimization
purpose.
BC
A00 01 11 10
00 1 3 2
14 5 7 6
Two-variable K-map
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F(A,B)
0 1
2
3
AB 0 1
0
1
0 2
1
3
BA 0 1
0
1
Two-variable K-map
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F(A,B) = AB
0 0
0 1
AB 0 1
0
1
Three-variable K-map
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F(A,B,C)
BC
A00 01 11 10
00 1 3 2
14 5 7 6
C
AB
0 1
000 1
012 3
11 6 7
104 5
Three-variable K-map
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F(x,y,z) = xyz + yz + x
x y z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
yz
x
00 01 11 10
0 0 0 0 1
1 1 1 1 1
z
xy
0 1
00 0 0
01 1 0
11 1 1
10 1 1
Four-variable K-map
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CD
AB00 01 11 10
00
01
11
10
F(A,B,C,D)
Four-variable K-map
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F(A,B,C,D) = AB + CD + BCD
CD
AB00 01 11 10
000 0 0 1
01 0 0 1 1
11 1 1 1 1
10 0 0 0 1
Five-variable K-map
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00 01 11 10ABCD
00
01
11
10
00 01 11 10ABCD
00
01
11
10
E 0 1
5 variables Karnaugh Map consists of two4 variables Karnaugh Map connected up/down.
Six-variable K-map
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1 1
1 1
1 1
00 01 11 10ABCD
00
01
11
10
1 1
1 1
1 1
00 01 11 10ABCD
00
01
11
10
E 0 1
1 1
1 1
1 1
00 01 11 10ABCD
00
01
11
10
1 1
1 1
1 1
00 01 11 10ABCD
00
01
11
10
F
0
1
Karnaugh map with dont care
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CD00 01 11 10
00
01
11
10
AB
1 1
1 1
dont care ~ input conditions that not occur
1.2. Switching Algebra and Logic Circuits
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1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.4 Representations of Algebraic Functions
1.2.5 Implementation of Functions with AND, OR, NOT, NAND,
NOR, XOR Gates
Basic logic gates
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AND OR NOT
A B out
0 0 0
0 1 0
1 0 0
1 1 1
A B out
0 0 0
0 1 1
1 0 1
1 1 1
A out
0 1
1 0
Basic logic gates
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NAND NOR XOR
A B out
0 0 1
0 1 11 0 1
1 1 0
A B out
0 0 1
0 1 01 0 0
1 1 0
A B out
0 0 0
0 1 11 0 1
1 1 0
Implementation of Functions with AND, OR
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Assume all inputs are available in uncomplemented and
complemented
F1 = xyz+xyz+xyz+xyz+xyz
F2 = xy+xy+xz
Implementation of Functions with AND, OR, NOT
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Complemented inputs can be produced using inverters NOT:
X
Y
Z
F
Multilevel circuits
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A circuit is called n-level circuit if the maximum number of
gates through which one signal must pass from input tooutput
two-level circuit three-level circuit
Implementation of Functions with NAND
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Using equivalent change steps, every expression can be
represented using only NAND gates.
NOT
AND
OR
A
B
A.B (A.B)=A+B
A
B
Implementation of Functions with NAND
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Represent the following expression using only NAND:
F(a,b,c) = ab + bc + b
=
bcbabbcbabbcbab ..=++=++
Implementation of Functions with NOR
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Using equivalent change steps, every expression can be
represented using only NOR gates.
U10A
7402N
U11A
7402N
U7A
7402N
U8A
7402N
U9A
7402N
A
B
( A' +B' ) ' =A. B
A'
B'U3A
7402N
A
( A+A) ' =A'
Implementation of Functions with NOR
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Represent the following expression using only NOR:
F(a,b,c) = ab + bc + b
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Chapter 2.
Logic Function Minimization Methods
2. Function Minimization Methods
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2.1 Algebraic Method
2.2 The Karnaugh Map Method
2.3 Quine-McCluskey Method
2. Function Minimization Methods
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What is minimization?
Number of operands is minimal and number of literal in each operand is
minimal
Why minimization needed?
Minimize electronic components used to construct the circuit to
implement that expression
2. Function Minimization Methods
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2.1 Algebraic Method
2.2 The Karnaugh Map Method
2.3 Quine-McCluskey Method
2.1. Algebraic Method
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Page 102
Use algebraic properties to minimize expressions
Drawback:
Heuristic, depending on experience no formal method/procedure
Manually
Not sure whether the last expression is minimal or not
2.1. Algebraic Method
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Eg: Minimize these expressions using algebraic method:
F0(x,y,z)=xyz+xyz+xyz+xyz
F1(a,b,c,d)=ab+abc+acd+acd+abcd
F2(A,B,C,D)=
F3(x,y,z)=(x+y)(x+y+z)+y F4(a,b,c,d)=(a+b+c)(a+c)(a+b+c)(a+c+d)
))(.()( CADCBABCA ++++
2. Function Minimization Methods
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2.1 Algebraic Method
2.2 The Karnaugh Map Method
2.3 Quine-McCluskey Method
2.2 The Karnaugh Map Method
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1. Minimum Sum of Product Expressions Using the Karnaugh
Map
2. Dont Cares
3. Product of Sums
4. Minimum Cost Gate Implementation
5. Five- and Six-Variable Maps
6. Multiple Output Problems
Implicant, Prime Implicant
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An implicant of a function is a product term that can be used in a SOP
CD
AB00 01 11 10
00 1 1
01 1
11 1 1 1 1
10
Implicants of F
Minterm Groups of 2 Groups of 4
ABCD ACD AB
ABCD BCD
ABCD ABC
ABCD ABD
ABCD ABCABCD ABD
ABCD
Implicant, Prime Implicant
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A prime Implicant is an implicant which can not be contained
in any other implicants.
CD
AB00 01 11 10
00 1 1 1
01 1 1
11 1 1
10 1 1 1 1
B C
*B D
*B D
A D
A B
C D
Essential Prime Implicant
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Essential PI is a PI which contains at least one minterm which
is not contained in other PI.
CD
AB00 01 11 10
00 1 1 1
01 1 1
11 1 1
10 1 1 1 1
B C
*B D
*B D
A D
A B
C D
minterm 0 is only contained in PI BD
minterm 5 is only contained in PI BD
=> BD & BD are two Essential PI
2.2.1 Minimum Sum of Product Expressions
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Page 109
Rules to minimize using K-map:
Rule 1: Fill K-map cells with corresponding values
Rule 2: Group adjacent cells whose values are 1. Number of cells is 2n.
Rule 3: Each group will be a part of result. Variables in each group will
be excluded: 2n cells => exclude n variables.
2.2.1 Minimum Sum of Product Expressions
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Step 2: Group adjacent cells whose values are 1. Number
of cells is 2n.
CD
AB00 01 11 10
00
011 1
11 1 1
10 1 1
CD
AB00 01 11 10
001 1
01 1 1
11 1 1
10 1 1
2.2.1 Minimum Sum of Product Expressions
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Step 3: Each group will be a part of result. Variables in each
group will be excluded: 2n cells => exclude n variables.
CD
AB00 01 11 10
00
01 1 1
11 1 1
10 1 1
21 cells => eliminate 1 variable
22 cells => eliminate 2 variables
F(A,B,C,D) = ABC + AC
2.2.1 Minimum Sum of Product Expressions
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Example 1: Minimize these functions using K-map:
a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)
b. F(A,B,C,D) = R(1,3,5,8,9,13,14,15)
c. F(A,B,C,D) = R(2,4,5,6,7,9,12,13)
d. F(A,B,C,D)= R(1,3,4,5,7,9,13,14,15)
e. F(A,B,C,D)=R(1,3,4,6,9,11,12,14)
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a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)
= BCD + ABD + BCD + ABD
CD
AB00 01 11 10
001 1
01 11
111 1
101
1
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b. F(A,B,C,D) = R(1,3,4,6,9,11,12,14)
= BD + BD
CD
AB00 01 11 10
00 1 1
01 1 1
11 1 1
101
1
2.2 The Karnaugh Map
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1. Minimum Sum of Product Expressions Using the Karnaugh
Map
2. Dont Cares
3. Product of Sums
4. Minimum Cost Gate Implementation
5. Five- and Six-Variable Maps
6. Multiple Output Problems
2.2.2 Dont care
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If the function has dont care values in cells:
Cells with dont care values
can be grouped with 1 cells
Do not group only dont
care cells in one group.
CD00 01 11 10
00
01
11
10
AB
1 1
1 1
CBCBDCBAF +=),,,(
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2. Function Minimization Methods
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2.1 Algebraic Method
2.2 The Karnaugh Map Method
2.3 Quine-McCluskey Method
2.3 Quine-McCluskey Method
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1. Quine-McCluskey Method for One Output
2. Iterated Consensus for One Output
3. Prime Implicant Tables for One Output
4. Quine-McCluskey for Multiple Output Problems
5. Iterated Consensus for Multiple Output Problems6. Prime Implicant Tables for Multiple Output Problems
2.3. Quine-Mcluskey method
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Karnaugh map cannot handle more than 6 variables.Quine-McCluskey method has no limitation with number of
variables, and is suitable for computer algorithm.
0 1
00
01 111 1 1
10 1 1
ABC
ABC+ABC+ABC+ABC+ABC
010
*10 11* 1*0 1*1 10*
110 111 100 101
1**
find a pair of numbers of 1 bit difference
Quine-Mcluskey Procedure
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1: Represent minterms in binary numbers
2: Group each minterm by the number of 1 appearance
3: Make set of 1 bit different numbers between neighboringgroup
write the difference within parenthesis
mark * to the number which is not included in a set
4: Make set of 1 bit different sets with the same number in aparenthesis
append the difference to parenthesis
mark + to the set which is not included in a set
5: Iterate these step until all the generated set is marked *
6: Select prime implicants
7: Convert to logic variable
S1. Represent minterms in binary numbers
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f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF
+ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF
f = 000000+000010+000110+000111+001110
+001000+101001+001100+001111+001010
f(A,B,C,D,E,F)=(0,2,6,7,14,8,41,12,15,10)
S2. Grouping
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f = 000000+000010+000110+000111+001110+001000+101001+001100+001111+001010
000000
once twice three times
000010001000
000110001100
001010
000111001110
101001
four times
001111
group 0 group 1 group 2 group 3 group 4
group each term by the appearance of 1
no times
S3 & S4. Making set (1)
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000000 0000010 2001000 8
000110 6001010 10001100 12
000111 7
001110 14101001 41
001111 15
0,2 (2)0,8 (8)
2,6(4)
2,10(8)
8,10(2)
8,12(4)
6,7(1)
6,14(8)
10,14(4)
12,14(2)
7,15(8)
14,15(1)
find a pair of 1 bit difference
between neighboring group
write difference within ( )
mark
to the number
not included in any set
group 0
group 1
group 2
group 3
group 4
S3 & S4. Making set (2)
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0,2 (2)0,8 (8)
2,6(4)
2,10(8)
8,10(2)
8,12(4)
6,7(1)
6,14(8)
10,14(4)
12,14(2)
7,15(8)
14,15(1)
0,2,8,10(2,8)
2,6,10,14(4,8)8,10,12,14(2,4)
6,7,14,15(1,8)
mark to the set
not involved
in the next level set
when all the set is marked
finish
Each pair appears in duplicate
find a pair of 1 bit different sets
with the same value in ( )
between neighboring group
append difference within ( )
S6. Selecting Prime Implicants (1)
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41
0,2,8,10(2,8)
2,6,10,14(4,8)
8,10,12,14(2,4)
6,7,14,15(1,8)
0 2 6 7 8 10 12 14 15 41
x x x x
x
x x x x
x x x x
x x x x
If only one x in a column, then the row is inevitable implicant
minterms (given at first)Primei
mplicant
marked
write x into the position where minterm is included
in the prime implicantinevitable
implicant
S6. Selecting Prime Implicants (2)
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41
0,2,8,10(2,8)2,6,10,14(4,8)
8,10,12,14(2,4)
6,7,14,15(1,8)
0 2 6 7 8 10 12 14 15 41
x x x x
x
x x x x
x x x x
x x x x
mini term
prim
eimplicants
mark minterms involved in the
inevitable implicants inevitableimplicants
S7. Conversion to logic variables
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41 101001
0,2,8,10(2,8)
000000
000010
001000
001010
8,10,12,14(2,4)
001000
001010
001100
001110
6,7,14,15(1,8)000110
000111
001110
001111
ABCDEF
ABDF
ABCF
ABDE
F=ABCDEF+ABDF
+ABCF
+ABDE
Examples:
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Page 129
Minimize the following functions using Quine-
Mcluskey method:
a.
b. F(a,b,c,d,e,f) =
(17,21,25,29, 44,45,46,47,49,52,53,54,55,47,61)
fedbafdcbfebcaefdba +++=f)e,d,c,b,F(a,
Quine-Mcluskey method with dont care
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1: Represent logic function in sum of mini terms ==>A
2: Represent dont care in sum of mini terms ==>B
3: If there exist duplication in A and B, remove from A
4: Apply Quine-McCluskey method for A and B
5: Be careful not to include B in selecting prime implicants
Quine-Mcluskey method with dont care
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f=ABCD+BCD+ACD+ABCD+ABCD
dont care AD
mini term
ABCD
0000
00010010
0011
0101
0111
1011
1101
1111
decimal
0
12
3
5
7
1113
15
first comparison second comparison0,1(1)
0,2(2)
1,3(2)1,5(4)
2,3(1)
3,7(4)
3,11(8)
5,7(2)5,13(8)
7,15(8)
11,15(4)
13,15(2)
0,1,2,3(1,2)
1,3,5,7(2,4)
3,7,11,15(4,8)5,7,13,15(2,8)
Quine-Mcluskey method with dont care
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0 2 11 13 15
0,1,2,3(1,2)
1,3,5,7(2,4)
3,7,11,15(4,8)
5,7,13,15(2,8)
xx
x
x
x
x
00**
0**1
**11
*1*1
ABCD
f=AB+CD+BD
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Chapter 3.
Larger Combinational Systems
Introduction
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Logic circuits are divided into two classes:
Combinational logic circuits
Output signals only depend on current input signals
Memoryless circuits
Sequential logic circuits
Output signals not only depend on current input signals, but also
depend on those input signals in the past
Memory circuits
3. Larger Combinational Systems
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples
3.1 Delay in Combinational Logic Circuits
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Delay through logic gates
When the input to a gate changes, the output of that gate doesnt
change immediately; but there is a small delay .
The output is stable after the longest delay path
A
B
C
F
X
3. Larger Combinational Systems
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples
Half Adder
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a b r0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
=a b
r = ab
=1
&
a
b
r
Half Adder
HA
a
b
r
(Result)
(Carry-out)
Addition of two n-bit numbers
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4
3
2
1
0
r3
r2
r1
r0
A = a3
a2
a1
a0
+B = b3 b2 b1 b0
r4
3
r3
2
r2
1
r1
0
Summation
Full Adder
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FAai
ri
bi
i
ri+1
ai
bi
ri
i
ri+1
0 0 0 0 00 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
aibi
ri
00 01 11 10
0 1 1
1 1 1
i
aibi
ri
00 01 11 10
0 1
1 1 1 1
ri+1
i= a
i b
i r
i
ri+1
= aib
i+ r
i(a
i b
i)
Combinational logic circuit design procedure
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Problems: design a combinational logic circuit to do smth.
Design procedure:
S1: Find inputs, outputs and relations.
S2: Construct truth table
S3: For each output, using K-map to minimize from truth table. S4: Draw the circuit.
Example 1
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Problem: Design a combinational logic circuit to implement
this operation: M=N+3, N is 3-bit binary number, the numberof bit of M is selected properly.
Solution:
S1: three inputs: n2n1n0
four outputs: m3m2m1m0
Example 1
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S1: three inputs: n2n1n0
four outputs: m3m2m1m0
S2: truth table
n2 n1 n0 m3 m2 m1 m0
0 0 0 0 0 1 1
0 0 1 0 1 0 0
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 0 1 1 1
1 0 1 1 0 0 0
1 1 0 1 0 0 1
1 1 1 1 0 1 0
S3:
n1n0
n2
00 01 11 10
0 0 0 0 0
1 0 1 1 1
m3
= n2n
0+ n
2n
1
n2
n1
n0
m3
m2
m1
m0
Example 2
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Problem: design a combinational logic circuit to calculate
square of a 2-bit binary number.
Solution:
Step1: find inputs, outputs Inputs: a1,a0
Outputs: b3,b2,b1,b0
Ex2
Example 2
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Step 2: truth table
Step3: using K-map to minimize outputs
b3 = a1.a0 b1 = 0
b2 = a1.a0 b0 = a0
a1 a0 b3 b2 b1 b0
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 1 0 0
1 1 1 0 0 1
Example 2
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Step 4: Draw circuit
b3 = a1.a0 b1 = 0
b2 = a1.a0 b0 = a0
a1
a0
b3
b2
b1
b0
U1A
7408N
U1B
7408N
U2A
7404N
X1
2.5 V
X2
2.5 V
X3
2.5 V
X4
2.5 V
R1
100
V15 V
J1
Key = A
R2
100
V212 V
J2
Key = B
Full Adder
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=1
&
ri
ai
bi
=1
&
i
ri+1 1
Full Adder
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=1
&
ri
ai
bi
=1
&
i
ri+1 1
HA HA
n-bit Adder
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Serial n-bit adder
A = an-1an-2...a1a0 , B = bn-1bn-2...b1b0
FA
an-1 bn-1
rn-1
rn
n-1
FA
an-2 bn-2
rn-2
n-2
FA
a1 b1
r1
r2
1
FA
a0 b0
r0= 0
0
n
Delay = n x ?
n-bit Adder
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Parallel n-bit adder:
ri+1
= aib
i+ r
i(a
i b
i)
Pi= a
i b
iand G
i= a
ib
i ri+1 = Gi + ri Pi
r1 = G0 + r0P0
&
1G0
P0
r0
r1
1
2
r2
= G1
+ G0P
1+ r
0P
0P
1
&
1G1
G0
P1
r2
&P0r0
Parallel 4-bit addition
b b b b
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r4 = 4 3 2 1 0
r2 r1
a2 b2 a1 b1 a0 b0
P3 G3 P2 G2 P1 G1 P0 G0
Calculate Pi and Gi
a3 b3 a2 b2 a1 b1 a0 b0
Carry calculation
Sum calculation
r0
a3 b3
r3r4
r0
Subtractor
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To subtract a-b, simply add a to 2s complement ofb.
Second choice:
Half Subtractor => Full Subtractor => n-bit Subtractor
Subtractor
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Subtractor by using 2s complement
A3A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0
1C1C2C3
C4
A B
C
S
C+ FAA B
C
S
C+ FA
A B
C
S
C+ FA
A B
C
S
C+ FA
Adder and Subtractor
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C1C2C3C4
A B
C
S
C+ FAA B
CS
C+ FA
A B
CS
C+ FA
A B
CS
C+ FA
MPX MPX MPX MPX
A3 A2 A1 A0B3 B2 B1 B0
S3 S2 S1 S0
sel
3. Larger Combinational Systems
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples
Decoder
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An nxm decoder is a combinational circuit that converts
binary information from n input lines to m output lines, wherem2n.
m = 2n => complete decoder
Fundamental property: only one output is 1 for any given
input combination.
Decoder
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Complete decoders: m=2n
Eg:+ 3 bit inputs x1,x2,x3.
+ 8 bit outputs Y0,Y1Y7
nxmdecoder..
....
x1
x2
xn
D0
D1
Dm-1
E
3x8decoder ...
x1
x2
x3
D0
D1
D7
Design 3x8 decoder
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3x8
decoder ...
x1
x2
x3
D0
D1
D7
En
if (En=0)
Disable or D0...D7=0else if (En=1)
Function as a 3x8 decoder
BCD-to-decimal decoder
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BCDtodecimalDecoder
ABCD
Y0
Y1
Yi
Y9
:
:
N A B C D Y0
Y1
.
.Y
9
0 0 0 0 0 1 0 ..
0
1 0 0 0 1 0 1 ..
0
2 0 0 1 0 0 0 .
.
0
3 0 0 1 1 0 0 ..
0
4 0 1 0 0 0 0 ..
0
5 0 1 0 1 0 0 ..
0
6 0 1 1 0 0 0 ..
0
7 0 1 1 1 0 0 ..
0
8 1 0 0 0 0 0 ..
0
9 1 0 0 1 0 0 . 1
BCD-to-decimal decoder
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= =0 1Y A B C D Y A B C D
=2Y BCD
=
=
=
=
=
=
=
3
4
5
6
7
8
9
Y BCD
Y BC D
Y BC D
Y BC D
Y BCD
Y AD
Y AD
CD
AB00 01 11 10
00 1
01
11 10
Decoder
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4x16 decoder using two 3x8 decoders
3x8
decoder ...
x2
x3
x4
D0
D1
D7
3x8decoder ...
x1D8
D9
D15
Decoder implementation of arbitrary functions
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4x16
decoder
x2
x3
x4
D0D1D2
x1
D3D4D5D6D7
D8D9D10D11D12
D13D14
D15
F1
F1(x1,x2,x3,x4)=(0,1,3,8,12)
BCD-to-7segment decoder
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a
b
c
d
e
f g
Each segment is a LightEmitting Diode (LED)
KA
N A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
BCD-to-7segment decoder
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CD
AB
00 01 11 10
00 1 0 1 1
01 0 1 1 1
11 10 1 1
= + + +a A C BD B D
&
&
B
D
1A
C
3 1 D l i C bi ti l L i Ci it
3. Larger Combinational Systems
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples
Encoder
A d i i it th t f th f ti f d d i
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An encoder is a circuit that performs the function of a decoder in reverse.
An mxn encoder has m inputs, n outputs where m2n. The outputsgenerate the binary codes corresponding to m inputs.
For example: encoder for PCs keyboard
Key Character Key code102 keys, 8 bit ASCII
Keyboard encoder
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9 keys
4-bit key code.
1
2
i Encoder
9
P2
P1
Pi
A
B
C
D
N=i
1
P9
Keyboard encoder
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A = 1 if (N=8) or (N=9)
B = 1 if (N=4) or (N=5) or (N=6)or (N=7)C = 1 if (N=2) or (N=3) or (N=6)
or (N=7)D = 1 if (N=1) or (N=3) or (N=5)
or (N=7) or (N=9)
N ABCD
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Keyboard encoder
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1
1
1
1
N=9
N=8
N=7
N=6
N=5N=4
N=3
N=2
N=1
A
B
C
D
3 1 D l i C bi ti l L i Ci it
3. Larger Combinational Systems
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders
3.5 Multiplexors
3.6 Demultiplexors
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples
Multiplexor
Multiplexor has one output and more than one input
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Multiplexor has one output and more than one input.
Function: select one of input for output
X0
X1
C0
Y
MUX 2-1
C0 Y
0 X0
1 X1
C1
C0
Y
0 0 X0
0 1 X1
1 0 X2
1 1 X3
control inputs
X0
X1
X2
X3
C0
C1
Y
MUX 4-1
2-to-1 Multiplexor
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X0
X1
C0
Y
MUX 2-1
C0
Y
0 X0
1 X1
= +0 0 1 0Y X C X C
X1X0C0
00 01 11 10
0 1 1
1 1 1
C0
X1
X0
Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
2-to-1 Multiplexor
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4-to-1 Multiplexor
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Y = s1s0I0 + s1s0I1 +s1s0I2+ s1s0I3
Application of multiplexor
Select source
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Select source
Source 1 Source 2
Receiver
Y3 Y2 Y1 Y0
A = a3 a2 a1 a0 B = b3 b2 b1 b0
C0
Application of multiplexor
Convert parallel serial
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Convert parallel-serial
a0
a1
a2
a3
C0
C1
Y
a0 a1 a2 a3
Y
C1
C0
0
1
0
1
t
t
t
A
Application of multiplexor
Implementation of arbitrary functions:
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Implementation of arbitrary functions:
= + + +f(A,B) A Bf(0,0) A Bf(0,1) A Bf(1,0) A Bf(1,1)
= + + +1 0 0 1 0 1 1 0 2 1 0 3Y C C X C C X C C X C C X
x0
x1
x2
x3C1 C0
f(0,0)
f(0,1)
f(1,0)
f(1,1)
A
B
Y = f(A,B)Inputs toselectfunction
Variables
Example
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F(A,B) = AB + AB
x0
x1
x2
x3C1 C0
0
1
1
0
A
B
Y = f(A,B)Inputs toselectfunction
Variables
3. Larger Combinational Systems
3 1 Delay in Combinational Logic Circuits
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders and Priority Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples
Demultiplexor
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Demultiplexor has one input and more than one output Function: select one of outputs for input
E
C0
S0
S1
ECS
ECS
01
00
=
=
DeMUX 1-2
Demultiplexor 1-4
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E
C1
C0
S0
S1
S2
S3
3 1 Delay in Combinational Logic Circuits
3. Larger Combinational Systems
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders and Priority Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples
3.7 Three-State Gates (Tristate)
Three state gates exhibit three states instead of two states
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Three state gates exhibit three states instead of two states.
The three states are: High : 1
Low : 0
High impedance : z
In this state the output is disconnected which is equal to open circuit.In the other words in that state circuit has no logic significant. We can
have AND or NAND three-state gates but the most common is three-
state buffer gate
3.7 Three-State Gates (Tristate)
We may use conventional gates such as AND or NAND as
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We may use conventional gates such as AND or NAND as
three-state gates but the most common is three-state buffergate.
Note that buffer produces transfer function and can be used
for power amplification. Three state buffer has extra input
control line entering the bottom of the gate symbol (see nextslide)
Three-State buffer
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Three-state buffer
C A Y
----------------------
0 0 z
0 1 z
1 0 0
1 1 1
Application of three-state buffer
Three-state buffers can be used to implement
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Three state buffers can be used to implement
multiplexer
3. Larger Combinational Systems
3.1 Delay in Combinational Logic Circuits
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3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders and Priority Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays - ROMs, PLAs and PALs3.9 Larger Examples
3.8 Gate Arrays - ROM, PLA and PAL
PLA - Programmable Logic Arrays
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PLA Programmable Logic Arrays
PAL - Programmable Array Logic
ROM
PLA - Programmable logic arrays
Pre-fabricated building block of many AND/OR gates
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Pre fabricated building block of many AND/OR gates
actually NOR or NAND
"personalized" by making or breaking connections among the gates
programmable array block diagram for sum of products form
inputs
AND
array
outputs
OR
arrayproductterms
A B C Z1 Z2
0 0 0 0 0 1
1 0 0 1 0 0
2 0 1 0 1 1
3 0 1 1 0 0
4 1 0 0 0 15 1 0 1 1 0
6 1 1 0 1 1
7 1 1 1 1 0
Before programming
All possible connections are available before "programming"
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p p g g
in reality, all AND and OR gates are NANDs
After programming
Unwanted connections are "blown"
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fuse (normally connected, break unwanted ones)
anti-fuse (normally disconnected, make wanted connections)
A B C
F1 F2 F3F0
AB
B'C
AC'
B'C'
A
PLA example
Multiple functions of A, B, C
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F1 = A B C F2 = A + B + C
F3 = A' B' C'
F4 = A' + B' + C'
F5 = A xor B xor C F6 = A xnor B xnor C
A B C F1F2F3F4F5 F60 0 0 0 0 1 1 0 00 0 1 0 1 0 1 1 1
0 1 0 0 1 0 1 1 10 1 1 0 1 0 1 0 01 0 0 0 1 0 1 1 11 0 1 0 1 0 1 0 01 1 0 0 1 0 1 0 01 1 1 1 1 0 0 1 1
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'ABC
A B C
F1 F2 F3 F4 F5F6
full decoder as for memory addresbits stored in memory
PALs and PLAs
Programmable logic array (PLA)
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what we've seen so far unconstrained fully-general AND and OR arrays
Programmable array logic (PAL)
constrained topology of the OR array
innovation by Monolithic Memories
faster and smaller OR plane
a given column of the OR arrayhas access to only a subset of
the possible product terms
ROM Read Only Memories
Two dimensional array of 1s and 0s
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entry (row) is called a "word" width of row = word-size
index is called an "address"
address is input
selected word is output
decoder
0 n-1
Address
2 -1
n
0
1 1 1 1
word[i] = 0011
word[j] = 1010
bit lines (normally pulled to 1 throughresistor selectively connected to 0by word line controlled switches)
j
i
internal organization
word lines (only oneis active decoder is
just right for this)
Example:10 address x 8 data ROM210 words x 8 ROM1024 words x 8 ROM1k x 8 ROM
ROM Read Only Memories
Combinational logic implementation (two-level canonical
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F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
truth table
A B C F0 F1 F2 F30 0 0 0 0 1 00 0 1 1 1 1 00 1 0 0 1 0 00 1 1 0 0 0 11 0 0 1 0 1 11 0 1 1 0 0 01 1 0 0 0 0 11 1 1 0 1 0 0
block diagram
ROM8 words x 4 bits/word
address outputsA B C F0 F1 F2 F3
g p (
form) using a ROM
ROM structure
Similar to a PLA structure but with a fully decoded AND array
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y y
completely flexible OR array (unlike PAL)
n address lines
inputs
decoder 2n word
lines
outputs
memory
array(2n words
by m bits)
m data lines
3. Larger Combinational Systems
3.1 Delay in Combinational Logic Circuits
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3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders and Priority Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs3.9 Larger Examples
3.9 Larger Examples
1. Seven-segment displays
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2. Comparator
Comparator
1-bit full comparator:
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1-bit full comparator:
1bit
Full
Comparator
ai
bi
Gi
Li
Ei
iii
iii
iii
baEbaL
baG
=
=
=
.
.ai > bi Gi=1
ai < bi Li=1
ai = bi Ei=1
Comparator
N-bit parallel comparator:
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Midterm examination (90)
1. Represent the following function in the canonical form SOP:
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F(A,B,C)=(A+B)C
2. Use the Quine-McCluskey method to obtain the minimal sum for thefollowing function:
F(A,B,C,D,E)= (1,4,6,7,8,9,10,11,15)
3. Design 4x16 decoder using only 2x4 decoders.
4. Design a combinational logic circuit to calculate the following function:M=N+3 where N is BCD number (Binary-Coded Decimal).
Midterm examination 2 (90)
1. Represent the following function in the canonical form SOP and POS:
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F(A,B,C)=C
2. Use the Quine-McCluskey method to obtain the minimal sum for thefollowing function:
F(A,B,C,D,E)= (1,4,6,7,8,11,12,13,15)
3. Using 3x8 decoder to implement the following function:
F(A,B,C) = AB + BC
4. Design a combinational logic circuit to calculate the following function:M=N+5 where N is BCD number (Binary-Coded Decimal).
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Chapter 4.
Sequential Systems
4. Sequential Systems
4.1 Definitions
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4.2 State Tables and Diagrams
4.3 Latches and Flip Flops
4.4 Analysis of Sequential Systems
4.5 Design of Sequential Systems
4.6 Solving Larger Sequential Problems
4.1 Definitions
Combinatorial circuit is memoryless.
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In a circuit with memory, an output value at tn+1 must be a
function not only of the inputs at tn+1 but also of the outputs at
tn.
To achieve this, the circuit must have some feedback
connections from its outputs to its inputs.
A circuit with memory is a combinatorial circuit
incorporating some feedback connections.
Feedback and memory devices
To implement feedback, signals are fed back from outputs to
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inputs using memory devices.A memory device stores an output value at time tn so that it
can be input to the circuit at tn+1.
But then, output at tn depends on input at tn-1, which in turn
depends on tn-2
The circuit maps input sequences to output sequences
Sequential circuit model
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Circuits with memory are called sequential circuits.
Combinatorial
circuit
.
.
.
x1
x2
xn
.
.
.
z1
z2
Memorydevice
Memory
device
..
.
Yk
Y1
yk
y1
Circuit inputs Circuit outputs
Present state Next state
Sequential circuit model
Mealy model:
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X : finite inputs. m inputs: x1,x2...,xm
S : finite states. n states: s1,s
2...,s
n
Y: finite outputs.l outputs: y1,y
2...,y
l
Fs: state function. s = Fs(X,S)
Fy : output function. y = Fy(X,S)
Moore: ~Mealy
Difference: Fy = Fy(S)
Asynchronous/Synchronous sequential circuits
The timing of the signal in the circuit determine two types of
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sequential circuits: Synchronous
Asynchronous.
Synchronous sequential circuits
In a synchronous sequential circuit, the state can change onlyat
discrete instants of time
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discrete instants of time.
To achieve that, the circuit uses a timing device, called a clock
generator, that produce trains of periodic or aperiodic clock pulses.
The clock pulses are input to the memory devices so that they can
change state onlyin response to the arrival of a pulse and only
once for each pulse occurrence.
The operation of the circuit is synchronized with the clock pulse input.
Asynchronous sequential circuits
The behavior of an asynchronous sequential circuit depends
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onlyon the order in which the inputs change and can beaffected at any instant of time.
There is no timing device in asynchronous sequential circuit
(unclocked memory).
4. Sequential Systems
4.1 Definitions
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4.2 State Tables and Diagrams
4.3 Latches and Flip Flops
4.4 Analysis of Sequential Systems
4.5 Design of Sequential Systems4.6 Solving Larger Sequential Problems
State diagram
Depict graphically the operation of a sequential circuit.
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Mealy state diagram
a b c d0/0 1/0 0/0
0/00/0
1/0 1/1
Example of state diagram
Example: a sequential circuit is used to detect the string
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A B C D0 / 0
1 / 00 / 0
1 / 0
1 / 0
0 / 0
0 / 0
1 / 1
0101 from one input.
State diagram
Depict graphically the operation of a sequential circuit.
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Moore state diagram
a/0
b/0
c/0
d/0
e/1
f/1
01 0
0
0
0
1
1
1
1
1
State table
State table presents in a tabular form the same information
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contained in the state diagram. Mealy state table
Moore state table
Mealy state table
0/00/0
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PS NS Output (z)
x=0 x=1 x=0 x=1
a b a 0 0
b b c 0 0
c d a 0 0
d b c 0 1
PS NS/Output (z)
x=0 x=1
a b/0 a/0
b b/0 c/0
c d/0 a/0
d b/0 c/1
PS: Present StateNS: Next State
k memory devices => 2k rows
n circuit inputs => NS portion contains 2n columns
Output portion also contains 2n columns
a b c d0/0 1/0 0/0
1/0 1/1
Moore state table
1
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PS NS Output
x=0 x=1 z
a b a 0
b b c 0
c d c 0
d d e 0
e f e 1
f f a 1
The output portion always contains a single column.
The entry at the intersection of any row with the output column indicates the
output values corresponding to the PS associated with that row.
a/0
b/0
c/0
d/0
e/1
f/1
01 0
0
0
0
0 1
1
1
1
Incompletely specified Mealy state table
Two inputs: x1,x2
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A single output: z
PS NS/Output (z)
00 01 11 10a -/- c/1 b/- e/1
b e/0 -/- -/- -/-
c f/0 f/1 -/- -/-
d a/- -/- e/- b/1
e -/- f/0 d/1 a/0
f c/0 -/- c/1 b/0
4. Sequential Systems
4.1 Definitions
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4.2 State Tables and Diagrams
4.3 Latches and Flip Flops
4.4 Analysis of Sequential Systems
4.5 Design of Sequential Systems4.6 Solving Larger Sequential Problems
4.3. Latches and Flip-Flops
Simplest memory devices: Delay element
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TYi yi
yi(t+T) = Yi(t)
T
Yi
yi
In practice, we dont have to actually insert delay elements
because propagation time delays between the inputs and
the outputs of the combinatorial part of the circuit provide
sufficient delay across the feedback loops.
4.3. Latches and Flip-Flops
Bistable devices:
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Two stable states: Q=0 : the device is reset(reset state)
Q=1: the device is set(set state)
A bistable device remains in one of two states indefinitely until directedby an input signal to change state.
Two types:
Latch
Flip-flop
4.3. Latches and Flip-Flops
Latch: transparency property:
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Change state when the input values change The new output state is delayed only by the propagation time delays of
the gates between inputs and outputs of the latch.
Used to implement the memory part of asynchronous circuits.
Flip-flop: no transparency property
Has a control (triggering) input, called clock.
The state change only in response to a transition of a clock pulse atclock input.
Used to implement memory part of synchronous circuits
SR Latch
Two inputs: S (set), R (reset)
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Two complementary outputs: Q, Q
S Q
R Q
Q
Q'
S
R
S R Q Q+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 -
1 1 1 - Indeterminate
Next state
Current state
Q = (R+Q)
Q= (S+Q)
SR Latch S Q
R Q
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Q
Q'
S
R
S R Q+
0 0 Q
0 1 0
1 0 1
1 1 Indeterminate
Equivalent characteristic table
SR=00 => Output no change
A logic 1 at inputs can change outputs states=> active-HIGH latch
SR Latch
S Q
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S Q
R Q
Q
Q'
S
R
active-HIGH SR Latch
S Q
R Q
S
R
Q
Q'
active-LOW SR Latch
SR Latch
Timing chart (NOR implementation)
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S
R
Q
Qset reset resetset
Q
Q'
S
R
SR Latch
Timing chart (NAND implementation)
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Q
Q
S
R
set reset set reset
S
R
Q
Q'
SR Latch
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R
S
Q
Circuit showing feedback
Q+ = RQ + RS
SR=0 => Q+ = RQ + RS + RS = RQ + S
for active-HIGH SR Latch
Q Q+ S R
0 0 0 -
0 1 1 0
1 0 0 1
1 1 - 0
Excitation table
D Latch
D
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D Q
Q
S Q
R Q
D Q*
0 0
1 1
Q Q* D
0 0 0
0 1 1
1 0 0
1 1 1
Graphic symbol Implementation using SR Latch
Equivalent characteristic table
Excitation tableQ* = D
Gated Latches
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S QE
R Q
S
R
Q
Q'
E
E: Enable input control
The latch will not change state as long as E=0
E=1 SR=10 => Set
E=1 SR=01 => Reset
The operation of latch is synchronized
with the E input => E: synchronous input
A latch with synchronous input is called
gated latch.
Flip-flops
Latches implement memory part in asynchronous sequentialcircuits
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Flip-flops do the same for synchronous circuits. FF has clockinput and changes state synchronously with clock.
Four common types of flip-flops: SR
D
JK
T
SR flip-flop
S Q S Q S Q
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The triangle called dynamic indicator, indicates that thedevice responds only to an input clock transition from LOW(0) to HIGH (1) => Positive edge-triggered
Appending a small circle to the CLK input indicates that theflip-flop responds only to an input clock transition from HIGH(1) to LOW (0) => Negative edge-triggered
CLK
R Q
CLK
R Q
CLK
R Q
Positive edge-triggered Negative edge-triggered Pulse-triggered
(Master-Slave)
SR flip-flop
The information is entered on the leading edge of
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the clock pulse, but the flip-flop does change state(the output is postponed) until the trailing edge of
the clock pulse.
S QCLK
R Q
Pulse-triggered(Master-Slave)
Difference between Latch and Flip-flop?
The flip-flop can not change state except on thetriggering edge of clock pulse => synchronous
Present and next states in a latch are separated
In time by gate delays, they are separated by clock
periods in a flip-flop.
SR flip-flop
Next stateCurrent state
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S R Q Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 01 0 0 1
1 0 1 1
1 1 0 -
1 1 1 -
Indeterminate
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Indeterminate
Characteristic table
Reduced characteristic table
Q Q(t+1) S R
0 0 0 -
0 1 1 0
1 0 0 1
1 1 - 0
Excitation table
Q(t+1)= RQ(t) + S(S=1 & R=1) is inhibited
Implementation of SR-FF
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CL
S
Q
R
Q
Q
Q
S
R
SR-latch
Q
Q
CL
S
R
Implementation of SR-FF by SR-Latch
SR flip-flop
Timing chart
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Q
Q
S
R
CL
S Q
CLK
R Q
D flip-flop
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D flip-flop is useful for storing a single bit
D QCLK
Q
S QCLK
R Q
D
CLK