meljun cortes handouts sequential logic

8/8/2019 MELJUN CORTES HANDOUTS Sequential Logic

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Sequential Logic

LogicDesignand Switching

* Property of STI

Page1of 63

physically implemented by the sequent ia l

circuit

Sequential Circuit

a type of circuit whose output depends not only

on its inputs’ present state, but also its previousinputs

made up of not only of the basic combinational

circuits but also of storage elements

classified according to the timing of its signals

Block Diagram of the Sequential Circuit

SequentialLogic

Source: Mano, “DigitalDesign”

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has to be synchronized by making it follow a

timing device called the clock generator orsimply, the clock

Clock

produces a periodic train of clock pulses fromwhich the required changes in the storage

devices are timed

Clock Pulses

are timed pulses of high and l ow-logic levelelectric signals

Clock Pulses

SynchronousSequential Logic

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observes its inputs and internal states only at

certain, discrete points in time

Asynchronous Sequential Circuit

observes the behavior of its inputs at any

instance of time, as well as the order in which

these inputs change in continuous time

Block diagrams of Synchronous Sequential

Circuit

SynchronousSequential Logic

Source: M. Mano, ”Logicand Computer DesignFundamentals”, 2nded updated

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the basic storage element from which flip-flops

are usually constructed

as long as there is electricity powering this

circuit, it holds and mainta ins the binary state

fed to it

asynchronous in nature

they do not need to be clocked to function

properly

digital circuit that has two outputs that should

always be at opposite states

digital circuits that have two outputs (commonlynamed as Q’ and Q ) that should always be at

opposite states

Types of Latches:

the SR (and S’R’ )

D latches

Latches

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also called an RS latch

The SR Latch from Two Cross-Coupled NOR

Gates

short for SET-RESET

has its output determined by:

its present state

triggering of its SET or RESET input line

the two NOR gates used in implementing the

latch are defined by the following equations:

NOR gate A

NOR gate B

Crossed-NORSR Latch

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resetting the output Q to 0

an unused or undefined state

Crossed-NORSR Latch

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Sequential Logic


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S = 1 and R =0:

NOR gate A the set state

by Boolean simplification, this becomes:

NOR gate B an unchanged state

Crossed-NORSR Latch

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another unchanged state of the SR latch

Function Table for SR Latch:

Crossed-NORSR Latch

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Sequential Logic


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the S’R’ or SET’ RESET’ latch

very much like the SR latch except that this is

act ive low

the SET’ input must be at logic 0 to set the output

Q to logic 1

The S’R’ Latch and its implementation using

NAND Gates

Cross-NANDS’R’ Latch

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unchanged statewhen outputs are set

unchanged state whenoutputs are reset

unused state when

both inputs are logic 0

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setting the Q output for the cross-NAND S’R’ latch

resetting


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Function Table for SR Latch:

their inputs are complements of each other in

producing the same output

different in the values of the outputs during an

unused state

crossed-NAND inputs: active low

cross-NOR inputs: active high


Comparison of theSR and S’R’ Latches

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Sequential Logic


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symbol of the Gated SR Latch

circuit construction of the Gated SR Latch

The GatedSR Latches

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an improvement over the clocked-SR (or gated-

SR) latch in the sense that it prevents theproblem when both the inputs are logic 1

has only two inputs: the input D and the CLK

enable

The D latch symbol and construction using NAND

Gates

TransparentD Latch

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The GatedSR Latches

setting the output Q

with CLK enabled

output Q is not reset

even with S=0 and R =1

because CLK is inhibited

Function Table for Gated SR Latch:

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CLK is enabled and the input D sets the output Q to

logic 1

CLK is enabled and the input D sets the output Q tologic 0s

TransparentD Latch

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CLK is inhibited and the output Q is not changed

TransparentD Latch

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Function Table for the D Latch with 0

Control:

TransparentD Latch

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Function Table for the D Latch with 1

Control:

derives its name form its ability to hold data

it is called transparent because the informationat the data line is transparent and can be seen

directly from the output as long as the CLK isenabled

D latch with 0 control symbol and constructionusing NOR gates

TransparentD Latch

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the timing diagram of a D latch

Examples

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How the Timing iagram of a Latch works:

Part 1:

Since the CLK is at logic 1 (HIGH), the value of

D is LOW; D should just be transferred to the

output Q. The output of Q’ should just be the

opposite of the Q value for all cases.

Part 2:

There is a transition of logic level of the D input

from LOW to HIGH. However, the CLK is still atHIGH. This means that there should also be a

transition of the Q output from LOW to HIGH.

Examples

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Given the timing diagram below, determine the

output waveform for an SR latch.

Solution:

Example 1

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How theTiming iagram

of aLatch

works(cont.):

Part 3:

There is a transition of the CLK input to LOW.

This means that any other change in the input D

will not affect the output. The output Q and Q

are therefore maintained at their respectivevalues.

Part 4:

Although D goes down to LOW, the output is

still latched to HIGH since CLK is still LOW.

Part 5:

The value of D goes up to HIGH but the CLK is

still LOW. The outputs are not affected by the

input’s transition and they remain the same.

Examples

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Solution (cont.):

the timing diagram corresponds to the high and low

logic levels of the SR latch’s function table

Example 1

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Sequential Logic


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Draw the waveform of the outputs for a gated

SR latch given the inputs below.

Solution:

Example 2

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the basic element for storing binary information

in synchronous sequential circuits

made up of latch circuitry

D latch is triggered as long as the clock is enabled

Block diagram of the sequential circuit using a latch

as storage

Flip-Flop

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Solution (cont.):

The gated SR latch can only function if the CLK

input is HIGH. When the CLK is LOW, the

outputs will not change whatever the value of

the S and R inputs are (hence the don’t caresymbol in then function table). Therefore, we

need only consider the instances when the CLK

is at logic 1.

Example 2

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eliminates the problem associated with the

propagation of the state of the input of simple

latches for storing information

two SR latches may be combined to form a

master-slave configuration

Master-Slave SR Flip-Flops

Master-SlaveFlip-Flops

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Second Latch

gives the final output of the flip-flop

1. When the CLK is triggered, the master stage is

activated and is immediately affected by the

inputs S and R . The values of the S and R arestored in the master SR latch.

2. When the CLK is driven to logic 0, the output of

the inverter is logic 1 and the slave stage istriggered.

3. Since the slave and master are connected while

the slave is triggered, the outputs Q and Q’ are

simply the values of the A and A’ master

outputs.

4. When CLK is again triggered, the master is

enabled while the slave is inhibited.


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made to avoid the unreliable operation that is

possible for ordinary SR master-slave flip-flops

when the J and K inputs of the flip-flop are bothlogic 1, the outputs are simply complemented

The JK flip-flop symbol and master-slaveimplementation

The JK Flip-Flop

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Timing Diagram of the SR Master-Slave

Flip-Flops with Time Delays


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When both inputs of JK and the SR master -

slave f l ip- f lops are 1, three th ings h appen:

1. When the flip-flop is presently operating

normally, the outputs are complemented. For

example, Q = 1 while Q’ = 0.

The JK Flip-Flop

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Sequential Logic


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2. When the CLK is triggered, the master SR latch

is either SET or RESET since its inputs areguaranteed to be complementary and the exact

opposite the flip-flop’s output values.

The JK Flip-Flop

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Function Table for the JK Flip-Flop:

Master-slave flip-flops are sometimes called pulse-

tr iggered f l ip- f lops :

the master latch continues to get the inputs until

the CLK is inhibited

The JK Flip-Flop

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3. After the CLK pulse stops triggering, the slave

will now get the value from the master’s outputs.

The JK Flip-Flop

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Consider the following illustration of a JK flip-

flop’s slave SR latch:

1. When the present state of Qn is logic 0 (and Qn’

logic 1), and given the following instance from

its timing diagram:

The JK Flip-Flop

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2. Consider the case when the input to the S line

is delayed internally in the latch. An immediateobservation is that the output Qn+1 is in error.

The JK Flip-Flop

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are employed when time delays and unreliable

oscillations are present in a sequential circuit

triggers only during the t ransit ion of the CLKsignal and ignores the pulse when it is at a

constant level (whether it is HIGH or LOW)

Edge-TriggeredFlip-Flops

Two Types:

1. Posit ive edge or leading

edge or r ising edge triggering occurs during the

LOW-to-HIGH transition

2. Negative edge or t ra i l ingedge or fa l l ing edge

triggering occurs during theHIGH-to-LOW transition

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The pulse-triggered flip-flop is susceptible totwo problems:

1. as long as the CLK is triggered HIGH

(intentional or not), the inputs are processed

and recognized by the outputs

2. long delays will cause the S and R lines of the

latches inside the flip-flop to change during aclock pulse

The JK Flip-Flop

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D-type trailing edge-triggered flip-flop

an example of a negative edge-triggered flip-

flop implementation

constructed by using a D latch, a gated SR

latch, and connected using an inverter

Trailing Edge D-Type Flip-Flop Implementation


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1. When the clock is at logic 1, the master D latch

is turned on and the output at A will follow thevalue of the input D.


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Function table for the trailing edge D-type

flip-flop:


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2. When the negative transition from logic 1 to

logic 0 takes place, the master D latch is turned

off but the slave transfers the value from its

inputs to the output.


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Leading Edge D-Type Flip-Flop Implementation

Function Table for the Leading Edge D-Type

Flip-Flop:


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Symbols for Latches and Flip-Flops

A Summary of theDifferent Flip-Flops

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T flip-flop

it toggles the output when it is activated

whenever its input becomes logic 0, the outputis toggled or complemented

T Flip-Flop from a JK Flip-Flop


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Function Table for the SR Flip-Flop:

Function Table for the JK Flip-Flop:

Flip-FlopFunction Tables

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A Sequential Circuit

Input Equat ions

Y = (BC)’

D x = ( AB)’+ (BC )’ + X’

CircuitAnalysis

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Function Table for the D Flip-Flop:

Function Table for the T Flip-Flop:

Flip-FlopFunction Tables

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State Table

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4 steps to come up with the state table:

1. List all possible combinations of the present

states and inputs in order. The present state is

the output of the flip-flops.

2. If there are outputs coming directly from logicgates present, write down their output

equations. Continue with step 2, making

another column for each flip-flop used.

3. If there are outputs coming directly from logic

gates present, write down their output

equations.

4. Get the respective values of the next state from

the input and present state combinations. Wewill use the flip-flop characteristics we have

discussed to evaluate the next state of the flip-

flop.

State Table

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Solution:

Input Equat ions

JK flip-flop: J x = AX + (AB)’

K x = (BZ)’

D flip-flop: Dy = (BZ)’

NAND-gate: Z = (AB)’

State Table for Example 3:

Example 3

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Derive the state table given the logic diagram

below:

Example 3

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an alternative way to represent the states in a

sequential circuit

more intuitive for human interpretation

represented by circles -the more flip-flops there

are for a certain circuit, the more circles are

needed

State Diagram from the State Table for Example 3

State Diagram

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Derive the state table given the logic diagram

below:

Solution:

Input Equat ions

D flip-flop: D x = (AY + AX’)’

NAND-gate: Y = AX’

Example 4

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The next state Xn+1 results from following the

input equation for the D-type flip-flop

The state diagram is directly derived from theabove state table

Example 4

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Write down the state table by enumerating the

present state and input

Evaluate the value of the output Y from the

AND-gate equation

Example 4

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State Equation

may be directly derived from the state table of a

sequential circuit

consists of simple Boolean expressions for the

output combinational circuit using the sum of

minterms, with the left-hand side of the equation

containing the output variable

State Table for Example 4:

Design and Synthesisof Sequential Circuits

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State Equat ions:

Z (A,X,Y ) =S(1,2,4,6)

D X (A,X,Y ) =S(2,5,6)

D Y (A,X,Y ) =S(0,2,3,4,6)

K-Map Simplification for the State Equations


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The simplified state equations are therefore:

Z = A’ • X’ •Y + XY’ + A•Y’ = A’X’Y + (A+X ) Y’

D X = AY + A’XY’

D Y = Y’ + A’X

Logic Diagram of the Sequential Circuit


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K-Map Simplification for the State Equations


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