marvell - storage - 88se9445 datasheet · 2020-02-07 · marvell. marvell retains the right to make...

Doc No. MV-S105602-00 Rev. E

April 6, 2015

Document Classification: ProprietaryMarvell. Moving Forward Faster

88SE9445 R3.3Four-Lane PCI-Express 2.0 to Four-Port SAS/SATA 6 Gbps RAID I/O Controller

Preliminary Datasheet

88SE9445 R3.3 Four-Lane PCI-Express 2.0 to Four-Port SAS/SATA 6 Gbps RAID I/O Controller

No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information.

Copyright © 1999–2015. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, Kinoma, Link Street, LinkCrypt, Marvell logo, Marvell, Moving Forward Faster, Marvell Smart, PISC, Prestera, Qdeo, QDEO logo, QuietVideo, Virtual Cable Tester, The World as YOU See It, Vmeta, Xelerated, and Yukon are registered trademarks of Marvell or its affiliates. G.now, HyperDuo, Kirkwood, and Wirespeed by Design are trademarks of Marvell or its affiliates.

Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.

For more information, visit our website at: www.marvell.com

ii

Copyright © 2015 Marvell Doc No. MV-S105602-00 Rev. EApril 6, 2015 Document Classification: Proprietary

http://www.marvell.com


Ordering Information

iii


ORDERING INFORMATION

Ordering Part Numbers and Package Markings

The following figure shows the ordering part numbering scheme for the 88SE9445 part. For complete ordering information, contact your Marvell FAE or sales representative.

Sample Ordering Part Number

The standard ordering part numbers for the respective solutions are indicated in the following table.

The next figure shows a typical Marvell package marking.

88SE9445 Package Marking and Pin 1 Location

Ordering Part Numbers

Part Number Description

88SE9445C3-BMJ2C000 481-Ball TFBGA 19 × 19 mm

This product does not support Marvell RAID stack.

Part Number

Product Revision

Custom Code

Custom Code(optional )

88XXXXX - XX - XXX - C000 - XXXX

Temperature CodeC = CommercialI = Industrial

Environmental Code + = RoHS 0/6–= RoHS 5/61 = RoHS 6/62 = Green)

Package Code3-character

alphabetic code such as BCC, TEH

Custom Code

Extended Part Number

YYWW xx@Country of Origin

Part number, package code, environmental code eXXXXX = Part number AAA = Package codee = Environmental code (+ = RoHS 0/6, no code = RoHS 5/6, 1 = RoHS 6/6, 2 = Green)

Country of origin(contained in the mold ID ormarked as the last line onthe package)

Pin 1 location

Marvell Logo

Lot Number88XXXXX-AAAe

Date code, custom code, assembly plant codeYYWW = Date code (YY = year, WW = Work Week)xx = Custom code or die revision@ = Assembly plant code

88SE9445 R3.3 Four-Lane PCI-Express 2.0 to Four-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet

THIS PAGE LEFT INTENTIONALLY BLANK

iv


Change History

v


CHANGE HISTORY

The following table identifies the document change history for Rev. E.

Document Changes *

Location Type Description Date

Page -iii Update Corrected the ordering description for Ordering Part Numbers:

from

481-Ball HSBGA 19 × 19 mm


to

481-Ball TFBGA 19 × 19 mm


May 9, 2014

Page 1-1 Update Updated the description for chapter 1, Overview:

from

The 88SE9445 is a four-port, 6.0 Gbps SAS/SATA controller that provides a one- or four-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack.

to

The 88SE9445 is a four-port, 6.0 Gbps SAS/SATA controller that provides a one-, two-, or four-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack.

December 8, 2014

Page 2-2 Update Updated the description for section 2.1, General. December 5, 2014

Page 3-5 Update Updated Table 3-1, Signal Type Definitions. December 8, 2014

Page 3-8 Update Updated the description for PIN_TEST[9:8] in Table 3-2, General Purpose I/O Signals:

from

PIN_TEST[9:8]–PCIe maximum lane width

0h: x81h: x12h: x43h: x8

to


0h: x8

Note: Always use 0h.

January 14, 2015

Page 4-3

Page 4-4

Page 4-5

Page 4-6

Update Updated the following schematics for section 4.1, 88SE9445 Board Schematics:

• Figure 4-1, 88SE9445 Example Board Schematic (1 of 4)• Figure 4-2, 88SE9445 Example Board Schematic (2 of 4)• Figure 4-3, 88SE9445 Example Board Schematic (3 of 4)• Figure 4-4, 88SE9445 Example Board Schematic (4 of 4)

June 27, 2014

88SE9445 R3.3 Four-Lane PCI-Express 2.0 to Four-Port SAS/SATA 6 Gbps RAID I/O Controller

vi


Page 5-4 Parameter Updated Table 5-3, DC Electrical Characteristics:

• Updated Analog Power for PCIe PHY 1.8V.• Updated Analog Power for SAS/SATA PHY 2.5V, Chip PLL.• Updated Digital Core Power.• Updated Digital I/O Power.• Corrected the Maximum value of Input Low Voltage of Digital I/O from

0.8 to 0.3 × VDDOx.• Corrected the Minimum value of Input High Voltage of Digital I/O from

2.0 to 0.7 × VDDOx.• Corrected the Maximum value of Input High Voltage of Digital I/O

from 3.6 to VDDOx + 0.4.• Corrected the Typical value of Output High Voltage of Digital I/O from

VDDO1/VDDO2 to VDDOx.

December 18, 2014

Page 5-5 Update Updated the description for section 5.4, Thermal Data:

from

Table 5-5 shows the values for the package thermal parameters for the 484-pin TFBGA mounted on a 4-layer PCB.

to

Table 5-5 shows the values for the package thermal parameters for the 481-ball TFBGA mounted on a 4-layer PCB.

December 4, 2014

* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.

Document Changes * (continued)

Location Type Description Date

Contents

vii


CONTENTS

1 OVERVIEW ........................................................................................................................................................ 1-1

2 FEATURES ........................................................................................................................................................ 2-1

2.1 GENERAL .................................................................................................................................................. 2-2

2.2 PCIE ......................................................................................................................................................... 2-3

2.3 SAS (DIRECT ATTACH OR EXPANDER) ....................................................................................................... 2-4

2.4 SATA (DIRECT ATTACH) ............................................................................................................................ 2-5

2.5 XOR ENGINE ............................................................................................................................................ 2-6

2.6 PERIPHERALS ............................................................................................................................................ 2-7

3 PACKAGE ......................................................................................................................................................... 3-1

3.1 BALL DIAGRAM .......................................................................................................................................... 3-2

3.2 MECHANICAL DIMENSIONS ......................................................................................................................... 3-3

3.3 SIGNAL DESCRIPTIONS ............................................................................................................................... 3-53.3.1 Signal Definitions ...................................................................................................................... 3-53.3.2 Signal Descriptions ................................................................................................................... 3-6

4 LAYOUT GUIDELINES ...................................................................................................................................... 4-1

4.1 88SE9445 BOARD SCHEMATICS ................................................................................................................ 4-2

4.2 LAYER STACK-UP ...................................................................................................................................... 4-74.2.1 Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes ................... 4-74.2.2 Layer 2–Solid Ground Plane ..................................................................................................... 4-74.2.3 Layer 3–Power Plane and Low Speed Signals ......................................................................... 4-74.2.4 Layer 4–Power Plane ................................................................................................................ 4-74.2.5 Layer 5–Solid Ground Plane ..................................................................................................... 4-74.2.6 Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes .................... 4-8

4.3 POWER SUPPLY ........................................................................................................................................ 4-94.3.1 VDD Power (1.0V) ..................................................................................................................... 4-94.3.2 PCIe Analog Power Supply (1.8V) ............................................................................................ 4-94.3.3 SAS/SATA Analog Power Supply (2.5V) .................................................................................. 4-94.3.4 General I/O Power (3.3V) .......................................................................................................... 4-94.3.5 Bias Current Resistor (RSET) ................................................................................................. 4-10

4.4 PCB TRACE ROUTING ............................................................................................................................. 4-11

4.5 RECOMMENDED LAYOUT .......................................................................................................................... 4-12

5 ELECTRICAL SPECIFICATIONS ...................................................................................................................... 5-1

5.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 5-2

5.2 RECOMMENDED OPERATING CONDITIONS ................................................................................................... 5-3

5.3 DC ELECTRICAL CHARACTERISTICS ........................................................................................................... 5-4

5.4 THERMAL DATA ......................................................................................................................................... 5-5

5.5 AC TIMING ................................................................................................................................................ 5-65.5.1 SATA ......................................................................................................................................... 5-65.5.2 PCIe .......................................................................................................................................... 5-65.5.3 Parallel Flash and NVSRAM ..................................................................................................... 5-6



viii


Part 1: Chip OverviewOverview

1-1


1 OVERVIEW

The 88SE9445 is a four-port, 6.0 Gbps SAS/SATA controller that provides a one-, two-, or four-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack.

The 88SE9445 controller brings a high-performance, low-cost 6.0 Gbps per port combined SAS and SATA solution to HBA, workstation, and server designs utilizing a one- or four-lane PCIe 2.0 interface. The 88SE9445 integrates four high-performance SAS/SATA PHYs and a self-configuring four-lane PCIe core. Each of the four PHYs is capable of 1.5 Gbps, 3.0 Gbps, and 6.0 Gbps SAS and SATA link rates. The 88SE9445 supports ANSI Serial Attached SCSI - 2.0 (SAS-2.0). The controller also supports the SATA protocol defined in the Serial ATA, Revision 3.0 Specification.

Figure 1-1 shows the system block diagram.

Figure 1-1 88SE9445 (4-port SAS/SATA) Block

AH

B B

us

MXI Bus

XOR x2

PCI-Express

x4

FLASHNVSRAM

PBSRAM

SAS / SATA

x4

Config, Interrupts , and Timers

GPPs, UART, andTWSI

Comm



1-2


Part 1: Chip OverviewFeatures

2-1


2 FEATURES

The chapter contains the following sections:

General

PCIe

SAS (Direct Attach or Expander)

SATA (Direct Attach)

XOR Engine

Peripherals


2-2 General


2.1 General

Four SAS/SATA ports.

Choice of x1, x2, or x4 lane PCIe 2.0 host interface.

Supports three Serial Device Bus (I2C) controllers for communicating with hardware monitoring ICs.

Supports two industry standard 57600 UARTs.

Supports two SFF-8485 compliant SGPIO ports.

Supports autodetection of SAS or native SATA device.

Up to 2048 concurrent I/O operations.

Up to 64 concurrent SATA Devices.

No hardware limit on the number of SAS devices supported.

55 nm CMOS process, 1.0V digital core, 2.5V analog power supply, and 3.3V I/O supply.

Estimated power (4-port):

Minimum = 3.0W

Typical = 3.93W

Maximum = 5.7W

Up to 34 LED/GPIO ports.

Supports hardware RAID 5 and RAID 6 acceleration.

Supports Data Path Parity Protection (DPP).


PCIe 2-3


2.2 PCIe

Supports x1, x2, or x4 lane PCIe 2.0 Interface (5.0 Gbps).

Supports four fully independent PCIe functions.

Supports independent interrupt mechanisms for each PCIe function.

Supports Message Signal Interrupts (MSI).

All registers memory mapped.

Supports PCIe Power Management: D0, D1, D3COLD, D3HOT.


2-4 SAS (Direct Attach or Expander)


2.3 SAS (Direct Attach or Expander)

Serial Attached SCSI (SAS-2.0) compliant.

Supports 6 Gbps, 3 Gbps, and 1.5 Gbps devices.

Supports SAS Multiplexing. Up to 8 logical ports when multiplexing is enabled on all PHYs.

Supports SSC, with independent control for each PHY using SSC_EN (R060h [17]).

Supports wide SAS ports. Up to four wide when multiplexing is disabled, and up to eight wide when multiplexing is enabled.

Supports Serial SCSI Protocol (SSP), initiator and target mode.

Supports SAS Management Protocol (SMP), initiator mode.

Supports Serial ATA Tunneling Protocol (STP), initiator mode.

Non-zero offset and non-sequential data delivery.

ATA and ATAPI commands.

Native Command Queuing (NCQ).

Supports T10 Protection Information Model. DIF fields can be inserted, checked, replaced, and/or removed.

Supports Transport Layer Retries.

Supports hardware assisted Scatter-Gather.


SATA (Direct Attach) 2-5


2.4 SATA (Direct Attach)

Serial ATA Revision 3.0 (6 Gbps) compliant, with speed negotiation to 3.0 Gbps and 1.5 Gbps.

Supports programmable SATA signaling levels, including Gen1x, Gen2i, and Gen2x.

Supports ATA and ATAPI commands.

Supports Native Command Queuing (NCQ).

Non-zero offset and non-sequential data delivery.

32 outstanding commands per device.

Supports Port Multiplier.

FIS based Switching on NCQ and legacy commands.

Supports Host mode and Device mode of operation.

Supports hardware assisted Scatter-Gather.


2-6 XOR Engine


2.5 XOR Engine

Supports Advanced RAID features including:

Dual XOR RAID 6.

P + Q + Copy, or Q + Q + Q RAID 6.

Memory Block Fill.

Zero Result Check.

Generates up to 3 checksums concurrently, including any combination of P and Q.

Independent GF Multiply coefficient for each of 3 concurrent Q checksum calculations.

Supports rebuilding three failed drives simultaneously with a single read of remaining good drives.

Supports chained XOR Descriptor Tables, with up to 32 operations in each table.

Supports Scatter-Gather transfers using a common PRD format.

Supports CRC32 checksum generation and checking.


Peripherals 2-7


2.6 Peripherals

Supports up to 4 MB of external NVSRAM memory (x8/x16).

Supports up to 4 MB of external PBSRAM memory (x32).

Supports up to 8 MB of external Parallel Flash memory (x8/x16).

Supports up to 16 MB of external SPI Flash memory.



2-8 Peripherals


Part 1: Chip OverviewPackage

3-1


3 PACKAGE

This chapter contains the following sections:

Ball Diagram

Mechanical Dimensions

Signal Descriptions


3-2 Ball Diagram


3.1 Ball Diagram

The 481-pin TFBGA ball diagram is illustrated in Figure 3-1.

Figure 3-1 Ball Diagram

VSS

VSS

PRXP

[0]

VSS

PRXP[1

]

VSS

PRXP

[2]

VSS

PRXP

[3]

VSS

REFC

LKP

VSS

NC

VSS

NC

VSS

NC

VSS

NC

VSS

PIN

_F_

WE_NP

IN_P

_

DATA

[20]V

SS

PIN

_TEST

[13]V

SS

PRXN[0

]

VSS

PRXN[1

]

VSS

PRXN[2

]

VSS

PRXN[3

]

VSS

REFC

LKN

VSSN

CVSS

NC

VSS

NC

VSS

NC

VSS

PIN

_F_

BYTE

_NPIN

_P_

DATA

[19]

PIN

_P_

DATA

[26]

PIN

_TEST

[10]

PIN

_TEST

[15]V

SS

PTX

P[0

]

VSS

PTX

P[1

]

VSS

PTX

P[2

]

VSS

PTX

P[3

]

VSS

NC

VSS

NC

VSS

NC

VSS

NC

VSS

PIN

_N_

CE_NP

IN_F

_

RESET

_NPIN

_P_

DATA

[25]

PIN

_P_

DATA

[29]

PIN

_TEST

[8]

PIN

_TEST

[14]V

SS

PTX

N[0

]

VSS

PTX

N[1

]

VSS

PTX

N[2

]

VSS

PTX

N[3

]

VSS

NC

VSS

NC

VSS

NC

VSS

NC

VSS

PIN

_N_

WE_NP

IN_F

_

READY

PIN

_P_

DATA

[24]P

IN_P

_

DATA

[30]

PIN

_TEST

[9]

PIN_T

EST

[11]

PIN

_TEST

[12]VS

SVSS

VSS

VSS

VSS

PTP

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

PIN

_F_C

E

_NPIN

_P

_DATA

[18]P

IN_P

_

DATA

[27]P

IN_P

_

DATA

[31]

PIN

_TEST

[4]

PIN

_TEST

[7]

PIN

_TEST

[6]V

SS

VSS

AVDD25

_

1VSS

AVDD[8

]-1

AVDD[8

]-1

AVDD[8

]-1

VSS

PIN

_ISET

AVDD[8

]-2

AVDD[8

]-2

AVD

D[8

]-2

VSS

AVDD25

_0

VSS

VDD

O2

PIN

_F_O

E_

NPIN

_P_

DATA

[34]P

IN_P

_

DATA

[17]

PIN

_P_

ADDR

[3]

PIN

_TEST

[1]

PIN

_TEST

[3]

PIN

_TEST

[5]

VSS

PIN

_N_O

E_

NPIN

_P_

DATA

[16]P

IN_P

_

DATA

[21]

PIN

_P_

ADDR

[2]

PIN

_FLT

[8]

PIN_T

EST

[0]

PIN

_TEST

[2]

VDDO1

VDD

VDD

AVDD[8

]-1

AVD

D[8

]-1

AVD

D[8

]-1

AVDD[8

]-1

AVD

D[8

]-2

AVD

D[8

]-2

AVD

D[8

]-2

AVDD[8

]-2

VDD

VDD

VDD

VDDO2

PIN

_P_

DATA

[22]P

IN_P

_

DATA

[23]

PIN

_P_

ADDR

[1]

PIN

_FLT

[5]

PIN

_FLT

[6]

PIN

_FLT

[7]

VDDO1

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDDO2

PIN

_P_

DATA

[28]P

IN_P

_

DATA

[35]

PIN

_P_

ADDR

[19]

PIN

_FLT

[2]

PIN

_FLT

[3]

PIN

_FLT

[4]

VDDO1

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDDO2

PIN

_P_

ADDR

[5]P

IN_P

_

ADDR

[0]

PIN

_P_

ADDR

[18]

PIN

_FLT

[0]

PIN

_FLT

[1]

PIN

_ACT

[8]

VDDO1

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDDO2

PIN

_P_

ADDR

[4]

PIN

_P_

ADDR

[11]P

IN_P

_

ADDR

[10]

PIN

_ACT

[6]

PIN

_ACT

[7]

PIN

_ACT

[3]V

DDO1

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDDO2

PIN

_P_

ADDR

[17]

PIN

_P_

ADDR

[13]P

IN_P

_

ADDR

[12]

PIN

_ACT

[5]

PIN

_ACT

[4]

PIN

_ACT

[0]

VDDO1

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDDO2

PIN

_P_

ADDR

[14]P

IN_P

_

ADDR

[16]

PIN

_P_

ADDR

[15]

PIN

_ACT

[2]

PIN_A

CT

[1]

PIN

_SCL

[0]

VDDO1

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDDO2

PIN

_P_

DATA

[1]P

IN_P

_

DATA

[0]

PIN

_P_

DATA

[32]

PIN

_SCL

[2]

PIN

_SCL

[1]

PIN

_SDA

[0]

VDDO1

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDDO2

PIN

_P_

DATA

[5]

PIN

_P_

DATA

[6]P

IN_P

_

DATA

[2]

PIN

_SDA

[2]

PIN

_SDA

[1]

PIN

_UAO

[0]

VDDO1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDO2

PIN

_P_

DATA

[10]PIN

_P_

DATA

[12]

PIN

_P_

DATA

[3]

PIN

_UAI

[1]

PIN_U

AI

[0]

PIN

_SPI_

DOV

AA_

ANA

VDDO2

PIN

_P_

DATA

[14]

PIN

_P_

DATA

[11]P

IN_P

_

DATA

[4]

PIN

_UAO[1

]

PIN

_SPI_

DI

PIN

_RESET

_NVSS

VSS

VSS

VSS

VAA[4

-7]

VAA[4

-7]

VAA[4

-7]

VAA[4

-7]

VAA[4

-7]

VAA[0

-3]

VAA[0

-3]

VAA[0

-3]

VAA[0

-3]

VAA[0

-3]

VSS

VSS

VSS

PIN

_P_

GW

_NPIN

_P_

DATA

[13]P

IN_P

_

DATA

[7]

PIN

_SPI_

CS_N

PIN

_CNFG

[1]

ISET

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

PIN

_P_W

E

_N[1

]PIN

_P_

DATA

[15]P

IN_P

_

DATA

[8]

PIN

_SPI_

CLK

PIN

_CNFG

[0]V

SS

NC

VSS

NC

VSS

NCV

SS

NC

VSS

PIN

_RXN

[3]V

SS

PIN

_RXN

[2]V

SS

PIN

_RXN

[1]V

SS

PIN

_RXN[0

]

VSS

PIN

_P_W

E_N

[2]

PIN

_P_

WE_N

[0]

PIN

_P_

DATA

[33]P

IN_P

_

DATA

[9]

PIN

_M_

DATA

PIN

_PRE

SET_N

VSS

NCV

SS

NC

VSS

NC

VSS

NCV

SS

PIN

_RXP

[3]

VSS

PIN_R

XP

[2]V

SS

PIN

_RXP

[1]V

SS

PIN

_RXP

[0]V

SS

PIN

_P_

CS1_

NPIN

_P_

WE_N

[3]

PIN

_P_

ADV_NP

IN_P

_

ADDR

[9]

PIN

_M_

CLK

PIN

_REF

CLKN

CVSS

NC

VSS

NCV

SS

NC

VSS

PIN

_TXN

[3]

VSS

PIN

_TXN

[2]V

SS

PIN

_TXN

[1]

VSS

PIN

_TXN

[0]

VSSP

IN_P

_

ADDR

[20]P

IN_P

_

ADDR

[6]

PIN

_P

_OUT_

CLKP

IN_P

_

ADSC_

NPIN

_P_

ADDR

[8]

VSS

PIN

_

TPNC

VSS

NC

VSS

NCV

SS

NC

VSS

PIN

_TXP

[3]V

SS

PIN

_TXP

[2]V

SS

PIN

_TXP

[1]V

SS

PIN

_TXP

[0]V

SS

PIN

_P_

ADDR

[21]

PIN

_P_

ADDR

[7]P

IN_P

_

OE_NP

IN_P

_

BW

_NVSS


Mechanical Dimensions 3-3


3.2 Mechanical Dimensions

The package mechanical drawing is shown in Figure 3-2 and the mechanical dimensions are shown in Figure 3-2.

Figure 3-2 Package Mechanical Drawing (BMJ)


3-4 Mechanical Dimensions


Figure 3-3 Package Mechanical Dimensions (BMJ)


Signal Descriptions 3-5


3.3 Signal Descriptions

This section includes information on signal definitions and descriptions:

Signal Definitions

Signal Descriptions

3.3.1 Signal Definitions

Signal type definitions are shown in Table 3-1.

Table 3-1 Signal Type Definitions

Signal Type Definition

I/O Input and output

I Input only

O Output only

OC Open Collector

OD Open-Drain pad

Ground Ground

Power Power

NC No Connect*

* Pin is floating and is not connected internally to any active circuitry nor has any electrical continuity to any other pin

DNC Do Not Connect†

† Device pin to which there may or may not be an internal connection, but to which no external connections are allowed.

N/A Not Applicable


3-6 Signal Descriptions


3.3.2 Signal Descriptions

This section outlines the 88SE9445 signal descriptions. Signals ending with the letter “N” are active-low signals.

Table 3-2 General Purpose I/O Signals

Signal NameSignal Number

Type Description

PIN_ACT[8]

PIN_ACT[7]

PIN_ACT[6]

PIN_ACT[5]

PIN_ACT[4]

PIN_ACT[3]

PIN_ACT[2]

PIN_ACT[1]

PIN_ACT[0]

L21

M22

M23

N23

N22

M21

P23

P22

N21

I/O, OC Activity LED.

Active low.

PIN_ACT is active when SAS/SATA PHY is transmitting or receiving.

These pins can be used as GPIO.

PIN_ACT[3:0]–SAS/SATA PHY[3:0] activity.

PIN_ACT[7:4]—Not used.

PIN_ACT[8]–Global Activity. Enabled when any SAS/SATA PHY is active.




PIN_FLT[8]

PIN_FLT[7]

PIN_FLT[6]

PIN_FLT[5]

PIN_FLT[4]

PIN_FLT[3]

PIN_FLT[2]

PIN_FLT[1]

PIN_FLT[0]

H23

J21

J22

J23

K21

K22

K23

L22

L23

I/O, OC Fault LED.

Active low signals.

PIN_FLT is active when PHY is not ready or when PHY is ready and there is any PHY related error or connection error.

These pins can be used as GPIO, SGPIO, I2C, or FLT_LED. See GPIO_FLT_CFG (R10080h [7:0]) and I2C_SGPIO_FLT_PAD_SEL (R10104h [9:8]).

Pins used as Fault LED:

• PIN_FLT[8]: Global Fault indication. The indicator is on when any SAS/SATA_PHY has a fault.

• PIN_FLT[7:0] corresponds to SAS/SATA_PHY7 through PHY0.

Note: When PHY is not ready, PIN_FLT[7:0] is always on. After the PHY is ready, a fault occurs.

Pins used as SGPIO:

• PIN_FLT[8]: Same as FLT mode.• PIN_FLT[7:4]: SGPIO1 SCLK, SLOAD, SDOUT,

SDIN• PIN_FLT[3:0]: SGPIO0

SCLK,SLOAD,SDOUT,SDIN

Used as I2C:

• PIN_FLT[8]: Same as FLT Mode• PIN_FLT[7:6]: I2C2 CLK, DATA• PIN_FLT[5:4]: Not used• PIN_FLT[3:2]: I2C1 CLK, DATA• PIN_FLT[1:0]: Not used

Table 3-2 General Purpose I/O Signals (continued)


Type Description




PIN_TEST[15]

PIN_TEST[14]

PIN_TEST[13]

PIN_TEST[12]

PIN_TEST[11]

PIN_TEST[10]

PIN_TEST[9]

PIN_TEST[8]

PIN_TEST[7]

PIN_TEST[6]

PIN_TEST[5]

PIN_TEST[4]

PIN_TEST[3]

PIN_TEST[2]

PIN_TEST[1]

PIN_TEST[0]

C22

D22

B23

E21

E22

C23

E23

D23

F22

F21

G21

F23

G22

H21

G23

H22

I/O Configuration and test pins.

These pins can be used as GPIO.

PIN_TEST[15]-PCIe power-up disable

0h: Enable PCIe after power-up1h: Disable PCIe after power-up

Not applicable to this chip. This signal needs pull-down.

PIN_TEST[14:13]–Chip reference clock selection

0h: 20 MHz1h: 50 MHz2h: 100 MHz3h: 75 MHz

PIN_TEST[12:11]–Reserved

PIN_TEST[10]–PCIe ROM location

0h: Parallel Flash1h: Serial Flash


0h: x8

Always use 0h.PIN_TEST[7:6]–Reserved

PIN_TEST[5]—PCIe configuration access enable.

0h: PCIe responds to configuration access.

1h: PCIe returns a retry configuration access.

Not applicable to this chip. This signal needs pull-down.

PIN_TEST[4]–Parallel Flash x8/x16

0h: Byte mode1h: Word mode

PIN_TEST[3:2]–Reserved

PIN_TEST[1]–UART baudrate

0h: 576001h: Reserved

PIN_TEST[0]–UART mode

0h: Reserved1h: Terminal mode

Table 3-3 Clock and Reset Signals


Type Description

PIN_REFCLK AB22 I Reference clock input.

2.5V, ± 350 ppm.

PIN_RESET_N V21 I Power-on reset.

Table 3-2 General Purpose I/O Signals (continued)


Type Description




.

PIN_PRESET_N AA22 I PCIe Reset

PIN_TP AC22 O SAS/SATA analog test port.

Table 3-4 I2C Signals


Type Description

PIN_SCL[2]

PIN_SCL[1]

PIN_SCL[0]

R23

R22

P21

I/O, OC I2C clock.

PIN_SDA[2]

PIN_SDA[1]

PIN_SDA[0]

T23

T22

R21

I/O, OC I2C data.

Table 3-5 UART Signals


Type Description

PIN_UAI[1]

PIN_UAI[0]

U23

U22

I UART input.

PIN_UAO[1]

PIN_UAO[0]

V23

T21

O UART output.

Table 3-6 Parallel Flash Signals


Type Description

PIN_F_BYTE_N B3 O Parallel flash Byte mode.

PIN_F_CE_N E4 O Parallel flash chip select.

PIN_F_OE_N F4 O Parallel flash output enable.

PIN_F_READY D3 I Parallel flash ready signal.

Requires external pull-up resistor.

PIN_F_RESET_N C3 O Parallel flash reset.

PIN_F_WE_N A3 O Parallel flash write enable.

Table 3-3 Clock and Reset Signals (continued)


Type Description




PIN_P_ADDR[21]

PIN_P_ADDR[20]

PIN_P_ADDR[19]

PIN_P_ADDR[18]

PIN_P_ADDR[17]

PIN_P_ADDR[16]

PIN_P_ADDR[15]

PIN_P_ADDR[14]

PIN_P_ADDR[13]

PIN_P_ADDR[12]

PIN_P_ADDR[11]

PIN_P_ADDR[10]

PIN_P_ADDR[9]

PIN_P_ADDR[8]

PIN_P_ADDR[7]

PIN_P_ADDR[6]

PIN_P_ADDR[5]

PIN_P_ADDR[4]

PIN_P_ADDR[3]

PIN_P_ADDR[2]

PIN_P_ADDR[1]]

PIN_P_ADDR[0]

AC5

AB5

J1

K1

M3

N2

N1

N3

M2

M1

L2

L1

AA1

AB1

AC4

AB4

K3

L3

F1

G1

H1

K2

O Shared address bus for parallel flash, NVSRAM and PBSRAM.

For Parallel Flash, signals are word addresses.

For NVSRAM, signals are WORD addresses.

For PBSRAM, signals are Dword addresses.

Table 3-6 Parallel Flash Signals (continued)


Type Description




PIN_P_DATA[35]

PIN_P_DATA[34]

PIN_P_DATA[33]

PIN_P_DATA[32]

PIN_P_DATA[31]

PIN_P_DATA[30]

PIN_P_DATA[29]

PIN_P_DATA[28]

PIN_P_DATA[27]

PIN_P_DATA[26]

PIN_P_DATA[25]

PIN_P_DATA[24]

PIN_P_DATA[23]

PIN_P_DATA[22]

PIN_P_DATA[21]

PIN_P_DATA[20]

PIN_P_DATA[19]

PIN_P_DATA[18]

PIN_P_DATA[17]

PIN_P_DATA[16]

PIN_P_DATA[15]

PIN_P_DATA[14]

PIN_P_DATA[13]

PIN_P_DATA[12]

PIN_P_DATA[11]

PIN_P_DATA[10]

PIN_P_DATA[9]

PIN_P_DATA[8]

PIN_P_DATA[7]

PIN_P_DATA[6]

PIN_P_DATA[5]

PIN_P_DATA[4]

PIN_P_DATA[3]

PIN_P_DATA[2]

PIN_P_DATA[1]]

PIN_P_DATA[0]

J2

F3

Y2

P1

E1

D1

C1

J3

E2

B1

C2

D2

H2

H3

G2

A2

B2

E3

F2

G3

W2

U3

V2

T2

U2

T3

Y1

W1

V1

R2

R3

U1

T1

R1

P3

P2

I/O Shared Data Bus for Parallel Flash/NVSRAM/PBSRAM.

For Parallel Flash, DATA[15:0] are used.

In Byte mode, DATA[15] is address bit 0. DATA[7:0] are data.

In Word mode, DATA[15:0] are data.

For NVSRAM, DATA[15:0] are used.

For PBSRAM, DATA[35:0] are used.

DATA[35] is parity for Byte 3.




Table 3-6 Parallel Flash Signals (continued)


Type Description




Table 3-7 NVSRAM Signals


Type Description

PIN_N_CE_N C4 O nvSRAM chip select.

PIN_N_OE_N G4 O nvSRAM output enable.

PIN_N_WE_N D4 O nvSRAM write enable.

Table 3-8 PBSRAM Signals


Type Description

PIN_P_ADSC_N AB2 O PBSRAM ASDC mode.

PIN_P_ADV_N AA2 O PBSRAM address advance.

PIN_P_BW_N AC2 O PBSRAM BW.

PIN_P_CS1_N AA4 O PBSRAM chip select.

PIN_P_GW_N V3 O PBSRAM global write enable.

PIN_P_OE_N AC3 O PBSRAM output enable.

PIN_P_OUT_CLK AB3 O PBSRAM clock.

PIN_P_WE_N[3]

PIN_P_WE_N[2]

PIN_P_WE_N[1]

PIN_P_WE_N[0]

AA3

Y4

W3

Y3

O PBSRAM write enable.

Table 3-9 System Interface Signals


Type Description

PIN_CNFG[1]

PIN_CNFG[0]

W22

Y22

I Configuration.

00: Normal Functional mode.Others:Test Mode.

REFCLKP A13 I PCIe reference clock input.

100MHz ± 300ppm.No internal clock termination.

REFCLKN B13 I PCIe reference clock input.

100MHz ± 300ppm.No internal clock termination.




Table 3-10 SPI Interface Signals


Type Description

PIN_SPI_DI V22 I SPI data input.

PIN_SPI_CLK Y23 O SPI clock.

PIN_SPI_CS_N W23 O SPI chip select.

PIN_SPI_DO U21 O SPI data output.

Table 3-11 PCIe Interface Signals


Type Description

ISET W21 I/O Reference Current for PCI-Express PHY.

This pin must be connected to an external 6.04 kΩ, 1% resistor to ground.

PIN_ISET F12 I Chip reference resistor 5 kΩ.

PTP E15 O Analog test port for PCIe.

PIN_M_CLK AB23 I PCIe debugging MDIO interface, clock.

PIN_M_DATA AA23 I/O PCIe debugging MDIO interface, data.

Table 3-12 SAS/SATA Transmitter and Receiver Interface Signals


Type Description

PIN_RXP[3]

PIN_RXP[2]

PIN_RXP[1]

PIN_RXP[0]

AA12

AA10

AA8

AA6

I PIN_RXP[3:0]–SAS/SATA PHY 3–0 Receiver Differential Signal.

PIN_RXN[3]

PIN_RXN[2]

PIN_RXN[1]

PIN_RXN[0]

Y12

Y10

Y8

Y6

I PIN_RXN[3:0]–SAS/SATA PHY 3–0 Receiver Differential Signals.




PIN_TXP[3]

PIN_TXP[2]

PIN_TXP[1]

PIN_TXP[0]

AC13

AC11

AC9

AC7

O PIN_TXP[3:0]–SAS/SATA PHY 3–0 Transmitter Differential Signals.

PIN_TXN[7]

PIN_TXN[6]

PIN_TXN[5]

PIN_TXN[4]

PIN_TXN[3]

PIN_TXN[2]

PIN_TXN[1]

PIN_TXN[0]

–

–

–

–

AB13

AB11

AB9

AB7

O PIN_TXN[3:0]–SAS/SATA PHY 3–0 Transmitter Differential Signals.

Table 3-13 PCIe Transmitter and Receiver Interface Signals


Type Description

PRXP[3]

PRXP[2]

PRXP[1]

PRXP[0]

A15

A17

A19

A21

I PRXP[3:0]–PCI-Express Lane 3–0 Receiver Differential Signal (PCI-Express RX +/-).

PRXN[3]

PRXN[2]

PRXN[1]

PRXN[0]

B15

B17

B19

B21

I PRXN[3:0]–PCI-Express Lane 3–0 Receiver Differential Signals (PCI-Express RX +/-).

PTXP[3]

PTXP[2]

PTXP[1]

PTXP[0]

C14

C16

C18

C20

O PTXP[3:0]–PCI-Express Lane 3–0 Transmitter Differential Signals (PCI-Express TX -/+).

PTXN[3]

PTXN[2]

PTXN[1]

PTXN[0]

D14

D16

D18

D20

O PTXN[3:0]–PCI-Express Lane 3–0 Transmitter Differential Signals (PCI-Express TX -/+).

Table 3-12 SAS/SATA Transmitter and Receiver Interface Signals (continued)


Type Description




Table 3-14 Power Interface Signals


Type Description

AVDD25_0 F7 Power, I I/O Pad Power 2.5V.

AVDD25_1 F18 Power, I I/O Pad Power 2.5V.

AVDD[8]-1 F14, F15, F16. H13, H14, H15, H16

Power, I 1.8V analog power for PCI-Express PHY.

AVDD[8] is for PLL and the current source.

AVDD[8]-2 F9, F10, F11, H9, H10, H11, H12

Power, I 1.8V analog power for PCI-Express PHY.

AVDD[8] is for PLL and the current source.

VAA[0-3] V7, V8, V9, V10, V11

Power, I 2.5V analog power for SAS/SATA PHY.

VAA[4-7] V12, V13, V14, V15, V16

Power, I 2.5V analog power for SAS/SATA PHY.

VAA_ANA U20 Power, I 2.5V analog power for PLL.

VDD H6, H7, H8, H17, H18, J6, J18, K6, K18, L6, L18, M6, M18, N6, N18, P6, P18, R6, R18, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18

Power, I 1.0V digital core power.

VDDO1 H20, J20, K20, L20, M20, N20, P20, R20, T20

Power, I Digital Power.

3.3V I/O Power to supply digital and I/Os.

VDDO2 F5, H4, J4, K4, L4, M4, N4, P4, R4, T4, U4




VSS A1, A4, A6, A8, A10, A12, A14, A16, A18, A20, A22, A23, B4, B6, B8, B10, B12, B14, B16, B18, B20, B22, C5, C7, C9, C11, C13, C15, C17, C19, C21, D5, D7, D9, D11, D13, D15, D17, D19, D21, E5–E14, E16–E20, F6, F8, F13, F17, F19, F20, G20, J7–J17, K7–K17, L7–L17, M7– M17, N7–N17, P7–P17, R7–R17, V4–V6, V17– V20, W4–W20, Y5, Y7, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21,

Ground Ground.

Table 3-14 Power Interface Signals (continued)


Type Description




VSS AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AC1, AC6, AC8, AC10, AC12, AC14, AC16, AC18, AC20, AC23

Ground Ground.

Table 3-15 No Connect Signals


Type Description

NC – A5, A7, A9, A11, B5, B7, B9, B11, C6, C8, C10, C12, D6, D8, D10, D12, Y14, Y16, Y18, Y20, AA14, AA16, AA18, AA20, AB15, AB17, AB19, AB21, AC15, AC17, AC19, AC21

N/A No Connect

Table 3-14 Power Interface Signals (continued)


Type Description


88SE9445 R3.3Four-Lane PCI-Express 2.0 to Four-Port SAS/SATA 6 Gbps RAID I/O Controller Preliminary Datasheet



Part 1: Chip OverviewLayout Guidelines

4-1


4 LAYOUT GUIDELINES

This chapter describes the system recommendations from the Marvell Semiconductor design and application engineers who work with the 88SE9445. It is written for those who are designing schematics and printed circuit boards for an 88SE9445-based system. Whenever possible, the PCB designer should try to follow the suggestions provided in this chapter.

The information in this chapter is preliminary. Please consult with Marvell Semiconductor design and application engineers before starting your PCB design.

The chapter contains the following sections:

88SE9445 Board Schematics

Layer Stack-Up

Power Supply

PCB Trace Routing

Recommended Layout

Refer to Chapter 3, Package, for package information.


4-2 88SE9445 Board Schematics


4.1 88SE9445 Board Schematics

This section contains the following example board schematics:

Figure 4-1, 88SE9445 Example Board Schematic (1 of 4)




88SE9445 Board Schematics 4-3



Figure 4-1 88SE9445 Example Board Schematic (1 of 4)

CNFG

[1:0

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TEST

MOD

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01:

10:

11:

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Nor

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PCIE X 4 ONLY

SR

XN

0

ST

XN

1

SR

XN

1

SR

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2

ST

XN

2

SR

XN

3

ST

XN

3

S_

RX

N3

PT

XN

0P

TX

P0

PC

LK

N

PC

LK

P

CN

FG

0

CN

FG

1

ST

XP

0

ST

XN

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XN

3P

TX

P3

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P2

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P1

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P0

S_

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N0

S_

RX

N0

S_

RX

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SR

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S_

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N1

S_

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S_

RX

N2

S_

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SR

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2

S_

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P3

S_

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N3

S_

RX

N3

S_

RX

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3

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N2

SR

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N0

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XP

1S

RX

N1

S_

RX

P3

S_

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N3

S_

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S_

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S_

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N2

S_

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N2

S_

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S_

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S_

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JT

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CK

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JT

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72

2R

_X

R_

CF

G0

_3

10

K_

XR

_C

FG

0_

31

0K

_X

C4

0.0

1U

C4

0.0

1U

C1

18

10

0n

FC

11

81

00

nF

R7

62

2R

R7

62

2R

C1

11

10

0n

FC

11

11

00

nF

C1

40

.01

UC

14

0.0

1U

R3

4.9

9K

R3

4.9

9K

R7

42

2R

R7

42

2R

PEX

CLOCK & RESET

SAS/SATA

04

49

ES

88

A1

U

PEX

CLOCK & RESET

SAS/SATA

04

49

ES

88

A1

U

PIN

_C

NF

G[1

]W

22

PIN

_C

NF

G[0

]Y

22

PIN

_T

PA

C2

2

PIN

_R

XP

[0]

AA

6

PIN

_R

XP

[1]

AA

8

PIN

_T

XN

[2]

AB

11

PIN

_T

XP

[3]

AC

13

PIN

_R

XN

[0]

Y6

PIN

_R

XN

[1]

Y8

PIN

_T

XP

[2]

AC

11

PIN

_T

XN

[3]

AB

13

PIN

_T

XN

[0]

AB

7

PIN

_T

XN

[1]

AB

9

PIN

_R

XP

[2]

AA

10

PIN

_R

XN

[3]

Y1

2

PIN

_T

XP

[0]

AC

7

PIN

_T

XP

[1]

AC

9

PIN

_R

XN

[2]

Y1

0

PIN

_R

XP

[3]

AA

12

PR

XN

[7]

B5

PR

XN

[6]

B7

PR

XP

[7]

A5

PR

XP

[6]

A7

PR

XN

[5]

A9

PR

XN

[4]

D1

2

PR

XN

[3]

B1

5

PR

XP

[2]

A1

7

PR

XP

[1]

A1

9

PR

XP

[0]

A2

1

PR

XP

[5]

B9

PR

XP

[4]

C1

2

PR

XP

[3]

A1

5

PR

XN

[2]

B1

7

PR

XN

[1]

B1

9

PR

XN

[0]

B2

1

PIN

_P

RE

SE

T_

NA

A2

2

PIN

_IS

ET

F1

2

RE

FC

LK

PA

13

RE

FC

LK

NB

13

ISE

TW

21

PT

XN

[7]

D6

PT

XP

[7]

C6

PT

XN

[6]

D8

PT

XP

[6]

C8

PT

XN

[5]

D1

0

PT

XP

[5]

C1

0

PT

XN

[4]

B1

1

PT

XP

[4]

A1

1

PT

XN

[3]

D1

4

PT

XP

[3]

C1

4

PT

XN

[2]

D1

6

PT

XP

[2]

C1

6

PT

XN

[1]

D1

8

PT

XP

[1]

C1

8

PT

XN

[0]

D2

0

PT

XP

[0]

C2

0

PIN

_R

ES

ET

_N

V2

1

PIN

_R

EF

CL

KA

B2

2

PT

PE

15

C38 1000pF_XC38 1000pF_X

C1

60

.01

UC

16

0.0

1U

C3

0.0

1U

C3

0.0

1U

C1

13

10

0n

FC

11

31

00

nF

J1

iPA

SS

_0

.8m

m_

36

CO

NN

-SA

S-3

6p

in-T

S

J1

iPA

SS

_0

.8m

m_

36

CO

NN

-SA

S-3

6p

in-T

S

RX

+0

A2

RX

+1

A5

RX

+2

A1

3

RX

+3

A1

6

RX

-0A

3

RX

-1A

6

RX

-2A

14

RX

-3A

17

TX

+0

B2

TX

+1

B5

TX

+2

B1

3

TX

+3

B1

6

TX

-0B

3

TX

-1B

6

TX

-2B

14

TX

-3B

17

GN

D1

A1

GN

D2

A4

GN

D3

A7

GN

D4

A1

2

GN

D5

A1

5

GN

D6

A1

8

GN

D7

B1

GN

D8

B4

GN

D9

B7

GN

D1

0B

12

PE

G1

P1

PE

G2

P2

MT

H1

S1

MT

H2

S2

MT

H3

S3

MT

H4

S4

MT

H5

S5

MT

H6

S6

SB

0-S

CL

KB

8

SB

1-S

LO

DB

9

SB

2-G

ND

B1

0

SB

3A

9

SB

4_

SD

OA

10

SB

5_

SD

IA

11

SB

6B

11

SB

7A

8

GN

D1

1B

15

GN

D1

2B

18

C9

0.0

1U

C9

0.0

1U

C37 1000pF_XC37 1000pF_X

U1

0

SN

74

LV

C1

G0

8A

ND

U1

0

SN

74

LV

C1

G0

8A

ND

A1

B2

GN

D3

Y4

VC

C5

C1

10

.01

UC

11

0.0

1U

R_

CF

G0

_1

10

K_

XR

_C

FG

0_

11

0K

_X

PEX 4x

P1

GO

LD F

ING

ER

PEX 4x

P1

GO

LD F

ING

ER

+1

2V

cB

1

+1

2V

dB

2

RS

VD

5B

3

SM

CL

KB

5

SM

DA

TB

6

3V

3c

B8

TR

ST

B9

3.3

VA

ux

B1

0

WA

KE

#B

11

RS

VD

3B

12

HS

O_

0+

B1

4

HS

O_

0-

B1

5

PR

SN

T#

2a

B1

7

HS

O_

1+

B1

9

HS

O_

1-

B2

0

HS

O_

2+

B2

3

HS

O_

2-

B2

4

HS

O_

3+

B2

7

HS

O_

3-

B2

8

RS

VD

4B

30

PR

SN

T#

2b

B3

1

PR

SN

T#

1A

1

+1

2V

bA

2+

12

Va

A3

GN

D2

1A

4

TC

KA

5

TD

IA

6

TD

OA

7

TM

SA

8

3V

3a

A9

3V

3b

A1

0

RS

Tn

A1

1

GN

D2

A1

2

RE

FC

LK

+A

13

RE

FC

LK

-A

14

GN

D9

A1

5G

ND

8A

18

RS

VD

2A

19

GN

D7

A2

0G

ND

6A

23

GN

D5

A2

4G

ND

4A

27

GN

D3

A2

8

RS

VD

1A

32

HS

I_0

-A

17

HS

I_1

-A

22

HS

I_2

-A

26

HS

I_3

-A

30

HS

I_0

+A

16

HS

I_1

+A

21

HS

I_2

+A

25

HS

I_3

+A

29

GN

D1

1B

29

GN

D1

2B

26

GN

D1

3B

25

GN

D1

4B

22

GN

D1

5B

21

GN

D1

6B

18

GN

D1

7B

16

GN

D1

8B

13

GN

D1

9B

7

GN

D2

0B

4G

ND

22

A3

1

GN

D1

0B

32

C1

16

10

0n

FC

11

61

00

nF

C1

00

.01

UC

10

0.0

1U

C35 1000pF_XC35 1000pF_X

R_

CF

G1

_2

1K

-5%

R_

CF

G1

_2

1K

-5%

C36 1000pF_XC36 1000pF_X




Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.


PIN_

TEST

[15:

0]Co

nfig

urat

ion

and

Test

pin

s, G

PIO.

PIN_

TEST

[15]

=>

RSVD

PIN_

TEST

[14:

13]

=> C

hip

refe

renc

e cl

ock

sele

ctio

n =>

PIN_

TEST

[12:

11]

=> R

SVD

PIN_

TEST

[10]

=>

PCIE

ROM

Loc

atio

n =>

PIN_

TEST

[9:8

] =>

PCI

E MA

X LA

NE W

idth

=>

PIN_

TEST

[7:5

] =>

RSV

DPI

N_TE

ST[4

] =>

Par

alle

l Fl

ash

x8/x

16 =

>PI

N_TE

ST[3

:2]

=> R

SVD

PIN_

TEST

[1]

=> U

ART

Baud

Rat

e =>

PIN_

TEST

[0]

=> U

ART

Mode

=>

00:

20MH

z, 0

1: 5

0MHz

10:

100M

Hz,

11:

75MH

z

0: P

aral

lel

Flas

h, 1

: Se

rial

Fla

sh00

: x8

, 01

: x1

10:

x4,

11:

x8

0: B

yte

Mode

, 1:

Wor

d Mo

de

0: 5

7600

, 1:

RSV

D0:

RSV

D, 1

: Te

rmin

al M

ode

(DRI

VE F

AULT

LED

)

SPI

FLAS

H, 4

MBit

(ACT

IVIT

Y LE

D)

NVRA

M 32

KBpi

n 2:

NC,

pin

47:

NC

NVRA

M 12

8KB

pin

2: A

16,

pin4

7: A

15

Encryption key

Drive Fault/ Activity LED headers

Top - Activity (Green)

Bottom - Fault (Yellow)

I2C

con

nect

or

UART

Seri

al E

EPRO

M fo

r I2

C

BUZZER

(ACT

IVIT

Y LE

D)

(DRI

VE F

AULT

LED

)

Install R34, 10K and R44, 1K for debug purposes (UART)

Item 25.

LED

SILK

SCRE

EN

U3,U

5,U6

ARE

OPT

IONA

L.

AC

T2

AC

T3

AC

T0

AC

T1

AC

T4

AC

T6

AC

T7

AC

T5

S_

DIN

1S

_D

OU

T1

S_

LO

AD

1S

_C

LK

1F

LT

8

P_

AD

DR

0P

_A

DD

R1

P_

AD

DR

2P

_A

DD

R3

P_

AD

DR

4P

_A

DD

R5

P_

AD

DR

6P

_A

DD

R7

P_

AD

DR

8P

_A

DD

R9

P_

AD

DR

10

P_

AD

DR

11

P_

AD

DR

12

P_

AD

DR

13

P_

AD

DR

14

P_

AD

DR

15

P_

AD

DR

16

P_

DA

TA

0P

_D

AT

A1

P_

DA

TA

2P

_D

AT

A3

P_

DA

TA

4P

_D

AT

A5

P_

DA

TA

6P

_D

AT

A7

TE

ST

[0]

TE

ST

[1]

TE

ST

[2]

TE

ST

[3]_

FL

T2

TE

ST

[4]_

FL

T3

TE

ST

[5]

TE

ST

[6]_

FL

T4

TE

ST

[7]_

FL

T5

TE

ST

[8]

TE

ST

[9]

TE

ST

[10

]T

ES

T[1

1]_

FL

T6

TE

ST

[12

]_F

LT

7T

ES

T[1

3]

TE

ST

[14

]

UA

I_0

N_

WE

_N

N_

CE

_N

N_

OE

_N

TE

ST

[10

]T

ES

T[1

3]

TE

ST

[14

]

M_

DA

TA

N_

WE

_N

P_

AD

DR

13

P_

AD

DR

8P

_A

DD

R9

P_

AD

DR

15

P_

AD

DR

11

N_

CE

_N

P_

DA

TA

6

P_

AD

DR

10

P_

DA

TA

7P

_D

AT

A5

P_

DA

TA

4P

_D

AT

A3

P_

DA

TA

0P

_A

DD

R3

P_

AD

DR

2P

_A

DD

R1

P_

AD

DR

0

P_

AD

DR

16

P_

AD

DR

14

P_

AD

DR

12

P_

AD

DR

7P

_A

DD

R6

P_

AD

DR

5

N_

OE

_N

P_

AD

DR

4

P_

DA

TA

1P

_D

AT

A2

SO

C_

RE

SE

T#

SM

CL

KS

MD

AT

AC

T8

SM

DA

TI2

C_

SD

A

SM

CL

KI2

C_

SC

LU

AO

_1

UA

I_1

SP

I_D

IS

PI_

DO

SP

I_C

LK

SP

I_C

S_

N

AD

M0

_T

X

SP

I_C

S_

N

SP

I_D

O

TE

ST

[2]

AC

T2

AC

T3

AC

T0

AC

T1

TE

ST

[1]_

DT

ES

T[3

]_D

TE

ST

[4]_

D

TE

ST

[0]

TE

ST

[1]

SP

I_C

LK

SP

I_D

I

UA

O_

0

TE

ST

[15

]

UA

I_0

AD

M0

_R

XA

DM

0_

RX

I2C

_S

CL

I2C

_S

DA

S_

DIN

0S

_D

OU

T0

S_

LO

AD

0S

_C

LK

0

M_

CL

K

UA

O_

0

TE

ST

[0]_

DT

ES

T[1

]_D

TE

ST

[4]_

DT

ES

T[3

]_D

TE

ST

[0]

TE

ST

[1]

TE

ST

[4]_

FL

T3

TE

ST

[3]_

FL

T2

AC

T3

AC

T2

AC

T1

AC

T0

AC

T2

_D

AC

T3

_D

AC

T0

_D

AC

T1

_D

TE

ST

[0]_

DT

ES

T[1

]_D

TE

ST

[4]_

DT

ES

T[3

]_D

TE

ST

[0]_

D

AC

T2

_D

AC

T1

_D

AC

T0

_D

AC

T3

_D

3V

33

V3

3V

3

3V

3

3V

33

V3

3V

3

3V

3

3V

3

3V

33

V3

3V

33

V3

3V

3

3V

3

3V

3

3V

3

3V

3

3V

3

3V

33

V3

3V

3

3V

3

3V

3

3V

3

SO

C_

RE

SE

T#

2

S_

DIN

02 S

_L

OA

D0

2S

_D

OU

T0

2

S_

CL

K0

2

I2C

_S

CL

2

I2C

_S

DA

2

R1

91

0R

R1

91

0R

U2

AD

M3

20

2A

RN

U2

AD

M3

20

2A

RN

C1

+1

V+

2

C1

-3

V-

6

C2

+4

C2

-5

3.3

V1

6

GN

D1

5

Tx1

IN1

1

Tx2

IN1

0

Rx1

OU

T1

2

Rx2

OU

T9

Tx1

OU

T1

4

Tx2

OU

T7

Rx1

IN1

3

Rx2

IN8

R1

7

10

K_

X

R1

7

10

K_

X

R3

61

0R

R3

61

0R

R4

01

0R

R4

01

0R

R5

01

K-5

%R

50

1K

-5%

R4

61

00

RR

46

10

0R

JP

2JP

2

12

TP

15

TP

15

1

TP

25

TP

25

1

C4

8

0.1

U

C4

8

0.1

U

TP

45

TP

45

1

R8

10

KR

81

0K

TP

34

TP

34

1

TP

61

TP

61

1

R5

71

0K

R5

71

0K

TP

17

TP

17

1

TP

48

TP

48

1

U1

2

PI7

4F

CT

24

1/S

O

U1

2

PI7

4F

CT

24

1/S

O

OE

A1

DA

02

DA

14

DA

26

DA

38

GND10

VCC20

OE

B1

9

OA

01

8

OA

11

6

OA

21

4

OA

31

2

DB

01

7

DB

11

5

DB

21

3

DB

31

1

OB

03

OB

15

OB

27

OB

39

U4

4M

bS

PI

FL

AS

H -

AT

26

F0

04

SO

IC8

-50

-21

2

U4

4M

bS

PI

FL

AS

H -

AT

26

F0

04

SO

IC8

-50

-21

2CS

1

SO

2

WP

3

SI

5

SC

LK

6

HO

LD

7

VC

C8

Gn

d4

R7

9

10

K_

X

R7

9

10

K_

X

TP

13

TP

13

1

Q1

FD

C6

40

PC

TQ

1F

DC

64

0P

CT

1

2

34

5

6

U5

DN

P_

AT

24

C0

2B

U5

DN

P_

AT

24

C0

2B

A0

1

A1

2

A2

3

GN

D4

SD

A5

SC

L6

WP

7V

CC

8

NVSRAM/FLASH

CONFIG/TEST/RSVD

PBSRAM

SERIAL INTERFACE

LED

U1

B8

8S

E9

44

0

NVSRAM/FLASH

CONFIG/TEST/RSVD

PBSRAM

SERIAL INTERFACE

LED

U1

B

PIN

_U

AO

[0]

T2

1

PIN

_U

AO

[1]

V2

3

PIN

_U

AI[

0]

U2

2

PIN

_U

AI[

1]

U2

3

PIN

_F

LT

[0]

L2

3

PIN

_F

LT

[1]

L2

2

PIN

_F

LT

[2]

K2

3

PIN

_F

LT

[3]

K2

2

PIN

_F

LT

[4]

K2

1

PIN

_F

LT

[5]

J2

3

PIN

_F

LT

[6]

J2

2

PIN

_F

LT

[7]

J2

1

PIN

_F

LT

[8]

H2

3

PIN

_S

PI_

DI

V2

2

PIN

_S

PI_

DO

U2

1

PIN

_S

PI_

CL

KY

23

PIN

_S

PI_

CS

_N

W2

3

PIN

_N

_W

E_

ND

4

PIN

_N

_C

E_

NC

4

PIN

_N

_O

E_

NG

4

PIN

_P

_A

DD

R[0

]K

2

PIN

_P

_A

DD

R[1

]H

1

PIN

_P

_A

DD

R[2

]G

1

PIN

_P

_A

DD

R[3

]F

1

PIN

_P

_A

DD

R[4

]L

3

PIN

_P

_A

DD

R[5

]K

3

PIN

_P

_A

DD

R[6

]A

B4

PIN

_P

_A

DD

R[7

]A

C4

PIN

_P

_A

DD

R[8

]A

B1

PIN

_P

_A

DD

R[9

]A

A1

PIN

_P

_A

DD

R[1

0]

L1

PIN

_P

_A

DD

R[1

1]

L2

PIN

_P

_A

DD

R[1

2]

M1

PIN

_P

_A

DD

R[1

4]

N3

PIN

_P

_A

DD

R[1

3]

M2

PIN

_P

_A

DD

R[1

5]

N1

PIN

_P

_A

DD

R[1

6]

N2

PIN

_P

_A

DD

R[1

7]

M3

PIN

_P

_A

DD

R[1

8]

K1

PIN

_P

_A

DD

R[1

9]

J1

PIN

_P

_A

DD

R[2

0]

AB

5

PIN

_P

_A

DD

R[2

1]

AC

5

PIN

_P

_B

W_

NA

C2

PIN

_P

_O

UT

_C

LK

AB

3

PIN

_P

_O

E_

NA

C3

PIN

_P

_C

S1

_N

AA

4

PIN

_P

_W

E_

N[0

]Y

3

PIN

_P

_W

E_

N[1

]W

3

PIN

_P

_W

E_

N[2

]Y

4

PIN

_P

_W

E_

N[3

]A

A3

PIN

_P

_D

AT

A[0

]P

2

PIN

_P

_D

AT

A[1

]P

3

PIN

_P

_D

AT

A[2

]R

1

PIN

_P

_D

AT

A[3

]T

1

PIN

_P

_D

AT

A[4

]U

1

PIN

_P

_D

AT

A[5

]R

3

PIN

_P

_D

AT

A[6

]R

2

PIN

_P

_D

AT

A[7

]V

1

PIN

_P

_D

AT

A[8

]W

1

PIN

_P

_D

AT

A[9

]Y

1

PIN

_P

_D

AT

A[1

0]

T3

PIN

_P

_D

AT

A[1

1]

U2

PIN

_P

_D

AT

A[1

2]

T2

PIN

_P

_D

AT

A[1

3]

V2

PIN

_P

_D

AT

A[1

4]

U3

PIN

_P

_D

AT

A[1

5]

W2

PIN

_P

_D

AT

A[1

6]

G3

PIN

_P

_D

AT

A[1

7]

F2

PIN

_P

_D

AT

A[1

8]

E3

PIN

_P

_D

AT

A[1

9]

B2

PIN

_P

_D

AT

A[2

0]

A2

PIN

_P

_D

AT

A[2

1]

G2

PIN

_P

_D

AT

A[2

2]

H3

PIN

_P

_D

AT

A[2

3]

H2

PIN

_P

_D

AT

A[2

4]

D2

PIN

_P

_D

AT

A[2

5]

C2

PIN

_P

_D

AT

A[2

6]

B1

PIN

_P

_D

AT

A[2

7]

E2

PIN

_P

_D

AT

A[2

8]

J3

PIN

_P

_D

AT

A[2

9]

C1

PIN

_P

_D

AT

A[3

0]

D1

PIN

_P

_D

AT

A[3

1]

E1

PIN

_P

_D

AT

A[3

2]

P1

PIN

_P

_D

AT

A[3

3]

Y2

PIN

_P

_D

AT

A[3

4]

F3

PIN

_P

_D

AT

A[3

5]

J2

PIN

_P

_G

W_

NV

3

PIN

_P

_A

DS

C_

NA

B2

PIN

_P

_A

DV

_N

AA

2

PIN

_F

_R

ES

ET

_N

C3

PIN

_F

_C

E_

NE

4

PIN

_F

_R

EA

DY

D3

PIN

_F

_W

E_

NA

3

PIN

_F

_O

E_

NF

4

PIN

_F

_B

YT

E_

NB

3

PIN

_S

DA

[0]

R2

1

PIN

_S

DA

[1]

T2

2

PIN

_S

DA

[2]

T2

3

PIN

_S

CL

[0]

P2

1

PIN

_S

CL

[1]

R2

2

PIN

_S

CL

[2]

R2

3

PIN

_T

ES

T[0

]H

22

PIN

_T

ES

T[1

]G

23

PIN

_T

ES

T[2

]H

21

PIN

_T

ES

T[3

]G

22

PIN

_T

ES

T[4

]F

23

PIN

_T

ES

T[5

]G

21

PIN

_T

ES

T[6

]F

21

PIN

_T

ES

T[7

]F

22

PIN

_T

ES

T[8

]D

23

PIN

_T

ES

T[9

]E

23

PIN

_T

ES

T[1

0]

C2

3

PIN

_T

ES

T[1

1]

E2

2

PIN

_T

ES

T[1

2]

E2

1

PIN

_T

ES

T[1

3]

B2

3

PIN

_T

ES

T[1

4]

D2

2

PIN

_T

ES

T[1

5]

C2

2

PIN

_A

CT

[0]

N2

1

PIN

_A

CT

[1]

P2

2

PIN

_A

CT

[2]

P2

3

PIN

_A

CT

[3]

M2

1

PIN

_A

CT

[4]

N2

2

PIN

_A

CT

[5]

N2

3

PIN

_A

CT

[6]

M2

3

PIN

_A

CT

[7]

M2

2

PIN

_A

CT

[8]

L2

1

PIN

_M

_C

LK

AB

23

PIN

_M

_D

AT

AA

A2

3

TP

16

TP

16

1

J5

4 H

EA

DE

R

J5

4 H

EA

DE

R

1 2 3 4

C4

9

C0

40

2

10

0n

F1

0V

C4

9

C0

40

2

10

0n

F1

0V

TP

26

TP

26

1

C5

8

0.1

U

C5

8

0.1

U

C4

4

0.1

U

C4

4

0.1

U

C4

61

00

nF

C0

40

2

C4

61

00

nF

C0

40

2

TP

35

TP

35

1

TP

18

TP

18

1

TP

4T

P4

1

FL

T1

Am

be

rF

LT

1A

mb

er

R5

6

10

K

R5

6

10

K

TP

60

TP

60

1

TP

49

TP

49

1

BU

ZZ

1

BU

ZZ

ER

_3

VD

C

BU

ZZ

1

BU

ZZ

ER

_3

VD

C

1 2

TP

27

TP

27

1

R7

10

KR

71

0K

FL

T4

Am

be

rF

LT

4A

mb

er

R4

41

K-5

%R

44

1K

-5%

U3

DN

P_

CY

14

B2

56

L-S

P3

5X

CT

U3

DN

P_

CY

14

B2

56

L-S

P3

5X

CT

Vca

p1

A1

62

A1

43

A1

24

A7

5

A6

6

A5

7

NC

18

A4

9

NC

21

0

NC

31

1

NC

41

2

VS

S1

13

NC

51

4

NC

61

5

DQ

01

6

A3

17

A2

18

A1

19

A0

20

DQ

12

1

DQ

22

2

NC

72

3

NC

82

4

VS

S2

36

NC

11

37

NC

12

38

NC

13

39

A1

14

0N

C1

44

1A

94

2A

84

3A

13

44

NC

10

35

NC

93

4

DQ

63

3

OE

#3

2

A1

03

1

CE

#3

0

VC

C2

48

A1

54

7

HS

B#

46

WE

#4

5

DQ

72

9

DQ

52

8

DQ

42

7

DQ

32

6

VC

C1

25

TP

39

TP

39

1

R7

21

K-5

%R

72

1K

-5%

TP

36

TP

36

1

TP

19

TP

19

1

TP

50

TP

50

1

R3

81

0R

R3

81

0R

TP

28

TP

28

1

AC

T2

GR

EE

NA

CT

2G

RE

EN

TP

57

TP

57

1

TP

7T

P7

1

TP

14

TP

14

1

C4

5

10

0n

F

C0

40

2

C4

5

10

0n

F

C0

40

2

TP

55

TP

55

1

R6

10

K

R6

10

K

TP

46

TP

46

1

TP

65

TP

65

1T

P6

2T

P6

21

R2

21

0R

R2

21

0R

TP

37

TP

37

1

TP

20

TP

20

1

R5

10

K

R5

10

K

TP

51

TP

51

1

TP

59

TP

59

1

C5

7

0.1

U

C5

7

0.1

U

TP

29

TP

29

1

TP

11

TP

11

1

FL

T2

Am

be

rF

LT

2A

mb

er

R6

91

K-5

%R

69

1K

-5%

+C

41

10

0u

F/1

6V

+C

41

10

0u

F/1

6V

R5

11

0K

R5

11

0K

C5

0

0.1

U

C5

0

0.1

U

R5

41

0K

R5

41

0K

R7

01

K-5

%R

70

1K

-5%

R3

71

0R

R3

71

0R

J3

SH

_2

x5

_2

.54

J3

SH

_2

x5

_2

.54

11

22

33

44

55

66

77

88

99

10

10

TP

8T

P8

1

R1

81

0R

R1

81

0R

TP

5T

P5

1

TP

38

TP

38

1

TP

21

TP

21

1

TP

52

TP

52

1

R3

4

10

K

R3

4

10

K

R9

R0

60

30R

R9

R0

60

30R

TP

30

TP

30

1

R1

15

6R

R1

15

6R

R1

6

10

K_

X

R1

6

10

K_

X

R4

8

10

K

R4

8

10

K

R5

51

0K

R5

51

0K

R232.0K R232.0K

TP

12

TP

12

1

FL

T3

Am

be

rF

LT

3A

mb

er

J2 DN

P_

SJ-3

52

3A

UD

IO-J

AC

K-S

J-3

52

3-S

MT

J2 DN

P_

SJ-3

52

3A

UD

IO-J

AC

K-S

J-3

52

3-S

MT

GN

D1

RX

O2

TX

I3

J4

4

J5

5

R1

44

.7K

-5%

R0

60

3

R1

44

.7K

-5%

R0

60

3

TP

40

TP

40

1

R6

3

10

K

R6

3

10

K

TP

22

TP

22

1

TP

66

TP

66

1

R7

11

K-5

%R

71

1K

-5%

R262.0K R262.0KR252.0K R252.0K

TP

6T

P6

1

TP

31

TP

31

1

R242.0K R242.0K

R302.0K R302.0KA

CT

1G

RE

EN

AC

T1

GR

EE

N

AC

T4

GR

EE

NA

CT

4G

RE

EN

TP

42

TP

42

1

R292.0K R292.0KR282.0K R282.0KR272.0K R272.0K

R1

25

6R

R1

25

6R

R1

55

6R

R1

55

6R

C4

7

10

0n

F

C0

40

2

C4

7

10

0n

F

C0

40

2

TP

43

TP

43

1

R1

35

6R

R1

35

6RT

P2

3T

P2

31

JP

3JP

3

12

TP

32

TP

32

1

AC

T3

GR

EE

NA

CT

3G

RE

EN

C4

3

10

0n

F

C0

40

2

C4

3

10

0n

F

C0

40

2

TP

44

TP

44

1

C4

21

00

nF

C0

40

2

C4

21

00

nF

C0

40

2

TP

9T

P9

1

LE

D1

GR

EE

N/Y

EL

LO

Wle

d_

bi_

sm

d4

LE

D1

GR

EE

N/Y

EL

LO

Wle

d_

bi_

sm

d4

C11A12C23A24

TP

3T

P3

1

TP

58

TP

58

1

R5

2

10

K

R5

2

10

K TP

53

TP

53

1

TP

56

TP

56

1

R5

31

0K

R5

31

0K

R4

9

10

K

R4

9

10

K

TP

24

TP

24

1

R4

31

00

RR

43

10

0R

TP

33

TP

33

1

R2

01

0R

R2

01

0R

I2C

0

22

-05

-50

35

I2C

0

22

-05

-50

35

11

22

33

TP

10

TP

10

1

TP

41

TP

41

1

TP

47

TP

47

1

U6

DN

P_

AR

C1

00

_1

6P

_X

U6

DN

P_

AR

C1

00

_1

6P

_X

NC

11

NC

22

NC

33

NC

45

NC

56

RS

T7

SC

L8

VC

C4

SD

A1

9S

DA

21

0G

ND

11

GN

D_

A1

2N

C6

13

NC

71

4


88SE9445 Board Schematics 4-5




VDDO1

AVDD[8]-1

AVDD[8]-1

AVDD[8]-2

AVDD_25

VDDO2

VDDO1

VAA_ANA

VAA_0_3

VAA_4_7

AVDD[8]-2

AVDD_25

1V0_core

VDDO2

1V0_core

1V0_core

VAA_ANA

VAA_0_3

VAA_4_7

2V5

3V3

1V0

2V5

2V5

2V5

1V8

J10

Banana Plug_Blue

J10

Banana Plug_Blue

C68

1000P

C68

1000P

C54

0.1U

C54

0.1U

C65

2.2U

C65

2.2U

C105

0.1U

C105

0.1U

R207 0.1-1%R0805

R207 0.1-1%R0805

C51

0.1U

C51

0.1U

C101

0.01U

C101

0.01U

C94

10U_10V

C94

10U_10V

FB10

FB_1A

FB10

FB_1A

1 2

C104

0.1U

C104

0.1U

R210 0.1-1%R0805

R210 0.1-1%R0805

R208 0.1-1%R0805

R208 0.1-1%R0805

R209 0.1-1%R0805

R209 0.1-1%R0805

C63

0.01U

C63

0.01U

C85

0.01U

C85

0.01U

C96

0.1U

C96

0.1U

C80

10U_10V

C80

10U_10V

C56

1000P

C56

1000P

C61

2.2U

C61

2.2U

C71

0.01U

C71

0.01U

C92

0.01U

C92

0.01U

C99

0.01U

C99

0.01U

C102

0.01U

C102

0.01U

C72

1000P

C72

1000P

C69

2.2U

C69

2.2U

C97

0.1U

C97

0.1U

C83

0.1U

C83

0.1U

C87

0.01U

C87

0.01U

R206 0.1-1%R0805

R206 0.1-1%R0805

J8

GND

J8

GND

C78

0.1U

C78

0.1U

C52

0.01U

C52

0.01U

C107

0.01U

C107

0.01U

C79

0.01U

C79

0.01U

C103

10U_10V

C103

10U_10V

FB8

FB_4A

FB8

FB_4A

1 2

C81

0.1U

C81

0.1U

C64

1000P

C64

1000P

C108

0.01U

C108

0.01U

R205 0.1-1%R0805

R205 0.1-1%R0805

J6

Banana Plug_WHITE

J6

Banana Plug_WHITE

C84

0.01U

C84

0.01U

J7

Banana Plug_RED

J7

Banana Plug_RED

FB7

FB_1A

FB7

FB_1A

1 2

J4

Banana Plug_YELLOW

J4

Banana Plug_YELLOW

C109

0.01U

C109

0.01U

C91

0.1U

C91

0.1U

C62

0.1U

C62

0.1U

C106

0.1U

C106

0.1U

FB9

FB_1A

FB9

FB_1A

1 2

C88

0.01U

C88

0.01U

FB4

FB_1A

FB4

FB_1A

1 2

FB2

FB_1A

FB2

FB_1A

1 2

C53

2.2U

C53

2.2U

FB6

FB_1A

FB6

FB_1A

1 2

FB3

FB_2A

FB3

FB_2A

1 2

C98

0.01U

C98

0.01U

C95

0.1U

C95

0.1U

C77

10U_10V

C77

10U_10V

C100

0.01U

C100

0.01U

POWER/GND

0449ES88C1U

POWER/GND

0449ES88C1U

VSS0A1

VSS1AC1

VSS2A4

VSS3B4

VSS4V4

VSS5W4

VSS6C5

VSS7D5

VSS8E5

VSS9V5

VSS10W5

VSS11Y5

VSS12AA5

VSS13A6

VSS14B6

VSS15E6

VSS16F6

VSS17V6

VSS18W6

VSS19AB6

VSS20AC6

VSS21C7

VSS22D7

VSS23E7

VSS24J7

VSS25K7

VSS26L7

VSS27M7

VSS28N7

VSS29P7

VSS30R7

VSS31W7

VSS32Y7

VSS33AA7

VSS34A8

VSS35B8

VSS36E8

VSS37F8

VSS38J8

VSS39K8

VSS40L8

VSS41M8

VSS42N8

VSS43P8

VSS44R8

VSS45W8

VSS46AB8

VSS47AC8

VSS48C9

VSS49D9

VSS50E9

VSS51J9

VSS52K9

VSS53L9

VSS54M9

VSS55N9

VSS56P9

VSS57R9

VSS58W9

VSS59Y9

VSS60AA9

VSS61A10

VSS62B10

VSS63E10

VSS64J10

VSS65K10

VSS66L10

VSS67M10

VSS68N10

VSS69P10

VSS70R10

VSS71W10

VSS72AB10

VSS73AC10

VSS74C11

VSS75D11

VSS76E11

VSS77J11

VSS78K11

VSS79L11

VSS80M11

VSS81N11

VSS82P11

VSS83R11

VSS84W11

VSS85Y11

VSS86AA11

VSS87A12

VSS88B12

VSS89E12

VSS90J12

VSS91K12

VSS92L12

VSS93M12

VSS94N12

VSS95P12

VSS96R12

VSS97W12

VSS98AB12

VSS99AC12

VSS100C13

VSS101D13

VSS102E13

VSS103F13

VSS104J13

VSS105K13

VSS106L13

VSS107M13

VSS108N13

VSS109P13

VSS110R13

VSS111W13

VSS112Y13

VSS113AA13

VSS114A14

VSS115B14

VSS116E14

VSS117J14

VSS118K14

VSS119L14

VSS120M14

VSS121N14

VSS122P14

VSS123R14

VSS124W14

VSS125AB14

VSS126AC14

VSS127C15

AVDD[8]-1_0H13

AVDD[8]-1_1F14

AVDD[8]-1_2H14

AVDD[8]-1_3F15

AVDD[8]-1_4H15

AVDD[8]-1_5F16

AVDD[8]-1_6H16

AVDD[8]-2_0F9

VAA_ANAU20

VDDO1_0H20

VDDO1_1J20

VDDO1_2K20

VDDO1_3L20

VDDO1_4M20

VDDO1_5N20

VDDO1_6P20

VDDO1_7R20

VDD0H6

VDD1J6

VDD2K6

VDD3L6

VDD4M6

VDD5N6

VDD6P6

VDD7R6

VDD8T6

VDD9H7

VDD10T7

VDD11H8

VDD12T8

VDD13T9

VDD14T10

VDD15T11

VDD16T12

VDD17T13

VDD18T14

VDD19T15

VDD20T16

VDD21H17

VDD22T17

VDD23H18

VDD24J18

VDD25K18

VDD26L18

VDD27M18

VDD28N18

VDD29P18

VDD30R18

VDD31T18

VAA[0_3]_0V7

VAA[0_3]_1V8

VAA[0_3]_2V9

VAA[0_3]_3V10

VAA[4_7]_0V12

VAA[4_7]_1V13

VAA[4_7]_2V14

VAA[4_7]_3V15

VDDO2_0H4

VDDO2_1J4

VDDO2_2K4

VDDO2_3L4

VDDO2_4M4

VDDO2_5N4

VDDO2_6P4

VSS154E17

VSS155F17

VSS156J17

VSS157K17

VSS158L17

VSS159M17

VSS160N17

VSS161P17

VSS162R17

VSS163V17

VSS164W17

VSS165Y17

VSS166AA17

VSS167A18

VSS168B18

VSS169E18

VSS170V18

VSS171W18

VSS172AB18

VSS173AC18

VSS174C19

VSS175D19

VSS176E19

VSS177F19

VSS178V19

VSS179W19

VSS180Y19

VSS181AA19

VSS182A20

VSS183B20

VSS184E20

VSS185F20

VSS186G20

VSS187V20

VSS188W20

VSS189AB20

VSS190AC20

VSS191C21

VSS192D21

VSS193Y21

VSS194AA21

VSS195A22

VSS196B22

VSS197A23

VSS198AC23

VS

S135

R15

VS

S136

W15

VS

S137

Y15

VS

S138

AA

15

VS

S139

A16

VS

S140

B16

VSS128D15

VSS129J15

VSS130K15

VSS131L15

VSS132M15

VSS133N15

VSS134P15

VS

S141

E16

VS

S142

J16

VS

S143

K16

VS

S144

L16

VS

S145

M16

VS

S146

N16

VS

S147

P16

VS

S148

R16

VS

S149

W16

VS

S150

AB

16

VS

S151

AC

16

VS

S152

C17

VS

S153

D17

AVDD[8]-2_1H9

AVDD[8]-2_2F10

AVDD[8]-2_3H10

AVDD[8]-2_4F11

AVDD[8]-2_5H11

AVDD[8]-2_6H12

AVDD25_0F7

AVDD25_1F18

VAA[0_3]_4V11

VAA[4_7]_4V16

VDDO1_8T20

VDDO2_7R4

VDDO2_8T4

VDDO2_9U4

VDDO2_10F5

C67

0.01U

C67

0.01U

C70

0.1U

C70

0.1U

C93

0.01U

C93

0.01U

TP64TP64

1

TP63TP63

1

C82

0.1U

C82

0.1U

C86

0.01U

C86

0.01U

C89

10U_10V

C89

10U_10V

C90

0.1U

C90

0.1U

C55

0.01U

C55

0.01U

FB5

FB_2A

FB5

FB_2A

1 2

C66

0.1U

C66

0.1U







SYSTEM 1.0V/ 3A

REG_PGOOD

VSET1

PSET1

VSET2

PSET2

SDI

3V3

3V3

3V3

3V3

2V5

1V8

3V3

1V0

3V3

3V3

REG_PGOOD2

C130

0.1U

C130

0.1U

U8

88PG8237

U8

88PG8237

EN1

SFB22

SVIN3

SGND4

SFB15

SDI6

SW1_17

PGND18

SW1_09

PVIN110

POR111

PSET112

VSET113

VSET214

PSET215

POR216

PVIN217

SW2_018

PGND219

SW2_120

L32.0uHL32.0uH

C125

22U

C125

22U

R_PSET1

0R

R_PSET1

0R

R6518.7K-1%R0402

R6518.7K-1%R0402

L22.0uHL22.0uH

NORMAL:5APEAK:7.5A

U9 88PG877

NORMAL:5APEAK:7.5A

U9 88PG877

VS

ET

1

EN2

VBS3

SW14

PVIN5PVIN6PVIN7

SW28

PGND9

PGND10

PGND11

SW312

SGND13

SFB14

SVIN15

SDI16

POR17

PS

ET

18

SW419

MTH1

Hole

MTH1

Hole

1

R59

10R

R59

10R

C128

22U

C128

22U

R67100KR67100K

C127

0.1U

C127

0.1U

MTH2

Hole

MTH2

Hole

1

C131

0.1U

C131

0.1U

+ C14322uF6V3C0805

+ C14322uF6V3C0805

R66 1K-5% R0402R66 1K-5% R0402

+

C14422uF6V3C0805

+

C14422uF6V3C0805

R62100KR62100K

R61

100K

R61

100K

R_VSET2

97.6K

R_VSET2

97.6K

L6

FDV0630-1R03.1A

1.0uH

L6

FDV0630-1R03.1A

1.0uH

R64

0R

R64

0R

+

C14522uF6V3C0805

+

C14522uF6V3C0805

C124

22U

C124

22U

C123

22U

C123

22U

R-VSET1

165K

R-VSET1

165K

C126

22U

C126

22U

R60

10K

R60

10K

C146

C0805

4.7uF10V

C146

C0805

4.7uF10V

+ C14222uF6V3C0805

+ C14222uF6V3C0805

R_PSET2

0R

R_PSET2

0R

C14747nF C0603C14747nF C0603

C129

22U

C129

22U

C122

0.1U

C122

0.1U

R58100KR58100K

C141

C0402

100nF10V

C141

C0402

100nF10V

+ GREEN

LED2

+ GREEN

LED2

R148

R0402

10

R148

R0402

10

C121

0.1U

C121

0.1U

R158

1K-5%

R158

1K-5%


Layer Stack-Up 4-7


4.2 Layer Stack-Up

The following layer stack up is recommended

Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes

Layer 2–Solid Ground Plane

Layer 3–Power Plane and Low Speed Signals

Layer 4–Power Plane

Layer 5–Solid Ground Plane

Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes

5 mil traces and 5 mil spacing are the recommended minimum requirements.

4.2.1 Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes

All active parts are to be placed on the topside. Some of the differential pairs for SAS/SATA and PCIe are routed on the top layer, differential 100 ohm impedance needs to be maintained for those high-speed signals.

4.2.2 Layer 2–Solid Ground Plane

A solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.

4.2.3 Layer 3–Power Plane and Low Speed Signals

Use solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.

4.2.4 Layer 4–Power Plane

Use solid planes on layer 4 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.

4.2.5 Layer 5–Solid Ground Plane

A solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.


4-8 Layer Stack-Up


4.2.6 Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes

Some of the differential pairs for SAS/SATA and PCIe are routed on the top layer, differential 100Ω impedance needs to be maintained for those high speed signals.


Power Supply 4-9


4.3 Power Supply

The 88SE9445 operates using the following power supplies:

VDD Power (1.0V) for the digital core

PCIe Analog Power Supply (1.8V)

SAS/SATA Analog Power Supply (2.5V)

General I/O Power (3.3V)

4.3.1 VDD Power (1.0V)

All digital power pins (VDD pins) must be connected directly to a VDD plane in the power layer with short and wide traces to minimize digital power-trace inductances.

Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD pins with the following dimensions:

0.001 µF (1 capacitor)

0.1 µF (2 capacitors)

2.2 µF (1 ceramic capacitor)

The combinations of small capacitors are used to suppress switching noise at various frequency ranges. The 2.2 µF ceramic decoupling capacitor is required to filter the lower frequency power-supply noise.

To reduce system noise, place high-frequency surface-mount monolithic ceramic bypass capacitors as close as possible to the channel VDD pins. Place at least one decoupling capacitor on each side of the IC package.

4.3.2 PCIe Analog Power Supply (1.8V)

The analog supply provides power for the PCIe link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.

4.3.3 SAS/SATA Analog Power Supply (2.5V)

The analog supply provides power for the SAS/SATA link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.

4.3.4 General I/O Power (3.3V)

A general I/O power supply provides power to the GPIO, flash and I2C blocks. A stable and clean power source is desired. Use proper bypass capacitors to provide a clean power source with good stability. A typical capacitor value combination is 0.1µF, and 2.2 µF.


4-10 Power Supply


4.3.5 Bias Current Resistor (RSET)

Connect a 6.04KΩ (1%) resistor between the ISET pin and the adjacent top ground plane. This resistor should lie as close as possible to the ISET pin. Avoid routing noisy signals close to the ISET pin.


PCB Trace Routing 4-11


4.4 PCB Trace Routing

The stack-up parameters for the reference board are shown in Table 4-1.

Table 4-1 PCB Board Stack-up Parameters

LayerLayer

DescriptionCopper Weight

(oz)Target Impedance

(±10%)

1 Signal 0.5 50

2 GND 1 N/A

3 Power and Signal

1 50

4 Power 1 N/A

5 GND 1 N/A

6 Signal 0.5 50


4-12 Recommended Layout


4.5 Recommended Layout

High-speed designs must consist of a good board stack-up and careful consideration of the power planes. For the 88SE9445, the following power planes are required:

VDDIO_C, VDDIO_D, and VDDIO_P power plane (3.3V power source for the digital I/O pins)

VDD (1.0V power source for the core and digital circuitry)

VAA (2.5V power source for SAS/SATA analog)

AVDD (1.8V power source for PCIe analog)

Solid ground planes are recommended. However, special care should be taken when routing VAA, AVDD, and VSS pins.

The following general tips describe what should be considered when determining your stack-up and board routing. These tips are not meant to substitute for consulting with a signal-integrity expert or doing your own simulations.

Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in every situation.

Do not split ground planes.

Keep good spacing between possible sensitive analog circuitry on your board and the digital signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return path for routing layers. Try to provide at least one ground plane adjacent to all routing layers (see Figure 4-5).

Keep trace layers as close as possible to the adjacent ground or power planes.

This helps minimize crosstalk and improve noise control on the planes.

Figure 4-5 Trace Has At Least One Solid Plane For Return Path

When routing adjacent to only a power plane, do not cross splits.

Route traces only over the power plane that supplies both the driver and the load. Otherwise, provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent power plane.

Critical signals should avoid running parallel and close to or directly over a gap.

This would change the impedance of the trace.

Separate analog powers onto opposing planes.

This helps minimize the coupling area that an analog plane has with an adjacent digital plane.

GND

V2

V1


Recommended Layout 4-13


For dual strip-line routing, traces should only cross at 90 degrees.

Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control impedance.

Planes should be evenly distributed in order to minimize warping.

Calculating or modeling impedance should be made prior to routing.

This helps ensure that a reasonable trace thickness is used and that the desired board thickness is available. Consult with your board fabricator for accurate impedance.

Allow good separation between fast signals to avoid crosstalk.

Crosstalk increases as the parallel traces get longer.

When packages become smaller, route traces over a split power plane

Smaller packages force vias to become smaller, thereby reducing board thickness and layer counts, which might create the need to route traces over a split power plane. Some alternatives to provide return path for these signals are listed below.

Caution must be used when applying these techniques. Digital traces should not cross over analog planes, and vice-versa. All of these rules must be followed closely to prevent noise contamination problems that might arise due to routing over the wrong plane.

By tightly controlling the return path, control noise on the power and ground planes can be controlled.

Place a ground layer close enough to the split power plane in order to couple enough to provide buried capacitance, such as SIG-PWR-GND (see Figure 4-6). Return signals that encounter splits in this situation simply jumps to the ground plane, over the split, and back to the other power plane. Buried capacitance provides the benefit of adding low inductance decoupling to your board. Your fabricator may charge for a special license fee and special materials. To determine the amount of capacitance your planes provide, use the following equation:

Where ER is the dielectric coefficient, L • W represents the area of copper, and H is the separation between planes.

Provide return-path capacitors that connect to both power planes and jumps the split. Place them close to the traces so that there is one capacitor for every four or five traces. The capacitors would then provide the return path (see Figure 4-7).

Allow only static or slow signals on layers where they are adjacent to split planes.

Figure 4-6 shows the ground layer close to the split power plane.

Figure 4-6 Close Power and Ground Planes Provide Coupling For Good Return Path

C 1.249 10 13–• Er• L• W H⁄•=

V2 PLANE

GND PLANE

V1 PLANEH


4-14 Recommended Layout


Figure 4-7 shows the thermal ground plane in relation to the return-path capacitor.

Figure 4-7 Suggested Thermal Ground Plane On Opposite Side of Chip

V1

V2

Part 1: Chip OverviewElectrical Specifications

5-1


5 ELECTRICAL SPECIFICATIONS

This chapter contains the following sections:

Absolute Maximum Ratings

Recommended Operating Conditions

DC Electrical Characteristics

Thermal Data

AC Timing


5-2 Absolute Maximum Ratings


5.1 Absolute Maximum Ratings

CAUTION: Exposure to conditions at or beyond the maximum rating may damage the device. Operation beyond the recommended operating conditions (Table 5-2) is neither recommended nor guaranteed.

Note: Before designing a system, it is recommended that you read application note AN-63: Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.

Table 5-1 Absolute Maximum Ratings

Parameter Symbol Minimum Typical Maximum Units

Absolute Analog Power for PCIe PHY AVDD[8:0] 1.62 1.8 1.98 V

Absolute Analog Power for SAS/SATA PHY, Chip PLL

VAA[7:0], VAA_ANA

2.25 2.5 2.75 V

Absolute Power for Digital Core VDD 0.9 1.0 1.1 V

Absolute Digital I/O Power VDDO1/VDDO2 3 3.3 3.6 V


Recommended Operating Conditions 5-3


5.2 Recommended Operating Conditions

CAUTION: Operation beyond the recommended operating conditions is neither recommended nor guaranteed.

Table 5-2 Recommended Operating Conditions


Analog Power for PCIe PHY AVDD[8:0] 1.71 1.8 1.89 V

Analog Power for SAS/SATA PHY, Chip PLL

VAA[7:0], VAA_ANA

2.38 2.5 2.63 V

Digital Core Power VDD 0.95 1.0 1.05 V

Digital I/O Power VDDO1/VDDO2 3.14 3.3 3.47 V

Internal Bias Reference ISET, PIN_ISET 5.74 6.04 6.34 KΩ

Ambient Operating Temperature TA 0 N/A 70 °C

Junction Operating Temperature TJ 0 N/A 125 °C


5-4 DC Electrical Characteristics


5.3 DC Electrical Characteristics

CAUTION: Operation beyond the recommended operating conditions is neither recommended nor guaranteed.

Table 5-4 shows the internal pull-up and pull-down strength.

Table 5-3 DC Electrical Characteristics


Analog Power for PCIe PHY 1.8V IAVDD 0.19 0.215 0.24 A

Analog Power for SAS/SATA PHY 2.5V, Chip PLL

IVAA 0.55 0.62 0.69 A

Digital Core Power IVDD 1.5 1.94 2.93 A

Digital I/O Power IVDDO 9.2 10.5 11.6 mA

Input Low Voltage of Digital I/O VIL -0.4 N/A 0.3 × VDDOx V

Input High Voltage of Digital I/O VIH 0.7 × VDDOx N/A VDDOx + 0.4 V

Output Low Voltage of Digital I/O VOL N/A 0.13 N/A V

Output High Voltage of Digital I/O VOH 2.0 VDDOx*

* VDDOx: VDDO1/VDDO2.

N/A V

Table 5-4 Internal Pull-Up and Pull-Down Strength

Specifications Condition Minimum Nominal Maximum Unit

Pull-Up Strength V(PAD) = 0.5 × VDDO 10 N/A 50 µA

V(PAD) = 0 10 N/A 65 µA

Pull-Down Strength V(PAD) = 0.5 × VDDO 10 N/A 50 µA


Thermal Data 5-5


5.4 Thermal Data

It is recommended to read application note AN-63 Thermal Management for Selected Marvell® Products (Document Number MV-S300281-00) and the ThetaJC, ThetaJA, and Temperature Calculations White Paper, available from Marvell, before designing a system. These documents describe the basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.

Table 5-5 provides the thermal data for the 88SE9445. The simulation was performed according to JEDEC standards. The heat sink is 25.4 mm × 25.4 mm × 25 mm.

Table 5-5 shows the values for the package thermal parameters for the 481-ball TFBGA mounted on a 4-layer PCB.

Table 5-5 Package Thermal Data, 4-Layer PCB*

* All data is based on parts mounted on a 4” x 4.5” JEDEC 4L PCB.

Parameter DefinitionAirflow Value

0 m/s 1 m/s 2 m/s 3 m/s

θJA Thermal resistance: junction to ambient (no heat sink)

16.2 C/W 13.9 C/W 13.0 C/W 12.6 C/W

θJA Thermal resistance: junction to ambient (with heat sink)

11.7 C/W 8.4 C/W 7.8 C/W 7.6 C/W

θJC Thermal resistance: junction to case

5.30 C/W N/A N/A N/A


5-6 AC Timing


5.5 AC Timing

This section discusses the following topics:

SATA

PCIe

Parallel Flash and NVSRAM

5.5.1 SATA

This product conforms to AC timing requirements as specified in the Serial ATA Revision 3.0 Specification (www.sata-io.org).

5.5.2 PCIe

This product conforms to AC timing requirements as specified in the PCIe® Base 2.0 specification (www.pcisig.com/).

5.5.3 Parallel Flash and NVSRAM

This section describes the timing for Parallel Flash and NVSRAM.


AC Timing 5-7


Figure 5-1 illustrates the Parallel Flash and NVSRAM Read timing, and Table 5-6 provides parameter information for the timing diagram.

Figure 5-1 Parallel Flash / NVSRAM Read Timing

Note: Tclk—Internal system clock cycle, default value is 3.33ns.

Table 5-6 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing

Parameter Description NVSRAM Parallel Flash Unit

tRC Read Cycle Time (NV_RD_CYCLE_TM (R0C968h [7:0]) + 2) × Tclk

(FLSH_RD_CYCLE_TM (R0C978h [7:0]) + 2) × Tclk

ns

tRCEL Read CE Assert Time (NV_RD_CE_ASSRT_TM (R0C96Ch [23:16]) + 1) × Tclk

(FLSH_RD_CE_ASSRT_TM (R0C97Ch [23:16]) + 1) × Tclk

ns

tRCEH Read CE Deassert Time (NV_RD_CE_DEASSRT_TM (R0C96Ch [31:24]) + 2) × Tclk

(FLSH_RD_CE_DEASSRT_TM (R0C97Ch [31:24]) + 2) × Tclk

ns

tOEL Read OE Assert Time (NV_RD_OE_ASSRT_TM (R0C96Ch [7:0]) + 1) × Tclk

(FLSH_RD_OE_ASSRT_TM (R0C97Ch [7:0]) + 1) × Tclk

ns

tOEH Read OE Deassert Time (NV_RD_OE_DEASSRT_TM (R0C96Ch [15:8]) + 2) × Tclk

(FLSH_RD_OE_DEASSRT_TM (R0C97Ch [15:8]) + 2) × Tclk

ns

tACC Read Data Latch Time (NV_RD_DATA_LTCH_TM (R0C968h [15:8]) + 1) × Tclk - 20

(FLSH_RD_DATA_LTCH_TM (R0C978h [15:8]) + 1) × Tclk - 20

ns

Address Valid

Input Data Valid

tRC

tRCEH

tRCEL

tOEL

tACC

tOEH

P_ADDR

CE_N

OE_N

P_DATA


5-8 AC Timing


Figure 5-2 illustrates the Parallel Flash and NVSRAM Write timing, and Table 5-7 provides parameter information for the timing diagram.

Figure 5-2 Parallel Flash / NVSRAM Write Timing

Table 5-7 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing

Parameter Description NVSRAM Parallel Flash Unit

tWC Write Cycle Time (NV_WRT_CYCLE_TM (R0C960h [7:0]) + 2) × Tclk

(FLSH_WRT_CYCLE_TM (R0C970h [7:0]) + 2) × Tclk

ns

tWCEL Write CE Assert Time (NV_CE_ASSRT_TM (R0C960h [15:8]) + 1) × Tclk

(FLSH_CE_ASSRT_TM (R0C970h [15:8]) + 1) × Tclk

ns

tWCEH Write CE Deassert Time (NV_CE_DEASSRT_TM (R0C960h [23:16]) + 2) × Tclk

(FLSH_CE_DEASSRT_TM (R0C970h [23:16]) + 2) × Tclk

ns

tWEL Write WE Assert Time (NV_WRT_WE_ASSRT_TM (R0C964h [7:0]) + 1) × Tclk

(FLSH_WRT_WE_ASSRT_TM (R0C974h [7:0]) + 1) × Tclk

ns

tWEH Read WE Deassert Time (NV_WRT_WE_DEASSRT_TM (R0C964h [15:8]) + 2) × Tclk

(FLSH_WRT_WE_DEASSRT_TM (R0C974h [15:8]) + 2) × Tclk

ns

tDL Write Data IO Enable Time

(NV_WRT_DATA_IO_EN_TM (R0C964h [23:16]) + 1) × Tclk

(FLSH_WRT_DATA_IO_EN_TM (R0C974h [23:16]) + 1) × Tclk

ns

tDH Write Data IO Disable Time

(NV_WRT_DATA_IO_DSBL_TM (R0C964h [31:24]) + 2) × Tclk

(FLSH_WRT_DATA_IO_DSBL_TM (R0C974h [31:24]) + 2) × Tclk

ns

Address Valid

tWC

tWCEH

tWCEL

tWEL

tDH

tWEH

Output Data ValidtDL

P_ADDR

CE_N

WE_N

P_DATA

Marvell Technology Groupwww.marvell.com

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