MARS

A Scan-Island Based Design EnablingPre-Bond Testability in Die-Stacked

Microprocessors

Dean L. Lewis Hsien-Hsin S. LeeGeorgia Institute of Technology

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 2/27

Outline

Introduction to 3DMotivationChallenges

DesignExperimental Results

Conclusion

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 3/27

3D Integration

• Technology– Stack multiple active layers vertically– Tightly integrate with die to die (d2d) vias

• Benefits– Routing freedom– Higher performance– Lower power

Kiran Puttaswamy,“Designing High-Performance Microprocessors in 3-Dimensional Integration Technology,”

Ph.D. dissertation, Georgia Institute of Technology, Atlanta, GA, USA, 2007

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 4/27

3D Die Stacking

Layer 1

Layer 2

Layer 3

Layer 4

Face to Face

Back to Back

Face to Back

Bond Pads

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 5/27

3D Assembly

Wafer to WaferWafer to Die

Die to Die

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 6/27

3D Integration and Testability

CMOS

DRAM

Analog TechnologyLevel

BitLine0

BitLine1

BitLine2

BitLine0

BitLine1

BitLine2

CircuitsLevel

ALU 1

ALU 2

ALU 3ArchitectureLevel

ALU 4

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 7/27

Motivation

1 layer

2 layers

4 layers

8 layers

16 layers

100% 80%

100%

0%

Single Layer Yield

Sta

ck Y

ield

95%

90%

81%

66%

44%

95%

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 8/27

Purpose

Enable Pre-bond 3D Test

Test StrategyHardware Requirements

Secondary Concerns

9/27

Pre-bond Challenges

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 10/27

Complete Architectural DesignPossible Pre-bond Partition

Fetch

Decode

ReorderBuffer

Issue

Out of OrderExecution

Commit

I Cache

D Cache

Pre-bond Test ChallengesIncomplete Circuits

Architectural Level Circuit Level

Complete Register File DesignPre-bond Circuit

10,000 +

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 11/27

Pre-bond Test ChallengesWafer Probing

Probing

Probe Pads

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 12/27

Pre-bond Clock Tree Nets

Pre-bond Test ChallengesSupporting Nets

Power, Ground, Clocks, Etc.

Complete Clock Tree Net

13/27

Proposed Solution

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 14/27

Test Strategy

Alpha 21364 3D Pre-bond Test

IEEE 1149.1 TAP

ISP ISP

LTC

LTC

IEEE 1149.1 TAP

CSC

CSC

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 15/27

Layer Border Scan Flops

Flags

Pip

elin

e S

tage

Reg

iste

rLowAdd

HighAdd

Bus From Another Layer Bus To Another Layer

Si So

Sca

n R

egis

ters

Pre-bondPost-bond

Test_Enable

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 16/27

Scan Flops Not Required

LowAdd

HighAdd

Bus From Another Layer Bus To Another Layer

Si So

Pre-bondPost-bond

Flags

Pip

elin

e S

tage

Reg

iste

r

LowAdd

HighAdd

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 17/27

Test Pads

Faceside Test Reuse Post-Bond

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 18/27

Power and Ground

Planar Die Die Stack

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 19/27

Clock Routing

Power/Routing Optimized Pre-bond Test Optimized

Lay

er

1

Lay

er

1

Lay

er

2

Lay

er

2

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 20/27

Real Clock Tree

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 21/27

Real 3D Clock Tree

Lay

er

1

Lay

er

2

Lay

er

3

Lay

er

4

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 22/27

Testable 3D Clock Tree

Lay

er

1

Lay

er

2

Lay

er

3

Lay

er

4

EN

CLKCLK

EN

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 23/27

More Trees Are Better

Pre-bond Test Reliability

X

24/27

Experiment and Results

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 25/27

Experiment

• Based on 21264 Architecture• Floorplanned microarchitecture blocks

– Two die layers

• Determined widths of inter-die buses• Laid out scan cell

E. Wong and S.-K. Lim. “3D Floorplanning with Thermal Vias.”In Design, Automation, and Test in Europe Proceedings, pp. 878-883, 2006.

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 26/27

Results

Layer 1

Layer 2

Scan Cell Size 75.8 μm2

Inter-die Vias 2397

Scan Cell Count

Two cells per via

4794

Area 0.363 mm2

Overhead 0.165%

ICache

FPEU1

IntQ

IEU4

IEU2

DCache

DTLB

IEU1 FPEU2

FPMap

DIS

LSQ

IRF1

FPRF

IMap

FPQ

BP

red

IRF2 IEU3

ITL

B

MemCtlr

FtchDcd

BIU

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 27/27

Conclusion

• Pre-bond test a necessity for integrating 10+ layers

• Pre-bond test can be achieved with current manufacturing technologies and test techniques

• Area cost is insignificant

• Clock can be designed to both enable pre-bond test and maximize power savings

28/27

Backup Slides

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 29/27

Scan and Non-Neighboring Blocks

I Fetch ALU

Si

So

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Clock Routing Area

2D Clock 3D Clock

Equal Wiring Required

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Clock Routing Area

2D Clock 3D Clock

50% More Wire in the Limit

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Clock Routing Layer

2D Clock 3D Clock

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 33/27

Die-to-Die BondingTezzaron Super-Via™

Standard Planar Die

Bulk Silicon

Device and Metal Layers

Top Layer Metal

S. Gupta, M. Hilbert, S. Hong, and R. Patti. “Techniques for Producing 3D ICs with High-Density Interconnect.”In Proceedings of the 21st International VLSI Multilevel Interconnection Conference, Waikoloa Beach, HI, USA, 2004

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 34/27

Die-to-Die BondingTezzaron Super-Via™

1 – Dialectric Fill

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Die-to-Die BondingTezzaron Super-Via™

2 – Super-Via™ Etch

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 36/27

Die-to-Die BondingTezzaron Super-Via™

3 – Barrier Deposition

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Die-to-Die BondingTezzaron Super-Via™

4 – Connection Etching

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 38/27

Die-to-Die BondingTezzaron Super-Via™

5 – Barrier and Cu Deposition

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 39/27

Die-to-Die BondingTezzaron Super-Via™

6 – Expose Bond

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 40/27

Die-to-Die BondingTezzaron Super-Via™

7 – Bond to Second Layer

ThermalDiffusionBonding

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 41/27

Die-to-Die BondingTezzaron Super-Via™

8 – Thin Second Layer

Grindingand CMP

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Die-to-Die BondingTezzaron Super-Via™

9 – Expose Via

Lewis and Lee, Enabling Pre-Bond Testability in 3D ICs (ITC’07) 43/27

Die-to-Die BondingTezzaron Super-Via™

10 – Repeat Pad Construction