mark montrose presentation pcb design-4 hours

© 1996/2000. Montrose, M.I., Printed Circuit Board Design Techniques for EMC Compliance. Wiley/IEEE Press. © 1999. Montrose, M.I., EMC and the Printed Circuit Board - Design Theory and Layout Made Simple. Wiley/IEEE Press.

Introduction to Printed Circuit Board Design

For EMC Compliance

Mark Montrose Principle Consultant

Montrose Compliance Services, Inc. + 1 (408) 247-5715

[email protected] www.montrosecompliance.com

1


Fundamentals of Signal Integrity

2


What is Signal Integrity

The ability of electrical signals to travel from a source to load through a dielectric without loss of signal amplitude or parametric values

In order to solve a signal integrity problem, one must first understand transmission lines and how they function both in theory and reality

There are two kinds of design engineers: “Those that have signal integrity problems, and those that will”

3

Signal Integrity Concerns

It only takes one item listed below to cause a signal integrity problem

• Incorrect transmission line routing • Improper terminations • Power and/or return plane bounce • Improper RF return current path • Mode conversion • Rise time degradation • Lossy transmission lines at higher

frequencies • Poor power distribution network • Hidden parasitics (RLC) • Propagation delays • Skin depth and dielectric loss • Non-monotonic edges • Excessive inductance in the

transmission line • Excessive ringing and reflection • Lossy transmission lines • Poor printed circuit board material

• Overshoot and undershoot • Impedance discontinuities • Delta I noise • RC delay • Crosstalk • Stubs and their lengths • Excessive capacitive loaded lines • IR drops • Via stubs • Excess attenuation • Non-monotonic edges • Signal skew • Gaps in planes • Dispersion • Impedance discontinuities • Unknown parasitic • Intra line skew • High dielectric losses


4


Aspects of High-Speed Problems Four aspects of high-speed problems are present in system designs 1. Signal quality: Reflections and distortions from impedance discontinuities

in the signal or return path can affect the quality of the signal. A transmitted signal should see the same impedance throughout all interconnects (includes vias and connectors).

2. Crosstalk between nets: Mutual capacitance and inductance exists, both within an ideal and non-ideal return path. One must keep spacing of traces greater than a minimal value while minimizing mutual inductance, keeping the return path impedance as low as possible.

3. Rail collapse: A voltage drop within the power and return system when digital components switch logic states. One must minimize the impedance of the power and return path along with the delta-I (current).

4. EMI: Can be developed as a result of poor signal integrity within a transmission line. Must minimize bandwidth, ground impedance and common-mode coupling.

Details on impedance discontinuities, transmission line routing, terminations, and simulations are presented later.

5


totaltotalpdo

oo CLt

I(x)V(x) =

CL = Z =

Lossless Transmission Line Equivalent Circuit Within a PCB

6


Lossy Transmission Line Equivalent Circuit Within a PCB

( ) ( )CjGLjRj LLLL +++=+=Γ ωωβα

( )( )CjG

LjRZoLL

LL

++

=ωω

characteristic impedance Zo =length line L =

may vary with frequency G ,R LL

jtxVxV o Γ−=ω )exp()exp(),(

7


Lossy Transmission Lines 1. Resistive losses - Constant with frequency. Attenuation, usually measured in

dB/unit distance, is proportional to the resistance per unit length of the conductor.

2. Skin effect losses - Proportional to the square root of frequency. As signal frequency increases, current flow retreats to the surface of the conductor flowing in a "skin" which becomes thinner with increasing frequency. Resistivity of the material stays the same, it is the cross section that decreases related to AC current flow.

3. Dielectric losses - The PCB material (core and prepreg) absorbs some of the electric field energy, which is directly proportional to frequency. Dielectric loss or dissipation factor (magnitude of energy loss) is not the same as dielectric constant (speed of signal travel).

4. Resonances - Typically caused by improperly terminated traces and split planes in addition to the lumped magnitude of both capacitance and inductance within power distribution networks.

8


Typical Transmission Line System

• Minimum reflections will occur when Zout = Zo and Zo= Zload • Maximum energy transfer occurs when Zout= Zo= Zload If the load is not matched, a voltage is reflected back toward the source. The value of reflected voltage (Vr) and the percentage of the propagation signal reflected back towards the source (%) is:

where Vr = reflected voltage Vo = source voltage RL = load resistance Zo = characteristic impedance of the transmission path When RL is less than Zo, a negative reflected wave exist. If RL is greater than Zo, a positive wave is observed. This reflected wave will bounce back and forth between source and driver until dielectric losses absorbs the signal.

Zo

V Source

Zout

RLoad

VloadVsource

oLoad

oLoad or

Z+RZ-RV = V 100

Z+ZZ-Z =reflection %

oL

oL×

RG174 - 50 Ω RG58 - 50 Ω RG59 - 75 Ω RG62 - 93 Ω TV Antenna - 300 Ω Cable TV - 75 Ω Twisted pairs - 70-120 Ω

9


Reflections – Poor Signal Integrity

Reflections will occur within a transmission line if not properly terminated. The following causes reflections. • Changes in trace width • Improperly matched termination networks • Lack of terminations • T-stubs, branched or bifurcated traces • Varying loads and logic families • Connector transitions • Any changes in impedance of the transmission line routing

Ringing indicates Rounding indicatesexcessive capacitancereflections (excessive inductance)

10


Crosstalk – Fundamental Aspects of Coupling

Zv= Zs (v)x ZL (v)Zs (v) ZL (v)+

Source Trace

Victim Trace

Victim Trace

Source TraceLm

Csv

CsvCvg

= Capacitance between source trace and victim trace= Capacitance between victim trace and ground

Csg = Capacitance between source trace and ground

Source Trace

Victim TraceCsv

Cvg

Z L (source)

Z L (victim)~

Zs (source)

VsZs (victim)

Inductive coupling

Csg

Ground plane or reference structureLm

Csv

AC

CA

B

B

D

D

Lm

11


Vs

Rs Ls

Rv Lv

Zg

Csg

Cvg

Z ZL1

L2Z

s1

Vv

Zs2

G (0V)

Schematic representation of a three wire circuit

MsvCsv

CsvCvg

= Capacitance between source trace and victim trace= Capacitance between victim trace and ground

Csg = Capacitance between source trace and ground

ZL1 ZL2

Csv

Msv

Vs

Zs1

Vv

Z s2

G (0V)

t

VsSource signal

t

Vv

Crosstalk onvictim trace

CvgCsg

Zg

Vs VvZs1 Zs2

ZL1 ZL2

Ground plane

Dielectric

Parallel traces over a ground plane

G (0V)

material

12

13

Stuck low

Coupled lines

Agressor line

Victim line

0.000 4.000 8.000 12.000 16.000 20.000Time (ns)

Voltage -V-

-3.000

-2.000

-1.000

0.000

1.000

2.000

3.000

4.000

5.000

6.000

7.000

Agressor line (source) - clock stimulus

Agressor line (load)

Victim line (source) - stuck lowVictim line (load)

0.010"

0.010"

0.010"

Signal

Power

Ground

Signal

0.008 0.008 0.0088.0 inches (20.3 cm) long, 72.1 ohmsPropagational delay: 1.126 nsOscillator: 66 MHz, 49% duty cycleCMOS, 3.3V, FastTraces: 0.008" wide and 0.008" apart (.20mm)Distance to reference plane: 0.010" (.25mm)



Far End Cross Talk Only appears in surface traces and scales with coupling length, inversely with rise time and depends on line to line spacing. Reduce it by shorter coupling lengths, longer rise time, larger spacing, or best of all, route in stripline. Near End Cross Talk Saturates with coupling length when coupling TD > ½ RT (rise time), predominantly affected by line to line spacing and can be reduced with lower dielectric constant. .

Common Forms of Crosstalk

14


Sample List of Design Techniques to Prevent Crosstalk

To prevent crosstalk within a PCB, the following design and layout techniques are useful. • Crosstalk will increase with a wider trace width as mutual capacitance, Cm, increases. • With long parallel traces, greater mutual inductance, Lm, is present. • Crosstalk also increases with faster edge rates and frequency of operation. 1. Group logic devices according to functionality. 2. Minimize routed distance between components. 3. Minimize parallel routed trace lengths. 4. Locate components away from I/O interconnects and areas susceptible to field

corruption. 5. Provide terminations for traces rich in harmonic energy. 6. Avoid routing of traces parallel to each other with adequate separation between the

tracks. 7. Route adjacent signal layers (either microstrip or stripline) orthogonally to prevents

capacitive and inductive coupling between two planes in parallel. 8. Reduce signal-to-ground reference distance separation. 9. Reduce trace impedance and/or signal drive level. 10. Isolate signal layers routed in the same axis by a solid planar (typical of backplane

designs).

15


Power and/or Return Plane Bounce

dtdIL = V discharge

rnpower/returnpower/retu

Q3

Q4 C

VCCLVCC

LGND Hi to Lo transition;C discharges

Lo to Hi transitionC charges

VOut

GND

Gate 2

ID

VGND (PCB)

L Vcc (PS)

DC power source

R trace ( PCB)

L GND )LGND (PS)

V GND

Gate 1

(PCB

16


Typical Bounce Waveform

Power and/or return bounce increases under the following conditions: • Capacitive loading is increased. • Load resistance is decreased. • Lead and trace inductance is increased. • Multiple gates (devices) switch simultaneously. Methods to minimize bounce include: 1. Load control - lower the capacitance and increase resistance. 2. Layout - minimize trace inductance during layout of the PCB. 3. Component packaging - use devices with a ground reference pin in the center of

the device (i.e., 4 nH instead of the corners 15 nH) or physically adjacent. Surface mount devices are preferred over through hole components for this reason.

4. Provide a separate connection for each power and return pin directly to their respective planes.

Ground bounce on ground plane

Digital switching pulse

positive bounce

negative bounce

17


Fundamentals of EMC

18


Definition of EMC Terms Electromagnetic Compatibility - The capability of electrical and electronic systems, equipment, and devices to operate in their intended electromagnetic environment within a defined margin of safety, and at design levels or performance, without suffering or causing unacceptable degradation as a result of electromagnetic interference. (ANSI C64.14-1992). Electromagnetic Interference - The lack of EMC, since the essence of interference is the

lack of compatibility. EMI is the process by which disruptive electromagnetic energy is transmitted from one electronic device to another via radiated or conducted paths (or both). In common usage, the term refers particularly to RF signals, but EMI can occur in the frequency range from "DC to daylight."

Radio Frequency - A frequency range containing coherent electromagnetic radiation of energy useful for communication purposes; roughly the range from 10 kHz to 100 GHz. This energy may be transmitted as a by-product of an electronic device’s operation. RF is transmitted through two basic modes: Radiated Emissions - The component of RF energy that is transmitted through a medium as

an electromagnetic field. RF energy is usually transmitted through free space, however, other modes of field transmission may occur.

Conducted Emissions - The component of RF energy that is transmitted through a medium

as a propagating wave, generally a wire or interconnect cables. LCI (Line Conducted Interference) refers to RF energy in a power cord or AC mains input cable. Conducted signals do not propagate as fields, but may propagate as conducted waves.

19


Susceptibility - A relative measure of a device or system’s propensity to be disrupted or damaged by EMI exposure. It is the lack of Immunity. Immunity - A relative measure of a device or system’s ability to withstand EMI exposure while maintaining a pre-defined performance level. Electrostatic Discharge - A transfer of electric charge between bodies of different electrostatic

potential in proximity or through direct contact. This definition is observed as a high-voltage pulse that may cause damage or loss of functionality to susceptible devices. Although lightning qualifies as a high-voltage pulse, the term ESD is generally applied to events of lesser amperage, and more specifically to events that are triggered by human beings. However, for the purposes of discussion, lightning is included in the ESD category because the protection techniques are very similar, although differing in magnitude.

Radiated Immunity - The relative ability of a product to withstand electromagnetic energy that

arrives via free-space propagation. Conducted Immunity - The relative ability of a product to withstand electromagnetic energy that

penetrates it through external cables, power cords and I/O interconnects. Containment - Preventing RF energy from exiting an enclosure, generally by shielding a product within a metal enclosure (Faraday cage or Gaussian structure) or by using a plastic housing with RF conductive paint. By reciprocity, we can also speak of containment as preventing RF energy from entering the enclosure. Suppression - The process of reducing or eliminating RF energy that exists without relying on a secondary method, such as a metal housing or chassis.

20


Basic Aspects and Elements of EMC

General rule of thumb when observing an EMC event Higher the frequency - coupling path is generally observed is radiated. Lower the frequency - coupling path generally observed is conducted. There are five aspects for an EMC event to be observed • Frequency - Where in the frequency spectrum is the problem observed? • Amplitude - How strong is the source of the RF energy and its potential to cause

harmful interference? • Time - Is the problem continuous (periodic signals) or does the problem exist only

during certain cycles of operation (e.g., disk drive write operation)? • Impedance - What is the impedance of both the source and receptor unit? • Dimensions - What are the physical dimensions of the device?

Three basic elements for an EMC event to be observed • There must be a source of energy. • There must be a receptor that is upset by this energy. • There must be a coupling path between the source and receptor for the

unwanted energy to transfer to. The propagation path may be either by radiated or conducted means.

21


Component Characteristics at RF Frequencies (The Hidden Schematic)

22


How RF Energy is Created – Maxwell Made Simple Maxwell’s four equations describe the relationship of electric and magnetic fields. Equations are derived from:

• Ampere’s Law • Faraday’s Law • Two from Gauss’s Law.

To overly simplify Maxwell, use Ohms law

Ohms Law (time domain-DC currents)

V = I R

Ohms Law (frequency domain-AC currents) Vrf = Irf Z

23


Right Hand Rule (Faraday’s Law)

Field or Flux Line

I (Current in the wire)

(Magnetic Flux)

Where is the electric field? In the direction of current flow.Only the magnetic field is shown as a flux line.

24


Maxwell's Equations

(For Reference Purposes)

totals

s

s

vs

I dst D JdlH

t D + J = H

Ampere) (from Current Electric :Law Fourth

dst B - = dlE

t B - = E

Faraday) (from Potential Electric :Law Third

0 dsB 0 B

Gauss) (from Flux Magnetic :Law Second

0 dv dsD = D

Gauss) (from Flux Electric :Law First

m

e

=•

∂∂

+=•∂∂

×∇

•∂∂

•∂∂

×∇

=•=ϕ=•∇

=ρ=•=ϕρ•∇

∫ ∫

∫ ∫

∫

∫∫

25

Electric and Magnetic Field Impedance

A plane wave is a combination of both electric and magnetic field components (Poynting vector). Fields propagate from a field source near the velocity of light. where µo = 4π∗10-7 H/m

εo = 8.85∗10-12 F/m Electric field component is measured in volts/meter (Note-voltage) Magnetic field component is in amps/meter (Note-current) The ratio of both electric field (E) to magnetic field (H) is identified as the "impedance" of free space. This impedance ratio is described by: Energy carried in the wave front is measured in Watts/meter2 (Note-power)


8oo 10 x3 = 1/=c εµ

ohms 377 = εμ = HE =Z

o

o o ×

26

(Note-resistance)


27

Plane waveZs = 377 ohms

Magnetic field predominates

Electric field predominates

Unknown field impedance

High source impedance

Low source impedanceW

ave

impe

danc

e, o

hms

Distance from source, normalized to λ/2π

far fieldnear field

101

10

0.1

100

1000

10k

transition region

d1H

dE ∝∝

1

3d1H

dE ∝∝ 2

1

2d1H

dE ∝∝ 3

1


Electric and Magnetic Field Representation

Dipole Antenna Loop Antenna

28


Closed Loop Circuit

If a continuous, conductive low impedance RF return path is not present (transmission line impedance is greater than 377 ohms), the return path will be free space (377 Ω at λ/4), which may be much less than the impedance of a localized RF return path.

Signal path

Return path

Switch

29


Radiated Emissions from a Closed Loop Circuit

Loop Area

Radiated energy

Return current

Signal path

This configuration is for a single- or double-sided PCB.For a multi-layer PCB, loop area is in the plane directly below the signal path.

30

Loop Area Between Circuits or Components – Different Layers


31


Return Current Path of Travel – Multilayer Assembly

High frequency operation Low frequency operation

Illustration provided courtesy: Dr. Howard Johnson

32

Circuit Return Current Simulation @ F=1 Hz Circuit Return Current Simulation @ F=100 kHz

Circuit Return Current Simulation @ F=5 GHz

Courtesy of Alexander Perez, Agilent Technologies


33

Loop Area Between Components

EMI is created from currents flowing between components. A small loop is one

whose dimensions are smaller than a quarter wavelength (λ/4) at a particular frequency of interest.

Maximum electric field strength from a loop in free space where A = loop area in cm2, f (MHz) is the frequency of Is, the source current in mA and r is the distance from the radiating element to the receiving antenna. Differential-mode radiation from a cable affixed to the PCB with a return reference

Common-mode radiation from a cable affixed to the PCB with a return reference


meter pervolts r1)IA(f 10131.6E s216

∗∗∗= −

meter pervolts r1)IA(f 10263E s216

∗∗∗= −

meter pervolts r1)IL(f 101.27E s

∗∗∗= −6

34


Common-Mode and Differential-Mode Currents

Differential-mode 1. Conveys desired information. 2. Does not cause interference as the fields generated oppose each other and cancel out.

Common-mode 1. The major source of cable radiation. 2. Contains no useful information. 3. Has no useful purpose. 4. Causes a system (traces, cables, etc.) to radiate as a monopole antenna.

I1

E~

I2

Z~

Noise sourcein load

I2

Common-mode currentI = I 1 + I2total

Differential-mode currentI = I 1 - I2total

E~ Z

Noise sourcein loadI1

~+ +

I2'

2 2

½ CM½ DM

½ CM½ DM

35


Summary on How EMI Is Developed Within the PCB 1. Current transients are created by the production of high frequency periodic

signals injected into the power and return distribution network. 2. An RF voltage drop develops across any impedance within a transmission

line. 3. Common-mode RF currents are created by this RF voltage drop on

unbalanced RF current return path. 4. Radiated emissions, created by these common-mode RF currents, are

observed on internal antenna structures by virtue of poor RF ground loop or return path control.

5. When any time-variant current is injected into a trace, magnetic flux is developed, which in turn creates an electric field. The combination of electric and magnetic fields create a propagating plane wave.

6. Lack of a proper RF current return path exacerbates EMI.

36


Basic EMC Suppression and Grounding Concepts

37


Grounding Hierarchy

Earth ground Equipotential

Chassis Reference point Reference plane

Return

In reality, there is only one grounding methodology

Single point

38


Different Types of Grounds • Signal Ground • Common Ground • Analog Ground • Digital Ground • Safety Ground • Noisy Ground • Quiet Ground • Earth Ground • Hardware Ground • Single-point Ground • Multi-point Ground • Shield Ground What about: RF Ground?

Often a ground reference may serve multiple needs, each with a different application.

39


Symbol Function

Circuit ground

Chassis ground

Digital returnD

AAnalog return

Application

Connection to the electrical ground structure

Connection to anynon-current carrying chassis

Path carrying the return ofa digital signal

Path carrying the return ofan analog signal

Common Ground Symbols

If there is more than one ground in a system, there will always be employment for EMC engineers

40

41

• Lower frequencies signals are “well behaved” • Higher frequencies create EMI problems

The principle of “Path of Least Inductance” applies to:

– Circuit grounding design and topologies – Power decoupling on PCBs – Transmission line layout and routing on PCBs

Few principles in EMC are as important as this principle for understanding the design of any printed circuit board

Path of Least Inductance Principle What the Rule Says


Defining “Ground”

Power/safety ground • Intended (neutral) and unintended (safety ground, generally the green wire) • 50/60/400 Hz

Lightning ground • A controlled path for lightning to reach the earth through a rod or metallic

structure • Generally a 1 MHz event and up to 100 kAmps per millisecond • Requires a high quality low ground resistance and inductance

Circuit/signal ground • Provides a return path for intended signal flow and for AC/DC power return;

mA to Amps • Requires a minimum low impedance path • Generally implemented as a ground plane or grids within a printed circuit

board


42

Defining “Ground” (continued)

EMI ground • Provides a controlled path for RF currents; DC to daylight, µA to Amps • Requires a minimum ground impedance

ESD ground • Provides a controlled path for ESD currents • 0.7-3 ns rise times, 100-300 MHz, 10-50 Amps

RF ground • Provides an RF return path for flux to return to its source • Covers the entire frequency spectrum • Requires minimum impedance for maximum current/flux flow



43

44

• A ground system topology is determined by – Signal characteristics – System dimensions – System-specific separation and isolation requirements – Electrical safety requirements

• Primary ground system topologies includes – A “floating” system – Single-point (“star) ground (SPG) – Multi-point ground – Hybrid ground

Grounding System Topologies



Three Primary Grounding Methodologies

Single-Point Grounding: Series and Parallel Multi-Point

1 2 3

21 3

I3I2I1

I = I1+I2+I3

SINGLE-POINT: SERIES CONNECTION

21 3

I3I2I1

SINGLE-POINT: PARALLEL CONNECTION

MULTI-POINT GROUNDING CONNECTIONS

L2L3L2L1

L3L2L1

L1L3

I3I2+I3

45


Single-Point: Best for use when signals are below 1 MHz. • Most sensitive circuit returns should be connected closest to the final

equipotential point. • Provides for greatest amount of loop currents to flow. • May be used between 1 and 10 MHz if longest conductor is < λ/20 of a

wavelength of highest frequency generated in the system. • Divided into two type: series and parallel. Multi-Point: Preferred for frequencies above 1 MHz. • Minimized loop currents and ground impedance of the planes. A good low

inductance ground is necessary for high-frequency digital logic circuits. Ground plane(s) provides a low inductance ground return for RF currents.

• Lead inductance must be kept extremely short. • Provides for maximum EMI suppression at the PCB level. Hybrid: For mixed technology products. • A combination of both single-point and multi-point grounding in the same

system

46


Resonance in a Multi-Point Ground

Printed circuit board.

Mounting plate or chassisMounting posts

Eddy currents

Internal power plane capacitance

Inductance in the power planes

ZZ I cm

Vcmby eddy currentsacross impedance(Z)post.

LC resonance in mounting posts

from mounting

produced

APPLICATION MODEL OF MULTIPOINT GROUNDING

ZtZ t cm2Vcm2V

cmI

ZB

Vcm1

Chassis

ELECTROMAGNETIC MODEL OF MULTI-POINT GROUNDING

V cm2 is reduced by the mounting posts (ground stitch locations).Resonance is thus controlled, along with enhanced RF suppression.

47


RF Current Density Distribution

where I(d) = signal current density, (A/inch or A/cm) Io = total current (A) H = height of the trace above the ground plane (in. or cm) D = perpendicular distance from the center line of the trace (in. or cm)

21

1

+

⋅

HDH

I = dI o

π)(

48


Ground Slots Created with Through-Hole Components

Equivalent circuit showing inductance in the returnpath. This inductance is approximately 1 nH/cm.

I.C.I.C.

Through-holes (multiple holes in one straight line)creates a slot in the ground plane. Return currentmust travel around the slot.

Optimal method of routing traces if through-holeThrough-holes (multiple holes spaced apart)

components must be used.

Signal trace

GroundPlane

RF return current

Signal trace

Return current in ground plane

E E = L dI/dT = plane radiation

49


Functional Partitioning

Slow speed I/O

CPU and clock logic

interconnects

Memory

Video Audio

Memory section

Power supply

Adapter cardsSupport logic

Analog processing

50


Bypassing and Decoupling (Power Distribution Networks)

51


The Need for Optimal Power Distribution

• Provides a stable voltage reference between components to ensure functional operation

• Distribute optimal power to all logic devices to minimize planar bounce Key items of concern Use low impedance connections between logic gates: • The impedance between power pins on gates should be just as low as the

impedance between the return pins on the same device • A low impedance path must always be provided between power and return

Input+

-

+

-

+

-

Load C

Inductance in the Power Path

Charging current for capacitor C flows throughthe inductance of the power distribution network

I

Signal

Inductance in the Return Path

52


Power Distribution Networks as Transmission Lines

Power distribution networks can be represented as a two conductor transmission line with a defined characteristic impedance and propagation delay.

Cx dx

Power

Return

Lx dx

+

- CC C C C

Real-Life Power Distribution Network – Multiple Loads

Power

Return

+

- CC C C C

Ideal Power Distribution Network – Multiple Loads

53


Primary Requirements for Enhanced Power Distribution

The amplitude of power supply transients are directly proportional to the characteristic impedance of the power distribution system, Z0: To reduce Z0

– Reduce inductance – Increase capacitance

Both are achieved by – Reduction of loop area between conductors (less inductance) – Placing conductors as close together as possible (greater capacitance) – Increase of conductors’ width (less inductance and greater capacitance, with respect to another conductor)

(x)

(x)

o

oo

IV

CL = Z =

54


Defining Capacitor Usage

Capacitors are used for one of three primary functions. Bulk Used to maintain constant DC voltage and current levels on a global basis

due to IR drops within the power distribution network, and to recharge the distribution network (i.e., planes) cause by dI/dt consumption from components (typically 1-100 µF).

Bypassing Diverts or steers RF currents from one location to another. Shunts

unwanted common-mode RF currents from components or cables from entering susceptible areas in addition to providing other functions of filtering (bandwidth limited).

Decoupling Provides a localized source of DC power, and are particularly useful in

reducing peak current surges propagated across the board. Prevents RF currents from being injected into the power distribution network during digital component edge transitions.

• Switching transient capacitance (0.01 µF) – Used to supply short-term energy demands of the silicon during switching states. • Line charging capacitance (0.1 µF) – Used to charge capacitive transmission lines as well as supplying current necessary for the driver.

55


Effective Range of Decoupling Systems and Target Impedance

(Artwork provided courtesy – Ansoft Corporation)

56

1. Supply current bursts for fast switching circuits (power delivery system issues-PDS) to prevent power and return bounce.

2. To lower the impedance of the power delivery system and prevent energy transference from one circuit to another sharing the same voltage levels.

3. To provide an AC shunt connection between power and return planes for RF signal return current (layer jumping) to ensure flux cancellation, which minimizes radiated emissions and prevents crosstalk between traces.

4. Controls EMI internal to the PCB by reducing the injection of common-mode current into the power distribution system. An RF modulating plane will propagate RF currents throughout the entire assembly causing disruption to all components sharing that voltage rail.

Basic Functions of Decoupling Capacitor Use


57


Capacitance of the power and ground planes is defined by: where Cpp = capacitance of parallel plates (pF) εr = dielectric constant of the board material A = area between the parallel plates (square inches or cm) D = distance spacing between the plates (inches or cm) k = conversion constant (0.2249 for inches, 0.884 for cm)

DAkC r

ppε

=

A

D

εr

Calculating Power and Return Plane Capacitance

58

Self-resonant frequency Through-hole capacitors

0.001

0.01

0.1

1

10

100

1000

10000

1.00 10.00 100.00 1000.00

Impedance (Ohms)

Frequency (MHz)

100 pF

0.001 uF

0.01 uF

0.1 uF

Capacitors and Resonance

1/4 inch or 0.64 cm leads – 15 nH


59

Self Resonant Frequency - SMT Capacitors

0.001

0.01

0.1

1

10

100

1000

10000

1 10 100 1000

Impedance (Ohms)

100 pF

0.01 uF

0.1 uF

Frequency (MHz)

0.001 uF


60

Effects of Capacitors in Parallel – Different Values


61

Effects of Capacitors in Parallel – Same Capacitor Values

How to calculate number of capacitors with the same capacitive value in parallel: (Plot provided courtesy AVX Corp.)

22 1

ω−

ω+

=

=

=

∗=

nCnESL

nESRZ

nESRESR

nLL

CnC

total

otal

total


62

Power and Ground Plane Capacitance

Cplane

L capLboard

C board C cap

Z (ohms)

Frequency

Decoupling

Bare board

0.1

1

10

100

Frequency

hms

oZ Z

ESL

C

ESR

|Z|=1

2 π f C(f < f )s

Discrete decoupling capacitor

Frequency

hms

oZ

Bare board without decoupling

Power and ground plane configuration(Bare board configuration)

Z

ESL 0

C

|Z|=1

2 π f C

≈


63

Conflicting Rules for PCB Decoupling

Use small-valued capacitors for high-frequency decoupling

Use 0.01 µF for local decoupling

Locate capacitors near thepower pins of active devices

Locate capacitors near theground pins of active devices

Avoid capacitors with a low ESR

Use capacitors with a low ESR!

Use 0.001 µF for local decouplingLocate of the decoupling capacitors is not relevant

Use the largest valued capacitors you can find in a given package size

Local decouping capacitors should have a range of values from 100 pf to 1 µF

Never put traces on decoupling capacitors

List created by Todd Hubing


64


Summary - Guidelines for Power Distribution Networks 1. Determine board impedance requirements. To maximize total, plane impedance must be held below a maximum level.

Calculate this value by estimating maximum current required by active devices and dividing that value into the maximum noise margin that can be tolerated.

2. Establish total amount of capacitance required. More capacitance results in lower power bus impedance. When using embedded

capacitance, the value should be greater than or equal to the amount of discrete components it is replacing with bulk capacitors remaining. Embedded capacitance usually replaces discrete (local) decoupling capacitors (i.e., capacitors with a value of 0.01 µF or smaller).

3. Ensure resonances are damped. When board dimensions exceed ½ wavelength, power bus resonances may occur,

causing EMI and signal integrity problems. Damp resonances using resistive elements, or space power and ground planes at a distance less than 0.010 mils (0.0025 mm) apart.

4. Estimate total board impedance. This can only be achieved using sophisticated, complex numerical modeling

software. Planes must be modeled as finite radial transmission lines.

65


Interconnects and I/O

66


Introduction to Interconnects and I/O Most RF emissions in I/O circuitry is generated from a combination of • Common-mode RF coupling inside I/O interface logic components • Power plane noise coupled into I/O circuits and cables • Clock signals coupling into I/O cables; both conductive and radiated modes • Lack of data line filtering on connectors and signals traces (common-mode

and differential-mode) • Improper connection of chassis, signal, frame, digital and analog ground

reference • Use of improper I/O connectors (plastic versus metal or unshielded versus shielded) I/O control logic must be physically located as close to the I/O connector as possible to minimize trace lengths and to minimize the risk that these signals will receive coupling from other signals. Filtering of data signals is often required. This filter is placed between the driver/receiver and connector.

67


Partitioning Functional Subsystems A group of components along with their respective support circuitry performing a common function. Quiet Areas Sections physically isolated from other functional areas to prevents noise sources from corrupting susceptible circuits in the quiet zone. Internal Radiated Noise Coupling Radiated RF coupling may occur between different functional subsections. To prevent this coupling, a fence or shield barrier may be required. A fence is a metal barrier secured to the ground plane(s) at intervals appropriate for the highest frequencies anticipated (at λ/20 wavelength intervals) and tall enough in height to prevent direct line RF radiated field coupling.

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Isolation (Moating)

L

Isolation transformer

Moat

Data line filter

I/O connector

moated area. Do not use an inductorFerrite bead-on-lead to bridge power (only) into theGround trace, if required, 3x wider than power trace

DLF(common-mode choke)

Optional decoupling capacitor, usually necessaryto ground, not across the moat

Absence of voltage and ground planes(to minimizecoupling capacitanceacross the DLF)

Best location for ground connection

69


MoatData line filter

Isolation transformer or optical isolators

Absence of voltage and ground planes

DLF

Shield-shellground connectionto chassis

I/O connector

Power

Ground

Decoupling capacitorsFerrite filter (with fuse)

Non-isolatedpower and shieldgrounds to chassis

70


Bridging

I/O

MoatConnection to chassis ground

Bridge in moat

Vcc

VccVcc

Vcc

Vcc

Vcc

Ferrite bead-on-lead for optional power, if required, over a separate moat for power plane. (dotted line).

Vcc connector

Location ofoptional grounds to chassis

71


Image Plane or Moat Violation

Signal Trace

Large looparea allowsfor common-mode RF energy toexist due to lack of an image planealong the entire traceroute.

Moat violation

Signal Return

Correct use of moating

72


Solution to All EMC Problems

73

mark montrose presentation pcb design-4 hours

Documents

wileyieee press

signal integrity problems

signal quality

transmitted signal

signal integrity concerns

loss of signal amplitude

kinds of design engineers

nonideal return path